* [PATCH 0/5] cxgbe: add features to CXGBE PMD
@ 2016-05-06 7:43 Rahul Lakkireddy
2016-05-06 7:43 ` [PATCH 1/5] pci: fix access to PCI config space in bsd Rahul Lakkireddy
` (5 more replies)
0 siblings, 6 replies; 9+ messages in thread
From: Rahul Lakkireddy @ 2016-05-06 7:43 UTC (permalink / raw)
To: dev; +Cc: Kumar Sanghvi, Nirranjan Kirubaharan
This patch series add some features to CXGBE PMD.
Patch 1 fixes a bug where reading/writing PCI config space in BSD fails
with EPERM due to missing write permission when opening /dev/pci/.
Patch 2 adds support to access PCI config space for CXGBE PMD.
Patch 3 programs PCIe completion timeout to 4 sec.
Patch 4 adds support to get/set EEPROM.
Patch 5 adds support to get register dump.
Rahul Lakkireddy (5):
pci: fix access to PCI config space in bsd
cxgbe: add support to access PCI config space
cxgbe: set default PCIe completion timeout
cxgbe: add support to get/set EEPROM
cxgbe: add support to get register dump
doc/guides/nics/overview.rst | 4 +-
drivers/net/cxgbe/base/adapter.h | 138 ++++-
drivers/net/cxgbe/base/common.h | 11 +-
drivers/net/cxgbe/base/t4_hw.c | 1047 ++++++++++++++++++++++++++++++++++-
drivers/net/cxgbe/base/t4_hw.h | 5 +-
drivers/net/cxgbe/cxgbe_ethdev.c | 167 ++++++
lib/librte_eal/bsdapp/eal/eal_pci.c | 4 +-
7 files changed, 1368 insertions(+), 8 deletions(-)
--
2.5.3
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 1/5] pci: fix access to PCI config space in bsd 2016-05-06 7:43 [PATCH 0/5] cxgbe: add features to CXGBE PMD Rahul Lakkireddy @ 2016-05-06 7:43 ` Rahul Lakkireddy 2016-05-31 16:20 ` Bruce Richardson 2016-05-06 7:43 ` [PATCH 2/5] cxgbe: add support to access PCI config space Rahul Lakkireddy ` (4 subsequent siblings) 5 siblings, 1 reply; 9+ messages in thread From: Rahul Lakkireddy @ 2016-05-06 7:43 UTC (permalink / raw) To: dev; +Cc: Kumar Sanghvi, Nirranjan Kirubaharan PCIOCREAD and PCIOCWRITE ioctls to read/write PCI config space fail with EPERM due to missing write permission. Fix by opening /dev/pci/ with O_RDWR instead. Fixes: 632b2d1deeed ("eal: provide functions to access PCI config") Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com> --- lib/librte_eal/bsdapp/eal/eal_pci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/librte_eal/bsdapp/eal/eal_pci.c b/lib/librte_eal/bsdapp/eal/eal_pci.c index 2d16d78..82330be 100644 --- a/lib/librte_eal/bsdapp/eal/eal_pci.c +++ b/lib/librte_eal/bsdapp/eal/eal_pci.c @@ -422,7 +422,7 @@ int rte_eal_pci_read_config(const struct rte_pci_device *dev, goto error; } - fd = open("/dev/pci", O_RDONLY); + fd = open("/dev/pci", O_RDWR); if (fd < 0) { RTE_LOG(ERR, EAL, "%s(): error opening /dev/pci\n", __func__); goto error; @@ -466,7 +466,7 @@ int rte_eal_pci_write_config(const struct rte_pci_device *dev, memcpy(&pi.pi_data, buf, len); - fd = open("/dev/pci", O_RDONLY); + fd = open("/dev/pci", O_RDWR); if (fd < 0) { RTE_LOG(ERR, EAL, "%s(): error opening /dev/pci\n", __func__); goto error; -- 2.5.3 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 1/5] pci: fix access to PCI config space in bsd 2016-05-06 7:43 ` [PATCH 1/5] pci: fix access to PCI config space in bsd Rahul Lakkireddy @ 2016-05-31 16:20 ` Bruce Richardson 2016-06-01 8:34 ` Rahul Lakkireddy 0 siblings, 1 reply; 9+ messages in thread From: Bruce Richardson @ 2016-05-31 16:20 UTC (permalink / raw) To: Rahul Lakkireddy; +Cc: dev, Kumar Sanghvi, Nirranjan Kirubaharan On Fri, May 06, 2016 at 01:13:15PM +0530, Rahul Lakkireddy wrote: > PCIOCREAD and PCIOCWRITE ioctls to read/write PCI config space fail > with EPERM due to missing write permission. Fix by opening /dev/pci/ > with O_RDWR instead. > > Fixes: 632b2d1deeed ("eal: provide functions to access PCI config") > > Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> > Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com> > --- > lib/librte_eal/bsdapp/eal/eal_pci.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/lib/librte_eal/bsdapp/eal/eal_pci.c b/lib/librte_eal/bsdapp/eal/eal_pci.c > index 2d16d78..82330be 100644 > --- a/lib/librte_eal/bsdapp/eal/eal_pci.c > +++ b/lib/librte_eal/bsdapp/eal/eal_pci.c > @@ -422,7 +422,7 @@ int rte_eal_pci_read_config(const struct rte_pci_device *dev, > goto error; > } > > - fd = open("/dev/pci", O_RDONLY); > + fd = open("/dev/pci", O_RDWR); > if (fd < 0) { > RTE_LOG(ERR, EAL, "%s(): error opening /dev/pci\n", __func__); > goto error; > @@ -466,7 +466,7 @@ int rte_eal_pci_write_config(const struct rte_pci_device *dev, > > memcpy(&pi.pi_data, buf, len); > > - fd = open("/dev/pci", O_RDONLY); > + fd = open("/dev/pci", O_RDWR); > if (fd < 0) { > RTE_LOG(ERR, EAL, "%s(): error opening /dev/pci\n", __func__); > goto error; > -- Does the read function as well as the write one need O_RDWR permissions? There is also an ioctl in rte_eal_pci_scan which operates on a RDONLY file descriptor. Does that need to be modified also? /Bruce ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/5] pci: fix access to PCI config space in bsd 2016-05-31 16:20 ` Bruce Richardson @ 2016-06-01 8:34 ` Rahul Lakkireddy 0 siblings, 0 replies; 9+ messages in thread From: Rahul Lakkireddy @ 2016-06-01 8:34 UTC (permalink / raw) To: Bruce Richardson; +Cc: dev@dpdk.org, Kumar A S, Nirranjan Kirubaharan Hi Bruce, On Tuesday, May 05/31/16, 2016 at 09:20:13 -0700, Bruce Richardson wrote: > On Fri, May 06, 2016 at 01:13:15PM +0530, Rahul Lakkireddy wrote: > > PCIOCREAD and PCIOCWRITE ioctls to read/write PCI config space fail > > with EPERM due to missing write permission. Fix by opening /dev/pci/ > > with O_RDWR instead. > > > > Fixes: 632b2d1deeed ("eal: provide functions to access PCI config") > > > > Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> > > Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com> > > --- > > lib/librte_eal/bsdapp/eal/eal_pci.c | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/lib/librte_eal/bsdapp/eal/eal_pci.c b/lib/librte_eal/bsdapp/eal/eal_pci.c > > index 2d16d78..82330be 100644 > > --- a/lib/librte_eal/bsdapp/eal/eal_pci.c > > +++ b/lib/librte_eal/bsdapp/eal/eal_pci.c > > @@ -422,7 +422,7 @@ int rte_eal_pci_read_config(const struct rte_pci_device *dev, > > goto error; > > } > > > > - fd = open("/dev/pci", O_RDONLY); > > + fd = open("/dev/pci", O_RDWR); > > if (fd < 0) { > > RTE_LOG(ERR, EAL, "%s(): error opening /dev/pci\n", __func__); > > goto error; > > @@ -466,7 +466,7 @@ int rte_eal_pci_write_config(const struct rte_pci_device *dev, > > > > memcpy(&pi.pi_data, buf, len); > > > > - fd = open("/dev/pci", O_RDONLY); > > + fd = open("/dev/pci", O_RDWR); > > if (fd < 0) { > > RTE_LOG(ERR, EAL, "%s(): error opening /dev/pci\n", __func__); > > goto error; > > -- > Does the read function as well as the write one need O_RDWR permissions? There > is also an ioctl in rte_eal_pci_scan which operates on a RDONLY file descriptor. > Does that need to be modified also? Yes, both PCIOCREAD and PCIOCWRITE ioctls seem to require write permission. Otherwise, pci_ioctl [1] seems to return EPERM. On the other hand, the PCIOCGETCONF ioctl used in rte_eal_pci_scan doesn't seem to require a write permission. So, it should be fine to leave it as RDONLY. [1] https://svnweb.freebsd.org/base/release/10.3.0/sys/dev/pci/pci_user.c?revision=297553&view=markup#l493 Thanks, Rahul ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 2/5] cxgbe: add support to access PCI config space 2016-05-06 7:43 [PATCH 0/5] cxgbe: add features to CXGBE PMD Rahul Lakkireddy 2016-05-06 7:43 ` [PATCH 1/5] pci: fix access to PCI config space in bsd Rahul Lakkireddy @ 2016-05-06 7:43 ` Rahul Lakkireddy 2016-05-06 7:43 ` [PATCH 3/5] cxgbe: set default PCIe completion timeout Rahul Lakkireddy ` (3 subsequent siblings) 5 siblings, 0 replies; 9+ messages in thread From: Rahul Lakkireddy @ 2016-05-06 7:43 UTC (permalink / raw) To: dev; +Cc: Kumar Sanghvi, Nirranjan Kirubaharan Add helper functions to access PCI config space. Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com> --- drivers/net/cxgbe/base/adapter.h | 129 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 128 insertions(+), 1 deletion(-) diff --git a/drivers/net/cxgbe/base/adapter.h b/drivers/net/cxgbe/base/adapter.h index a5225c0..af34721 100644 --- a/drivers/net/cxgbe/base/adapter.h +++ b/drivers/net/cxgbe/base/adapter.h @@ -1,7 +1,7 @@ /*- * BSD LICENSE * - * Copyright(c) 2014-2015 Chelsio Communications. + * Copyright(c) 2014-2016 Chelsio Communications. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -427,6 +427,133 @@ static inline void t4_write_reg64(struct adapter *adapter, u32 reg_addr, CXGBE_WRITE_REG64(adapter, reg_addr, val); } +#define PCI_STATUS 0x06 /* 16 bits */ +#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ +#define PCI_CAPABILITY_LIST 0x34 +/* Offset of first capability list entry */ +#define PCI_CAP_LIST_ID 0 /* Capability ID */ +#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ + +/** + * t4_os_pci_write_cfg4 - 32-bit write to PCI config space + * @adapter: the adapter + * @addr: the register address + * @val: the value to write + * + * Write a 32-bit value into the given register in PCI config space. + */ +static inline void t4_os_pci_write_cfg4(struct adapter *adapter, size_t addr, + off_t val) +{ + u32 val32 = val; + + if (rte_eal_pci_write_config(adapter->pdev, &val32, sizeof(val32), + addr) < 0) + dev_err(adapter, "Can't write to PCI config space\n"); +} + +/** + * t4_os_pci_read_cfg4 - read a 32-bit value from PCI config space + * @adapter: the adapter + * @addr: the register address + * @val: where to store the value read + * + * Read a 32-bit value from the given register in PCI config space. + */ +static inline void t4_os_pci_read_cfg4(struct adapter *adapter, size_t addr, + u32 *val) +{ + if (rte_eal_pci_read_config(adapter->pdev, val, sizeof(*val), + addr) < 0) + dev_err(adapter, "Can't read from PCI config space\n"); +} + +/** + * t4_os_pci_write_cfg2 - 16-bit write to PCI config space + * @adapter: the adapter + * @addr: the register address + * @val: the value to write + * + * Write a 16-bit value into the given register in PCI config space. + */ +static inline void t4_os_pci_write_cfg2(struct adapter *adapter, size_t addr, + off_t val) +{ + u16 val16 = val; + + if (rte_eal_pci_write_config(adapter->pdev, &val16, sizeof(val16), + addr) < 0) + dev_err(adapter, "Can't write to PCI config space\n"); +} + +/** + * t4_os_pci_read_cfg2 - read a 16-bit value from PCI config space + * @adapter: the adapter + * @addr: the register address + * @val: where to store the value read + * + * Read a 16-bit value from the given register in PCI config space. + */ +static inline void t4_os_pci_read_cfg2(struct adapter *adapter, size_t addr, + u16 *val) +{ + if (rte_eal_pci_read_config(adapter->pdev, val, sizeof(*val), + addr) < 0) + dev_err(adapter, "Can't read from PCI config space\n"); +} + +/** + * t4_os_pci_read_cfg - read a 8-bit value from PCI config space + * @adapter: the adapter + * @addr: the register address + * @val: where to store the value read + * + * Read a 8-bit value from the given register in PCI config space. + */ +static inline void t4_os_pci_read_cfg(struct adapter *adapter, size_t addr, + u8 *val) +{ + if (rte_eal_pci_read_config(adapter->pdev, val, sizeof(*val), + addr) < 0) + dev_err(adapter, "Can't read from PCI config space\n"); +} + +/** + * t4_os_find_pci_capability - lookup a capability in the PCI capability list + * @adapter: the adapter + * @cap: the capability + * + * Return the address of the given capability within the PCI capability list. + */ +static inline int t4_os_find_pci_capability(struct adapter *adapter, int cap) +{ + u16 status; + int ttl = 48; + u8 pos = 0; + u8 id = 0; + + t4_os_pci_read_cfg2(adapter, PCI_STATUS, &status); + if (!(status & PCI_STATUS_CAP_LIST)) { + dev_err(adapter, "PCIe capability reading failed\n"); + return -1; + } + + t4_os_pci_read_cfg(adapter, PCI_CAPABILITY_LIST, &pos); + while (ttl-- && pos >= 0x40) { + pos &= ~3; + t4_os_pci_read_cfg(adapter, (pos + PCI_CAP_LIST_ID), &id); + + if (id == 0xff) + break; + + if (id == cap) + return (int)pos; + + t4_os_pci_read_cfg(adapter, (pos + PCI_CAP_LIST_NEXT), &pos); + } + return 0; +} + /** * t4_os_set_hw_addr - store a port's MAC address in SW * @adapter: the adapter -- 2.5.3 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 3/5] cxgbe: set default PCIe completion timeout 2016-05-06 7:43 [PATCH 0/5] cxgbe: add features to CXGBE PMD Rahul Lakkireddy 2016-05-06 7:43 ` [PATCH 1/5] pci: fix access to PCI config space in bsd Rahul Lakkireddy 2016-05-06 7:43 ` [PATCH 2/5] cxgbe: add support to access PCI config space Rahul Lakkireddy @ 2016-05-06 7:43 ` Rahul Lakkireddy 2016-05-06 7:43 ` [PATCH 4/5] cxgbe: add support to get/set EEPROM Rahul Lakkireddy ` (2 subsequent siblings) 5 siblings, 0 replies; 9+ messages in thread From: Rahul Lakkireddy @ 2016-05-06 7:43 UTC (permalink / raw) To: dev; +Cc: Kumar Sanghvi, Nirranjan Kirubaharan Program the PCIe completion timeout to 4 sec to give enough time to allow completions to be received successfully in some older systems. Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com> --- drivers/net/cxgbe/base/adapter.h | 2 ++ drivers/net/cxgbe/base/t4_hw.c | 19 ++++++++++++++++++- 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/net/cxgbe/base/adapter.h b/drivers/net/cxgbe/base/adapter.h index af34721..73e7aca 100644 --- a/drivers/net/cxgbe/base/adapter.h +++ b/drivers/net/cxgbe/base/adapter.h @@ -431,8 +431,10 @@ static inline void t4_write_reg64(struct adapter *adapter, u32 reg_addr, #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ +#define PCI_CAP_ID_EXP 0x10 /* PCI Express */ #define PCI_CAP_LIST_ID 0 /* Capability ID */ #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ +#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */ /** * t4_os_pci_write_cfg4 - 32-bit write to PCI config space diff --git a/drivers/net/cxgbe/base/t4_hw.c b/drivers/net/cxgbe/base/t4_hw.c index 79af806..7882f9a 100644 --- a/drivers/net/cxgbe/base/t4_hw.c +++ b/drivers/net/cxgbe/base/t4_hw.c @@ -1,7 +1,7 @@ /*- * BSD LICENSE * - * Copyright(c) 2014-2015 Chelsio Communications. + * Copyright(c) 2014-2016 Chelsio Communications. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -2326,6 +2326,21 @@ int t4_get_flash_params(struct adapter *adapter) return 0; } +static void set_pcie_completion_timeout(struct adapter *adapter, + u8 range) +{ + u32 pcie_cap; + u16 val; + + pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP); + if (pcie_cap) { + t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val); + val &= 0xfff0; + val |= range; + t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val); + } +} + /** * t4_prep_adapter - prepare SW and HW for operation * @adapter: the adapter @@ -2384,6 +2399,8 @@ int t4_prep_adapter(struct adapter *adapter) adapter->params.portvec = 1; adapter->params.vpd.cclk = 50000; + /* Set pci completion timeout value to 4 seconds. */ + set_pcie_completion_timeout(adapter, 0xd); return 0; } -- 2.5.3 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 4/5] cxgbe: add support to get/set EEPROM 2016-05-06 7:43 [PATCH 0/5] cxgbe: add features to CXGBE PMD Rahul Lakkireddy ` (2 preceding siblings ...) 2016-05-06 7:43 ` [PATCH 3/5] cxgbe: set default PCIe completion timeout Rahul Lakkireddy @ 2016-05-06 7:43 ` Rahul Lakkireddy 2016-05-06 7:43 ` [PATCH 5/5] cxgbe: add support to get register dump Rahul Lakkireddy 2016-06-02 14:43 ` [PATCH 0/5] cxgbe: add features to CXGBE PMD Bruce Richardson 5 siblings, 0 replies; 9+ messages in thread From: Rahul Lakkireddy @ 2016-05-06 7:43 UTC (permalink / raw) To: dev; +Cc: Kumar Sanghvi, Nirranjan Kirubaharan Add operations to get/set EEPROM. Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com> --- doc/guides/nics/overview.rst | 2 +- drivers/net/cxgbe/base/adapter.h | 7 ++ drivers/net/cxgbe/base/common.h | 5 +- drivers/net/cxgbe/base/t4_hw.c | 182 +++++++++++++++++++++++++++++++++++++++ drivers/net/cxgbe/base/t4_hw.h | 5 +- drivers/net/cxgbe/cxgbe_ethdev.c | 142 ++++++++++++++++++++++++++++++ 6 files changed, 340 insertions(+), 3 deletions(-) diff --git a/doc/guides/nics/overview.rst b/doc/guides/nics/overview.rst index f08039e..afaac28 100644 --- a/doc/guides/nics/overview.rst +++ b/doc/guides/nics/overview.rst @@ -130,7 +130,7 @@ Most of these differences are summarized below. Basic stats Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Extended stats Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Stats per queue Y Y Y Y Y Y Y Y Y Y Y Y - EEPROM dump Y Y Y + EEPROM dump Y Y Y Y Registers dump Y Y Y Y Y Y Multiprocess aware Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y BSD nic_uio Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y diff --git a/drivers/net/cxgbe/base/adapter.h b/drivers/net/cxgbe/base/adapter.h index 73e7aca..5e3bd50 100644 --- a/drivers/net/cxgbe/base/adapter.h +++ b/drivers/net/cxgbe/base/adapter.h @@ -318,6 +318,9 @@ struct adapter { unsigned int mbox; /* associated mailbox */ unsigned int pf; /* associated physical function id */ + unsigned int vpd_busy; + unsigned int vpd_flag; + int use_unpacked_mode; /* unpacked rx mode state */ }; @@ -435,6 +438,10 @@ static inline void t4_write_reg64(struct adapter *adapter, u32 reg_addr, #define PCI_CAP_LIST_ID 0 /* Capability ID */ #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */ +#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ +#define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */ +#define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */ +#define PCI_VPD_DATA 4 /* 32-bits of data returned here */ /** * t4_os_pci_write_cfg4 - 32-bit write to PCI config space diff --git a/drivers/net/cxgbe/base/common.h b/drivers/net/cxgbe/base/common.h index cf2e82d..853edd8 100644 --- a/drivers/net/cxgbe/base/common.h +++ b/drivers/net/cxgbe/base/common.h @@ -1,7 +1,7 @@ /*- * BSD LICENSE * - * Copyright(c) 2014-2015 Chelsio Communications. + * Copyright(c) 2014-2016 Chelsio Communications. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -398,4 +398,7 @@ int t4_init_sge_params(struct adapter *adapter); int t4_init_tp_params(struct adapter *adap); int t4_filter_field_shift(const struct adapter *adap, unsigned int filter_sel); int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); +int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data); +int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data); +int t4_seeprom_wp(struct adapter *adapter, int enable); #endif /* __CHELSIO_COMMON_H */ diff --git a/drivers/net/cxgbe/base/t4_hw.c b/drivers/net/cxgbe/base/t4_hw.c index 7882f9a..ff8594a 100644 --- a/drivers/net/cxgbe/base/t4_hw.c +++ b/drivers/net/cxgbe/base/t4_hw.c @@ -569,6 +569,185 @@ int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, FW_CMD_MAX_TIMEOUT); } +/* EEPROM reads take a few tens of us while writes can take a bit over 5 ms. */ +#define EEPROM_DELAY 10 /* 10us per poll spin */ +#define EEPROM_MAX_POLL 5000 /* x 5000 == 50ms */ + +#define EEPROM_STAT_ADDR 0x7bfc + +/** + * Small utility function to wait till any outstanding VPD Access is complete. + * We have a per-adapter state variable "VPD Busy" to indicate when we have a + * VPD Access in flight. This allows us to handle the problem of having a + * previous VPD Access time out and prevent an attempt to inject a new VPD + * Request before any in-flight VPD request has completed. + */ +static int t4_seeprom_wait(struct adapter *adapter) +{ + unsigned int base = adapter->params.pci.vpd_cap_addr; + int max_poll; + + /* If no VPD Access is in flight, we can just return success right + * away. + */ + if (!adapter->vpd_busy) + return 0; + + /* Poll the VPD Capability Address/Flag register waiting for it + * to indicate that the operation is complete. + */ + max_poll = EEPROM_MAX_POLL; + do { + u16 val; + + udelay(EEPROM_DELAY); + t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val); + + /* If the operation is complete, mark the VPD as no longer + * busy and return success. + */ + if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) { + adapter->vpd_busy = 0; + return 0; + } + } while (--max_poll); + + /* Failure! Note that we leave the VPD Busy status set in order to + * avoid pushing a new VPD Access request into the VPD Capability till + * the current operation eventually succeeds. It's a bug to issue a + * new request when an existing request is in flight and will result + * in corrupt hardware state. + */ + return -ETIMEDOUT; +} + +/** + * t4_seeprom_read - read a serial EEPROM location + * @adapter: adapter to read + * @addr: EEPROM virtual address + * @data: where to store the read data + * + * Read a 32-bit word from a location in serial EEPROM using the card's PCI + * VPD capability. Note that this function must be called with a virtual + * address. + */ +int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data) +{ + unsigned int base = adapter->params.pci.vpd_cap_addr; + int ret; + + /* VPD Accesses must alway be 4-byte aligned! + */ + if (addr >= EEPROMVSIZE || (addr & 3)) + return -EINVAL; + + /* Wait for any previous operation which may still be in flight to + * complete. + */ + ret = t4_seeprom_wait(adapter); + if (ret) { + dev_err(adapter, "VPD still busy from previous operation\n"); + return ret; + } + + /* Issue our new VPD Read request, mark the VPD as being busy and wait + * for our request to complete. If it doesn't complete, note the + * error and return it to our caller. Note that we do not reset the + * VPD Busy status! + */ + t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr); + adapter->vpd_busy = 1; + adapter->vpd_flag = PCI_VPD_ADDR_F; + ret = t4_seeprom_wait(adapter); + if (ret) { + dev_err(adapter, "VPD read of address %#x failed\n", addr); + return ret; + } + + /* Grab the returned data, swizzle it into our endianness and + * return success. + */ + t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data); + *data = le32_to_cpu(*data); + return 0; +} + +/** + * t4_seeprom_write - write a serial EEPROM location + * @adapter: adapter to write + * @addr: virtual EEPROM address + * @data: value to write + * + * Write a 32-bit word to a location in serial EEPROM using the card's PCI + * VPD capability. Note that this function must be called with a virtual + * address. + */ +int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data) +{ + unsigned int base = adapter->params.pci.vpd_cap_addr; + int ret; + u32 stats_reg; + int max_poll; + + /* VPD Accesses must alway be 4-byte aligned! + */ + if (addr >= EEPROMVSIZE || (addr & 3)) + return -EINVAL; + + /* Wait for any previous operation which may still be in flight to + * complete. + */ + ret = t4_seeprom_wait(adapter); + if (ret) { + dev_err(adapter, "VPD still busy from previous operation\n"); + return ret; + } + + /* Issue our new VPD Read request, mark the VPD as being busy and wait + * for our request to complete. If it doesn't complete, note the + * error and return it to our caller. Note that we do not reset the + * VPD Busy status! + */ + t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, + cpu_to_le32(data)); + t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, + (u16)addr | PCI_VPD_ADDR_F); + adapter->vpd_busy = 1; + adapter->vpd_flag = 0; + ret = t4_seeprom_wait(adapter); + if (ret) { + dev_err(adapter, "VPD write of address %#x failed\n", addr); + return ret; + } + + /* Reset PCI_VPD_DATA register after a transaction and wait for our + * request to complete. If it doesn't complete, return error. + */ + t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0); + max_poll = EEPROM_MAX_POLL; + do { + udelay(EEPROM_DELAY); + t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg); + } while ((stats_reg & 0x1) && --max_poll); + if (!max_poll) + return -ETIMEDOUT; + + /* Return success! */ + return 0; +} + +/** + * t4_seeprom_wp - enable/disable EEPROM write protection + * @adapter: the adapter + * @enable: whether to enable or disable write protection + * + * Enables or disables write protection on the serial EEPROM. + */ +int t4_seeprom_wp(struct adapter *adapter, int enable) +{ + return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0); +} + /** * t4_config_rss_range - configure a portion of the RSS mapping table * @adapter: the adapter @@ -2384,6 +2563,9 @@ int t4_prep_adapter(struct adapter *adapter) return -EINVAL; } + adapter->params.pci.vpd_cap_addr = + t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD); + ret = t4_get_flash_params(adapter); if (ret < 0) return ret; diff --git a/drivers/net/cxgbe/base/t4_hw.h b/drivers/net/cxgbe/base/t4_hw.h index bf623cf..5e62c41 100644 --- a/drivers/net/cxgbe/base/t4_hw.h +++ b/drivers/net/cxgbe/base/t4_hw.h @@ -1,7 +1,7 @@ /*- * BSD LICENSE * - * Copyright(c) 2014-2015 Chelsio Communications. + * Copyright(c) 2014-2016 Chelsio Communications. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -36,6 +36,9 @@ enum { NCHAN = 4, /* # of HW channels */ + EEPROMSIZE = 17408, /* Serial EEPROM physical size */ + EEPROMVSIZE = 32768, /* Serial EEPROM virtual address space size */ + EEPROMPFSIZE = 1024, /* EEPROM writable area size for PFn, n>0 */ NMTUS = 16, /* size of MTU table */ NCCTRL_WIN = 32, /* # of congestion control windows */ MBOX_LEN = 64, /* mailbox size in bytes */ diff --git a/drivers/net/cxgbe/cxgbe_ethdev.c b/drivers/net/cxgbe/cxgbe_ethdev.c index 04eddaf..dbc3800 100644 --- a/drivers/net/cxgbe/cxgbe_ethdev.c +++ b/drivers/net/cxgbe/cxgbe_ethdev.c @@ -781,6 +781,145 @@ cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev) return NULL; } +static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev) +{ + RTE_SET_USED(dev); + return EEPROMSIZE; +} + +/** + * eeprom_ptov - translate a physical EEPROM address to virtual + * @phys_addr: the physical EEPROM address + * @fn: the PCI function number + * @sz: size of function-specific area + * + * Translate a physical EEPROM address to virtual. The first 1K is + * accessed through virtual addresses starting at 31K, the rest is + * accessed through virtual addresses starting at 0. + * + * The mapping is as follows: + * [0..1K) -> [31K..32K) + * [1K..1K+A) -> [31K-A..31K) + * [1K+A..ES) -> [0..ES-A-1K) + * + * where A = @fn * @sz, and ES = EEPROM size. + */ +static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz) +{ + fn *= sz; + if (phys_addr < 1024) + return phys_addr + (31 << 10); + if (phys_addr < 1024 + fn) + return fn + phys_addr - 1024; + if (phys_addr < EEPROMSIZE) + return phys_addr - 1024 - fn; + if (phys_addr < EEPROMVSIZE) + return phys_addr - 1024; + return -EINVAL; +} + +/* The next two routines implement eeprom read/write from physical addresses. + */ +static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v) +{ + int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE); + + if (vaddr >= 0) + vaddr = t4_seeprom_read(adap, vaddr, v); + return vaddr < 0 ? vaddr : 0; +} + +static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v) +{ + int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE); + + if (vaddr >= 0) + vaddr = t4_seeprom_write(adap, vaddr, v); + return vaddr < 0 ? vaddr : 0; +} + +#define EEPROM_MAGIC 0x38E2F10C + +static int cxgbe_get_eeprom(struct rte_eth_dev *dev, + struct rte_dev_eeprom_info *e) +{ + struct port_info *pi = (struct port_info *)(dev->data->dev_private); + struct adapter *adapter = pi->adapter; + u32 i, err = 0; + u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0); + + if (!buf) + return -ENOMEM; + + e->magic = EEPROM_MAGIC; + for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4) + err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]); + + if (!err) + rte_memcpy(e->data, buf + e->offset, e->length); + rte_free(buf); + return err; +} + +static int cxgbe_set_eeprom(struct rte_eth_dev *dev, + struct rte_dev_eeprom_info *eeprom) +{ + struct port_info *pi = (struct port_info *)(dev->data->dev_private); + struct adapter *adapter = pi->adapter; + u8 *buf; + int err = 0; + u32 aligned_offset, aligned_len, *p; + + if (eeprom->magic != EEPROM_MAGIC) + return -EINVAL; + + aligned_offset = eeprom->offset & ~3; + aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3; + + if (adapter->pf > 0) { + u32 start = 1024 + adapter->pf * EEPROMPFSIZE; + + if (aligned_offset < start || + aligned_offset + aligned_len > start + EEPROMPFSIZE) + return -EPERM; + } + + if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) { + /* RMW possibly needed for first or last words. + */ + buf = rte_zmalloc(NULL, aligned_len, 0); + if (!buf) + return -ENOMEM; + err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf); + if (!err && aligned_len > 4) + err = eeprom_rd_phys(adapter, + aligned_offset + aligned_len - 4, + (u32 *)&buf[aligned_len - 4]); + if (err) + goto out; + rte_memcpy(buf + (eeprom->offset & 3), eeprom->data, + eeprom->length); + } else { + buf = eeprom->data; + } + + err = t4_seeprom_wp(adapter, false); + if (err) + goto out; + + for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) { + err = eeprom_wr_phys(adapter, aligned_offset, *p); + aligned_offset += 4; + } + + if (!err) + err = t4_seeprom_wp(adapter, true); +out: + if (buf != eeprom->data) + rte_free(buf); + return err; +} + static const struct eth_dev_ops cxgbe_eth_dev_ops = { .dev_start = cxgbe_dev_start, .dev_stop = cxgbe_dev_stop, @@ -806,6 +945,9 @@ static const struct eth_dev_ops cxgbe_eth_dev_ops = { .stats_reset = cxgbe_dev_stats_reset, .flow_ctrl_get = cxgbe_flow_ctrl_get, .flow_ctrl_set = cxgbe_flow_ctrl_set, + .get_eeprom_length = cxgbe_get_eeprom_length, + .get_eeprom = cxgbe_get_eeprom, + .set_eeprom = cxgbe_set_eeprom, }; /* -- 2.5.3 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 5/5] cxgbe: add support to get register dump 2016-05-06 7:43 [PATCH 0/5] cxgbe: add features to CXGBE PMD Rahul Lakkireddy ` (3 preceding siblings ...) 2016-05-06 7:43 ` [PATCH 4/5] cxgbe: add support to get/set EEPROM Rahul Lakkireddy @ 2016-05-06 7:43 ` Rahul Lakkireddy 2016-06-02 14:43 ` [PATCH 0/5] cxgbe: add features to CXGBE PMD Bruce Richardson 5 siblings, 0 replies; 9+ messages in thread From: Rahul Lakkireddy @ 2016-05-06 7:43 UTC (permalink / raw) To: dev; +Cc: Kumar Sanghvi, Nirranjan Kirubaharan Add operations to get register dump. Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com> --- doc/guides/nics/overview.rst | 2 +- drivers/net/cxgbe/base/common.h | 6 + drivers/net/cxgbe/base/t4_hw.c | 846 +++++++++++++++++++++++++++++++++++++++ drivers/net/cxgbe/cxgbe_ethdev.c | 25 ++ 4 files changed, 878 insertions(+), 1 deletion(-) diff --git a/doc/guides/nics/overview.rst b/doc/guides/nics/overview.rst index afaac28..6075c09 100644 --- a/doc/guides/nics/overview.rst +++ b/doc/guides/nics/overview.rst @@ -131,7 +131,7 @@ Most of these differences are summarized below. Extended stats Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Stats per queue Y Y Y Y Y Y Y Y Y Y Y Y EEPROM dump Y Y Y Y - Registers dump Y Y Y Y Y Y + Registers dump Y Y Y Y Y Y Y Multiprocess aware Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y BSD nic_uio Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Linux UIO Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y diff --git a/drivers/net/cxgbe/base/common.h b/drivers/net/cxgbe/base/common.h index 853edd8..11f139c 100644 --- a/drivers/net/cxgbe/base/common.h +++ b/drivers/net/cxgbe/base/common.h @@ -50,6 +50,10 @@ enum { }; enum { + T5_REGMAP_SIZE = (332 * 1024), +}; + +enum { MEMWIN0_APERTURE = 2048, MEMWIN0_BASE = 0x1b800, }; @@ -398,6 +402,8 @@ int t4_init_sge_params(struct adapter *adapter); int t4_init_tp_params(struct adapter *adap); int t4_filter_field_shift(const struct adapter *adap, unsigned int filter_sel); int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); +unsigned int t4_get_regs_len(struct adapter *adap); +void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size); int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data); int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data); int t4_seeprom_wp(struct adapter *adapter, int enable); diff --git a/drivers/net/cxgbe/base/t4_hw.c b/drivers/net/cxgbe/base/t4_hw.c index ff8594a..7e79adf 100644 --- a/drivers/net/cxgbe/base/t4_hw.c +++ b/drivers/net/cxgbe/base/t4_hw.c @@ -569,6 +569,852 @@ int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, FW_CMD_MAX_TIMEOUT); } +/** + * t4_get_regs_len - return the size of the chips register set + * @adapter: the adapter + * + * Returns the size of the chip's BAR0 register space. + */ +unsigned int t4_get_regs_len(struct adapter *adapter) +{ + unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip); + + switch (chip_version) { + case CHELSIO_T5: + return T5_REGMAP_SIZE; + } + + dev_err(adapter, + "Unsupported chip version %d\n", chip_version); + return 0; +} + +/** + * t4_get_regs - read chip registers into provided buffer + * @adap: the adapter + * @buf: register buffer + * @buf_size: size (in bytes) of register buffer + * + * If the provided register buffer isn't large enough for the chip's + * full register range, the register dump will be truncated to the + * register buffer's size. + */ +void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size) +{ + static const unsigned int t5_reg_ranges[] = { + 0x1008, 0x10c0, + 0x10cc, 0x10f8, + 0x1100, 0x1100, + 0x110c, 0x1148, + 0x1180, 0x1184, + 0x1190, 0x1194, + 0x11a0, 0x11a4, + 0x11b0, 0x11b4, + 0x11fc, 0x123c, + 0x1280, 0x173c, + 0x1800, 0x18fc, + 0x3000, 0x3028, + 0x3060, 0x30b0, + 0x30b8, 0x30d8, + 0x30e0, 0x30fc, + 0x3140, 0x357c, + 0x35a8, 0x35cc, + 0x35ec, 0x35ec, + 0x3600, 0x5624, + 0x56cc, 0x56ec, + 0x56f4, 0x5720, + 0x5728, 0x575c, + 0x580c, 0x5814, + 0x5890, 0x589c, + 0x58a4, 0x58ac, + 0x58b8, 0x58bc, + 0x5940, 0x59c8, + 0x59d0, 0x59dc, + 0x59fc, 0x5a18, + 0x5a60, 0x5a70, + 0x5a80, 0x5a9c, + 0x5b94, 0x5bfc, + 0x6000, 0x6020, + 0x6028, 0x6040, + 0x6058, 0x609c, + 0x60a8, 0x614c, + 0x7700, 0x7798, + 0x77c0, 0x78fc, + 0x7b00, 0x7b58, + 0x7b60, 0x7b84, + 0x7b8c, 0x7c54, + 0x7d00, 0x7d38, + 0x7d40, 0x7d80, + 0x7d8c, 0x7ddc, + 0x7de4, 0x7e04, + 0x7e10, 0x7e1c, + 0x7e24, 0x7e38, + 0x7e40, 0x7e44, + 0x7e4c, 0x7e78, + 0x7e80, 0x7edc, + 0x7ee8, 0x7efc, + 0x8dc0, 0x8de0, + 0x8df8, 0x8e04, + 0x8e10, 0x8e84, + 0x8ea0, 0x8f84, + 0x8fc0, 0x9058, + 0x9060, 0x9060, + 0x9068, 0x90f8, + 0x9400, 0x9408, + 0x9410, 0x9470, + 0x9600, 0x9600, + 0x9608, 0x9638, + 0x9640, 0x96f4, + 0x9800, 0x9808, + 0x9820, 0x983c, + 0x9850, 0x9864, + 0x9c00, 0x9c6c, + 0x9c80, 0x9cec, + 0x9d00, 0x9d6c, + 0x9d80, 0x9dec, + 0x9e00, 0x9e6c, + 0x9e80, 0x9eec, + 0x9f00, 0x9f6c, + 0x9f80, 0xa020, + 0xd004, 0xd004, + 0xd010, 0xd03c, + 0xdfc0, 0xdfe0, + 0xe000, 0x1106c, + 0x11074, 0x11088, + 0x1109c, 0x1117c, + 0x11190, 0x11204, + 0x19040, 0x1906c, + 0x19078, 0x19080, + 0x1908c, 0x190e8, + 0x190f0, 0x190f8, + 0x19100, 0x19110, + 0x19120, 0x19124, + 0x19150, 0x19194, + 0x1919c, 0x191b0, + 0x191d0, 0x191e8, + 0x19238, 0x19290, + 0x193f8, 0x19428, + 0x19430, 0x19444, + 0x1944c, 0x1946c, + 0x19474, 0x19474, + 0x19490, 0x194cc, + 0x194f0, 0x194f8, + 0x19c00, 0x19c08, + 0x19c10, 0x19c60, + 0x19c94, 0x19ce4, + 0x19cf0, 0x19d40, + 0x19d50, 0x19d94, + 0x19da0, 0x19de8, + 0x19df0, 0x19e10, + 0x19e50, 0x19e90, + 0x19ea0, 0x19f24, + 0x19f34, 0x19f34, + 0x19f40, 0x19f50, + 0x19f90, 0x19fb4, + 0x19fc4, 0x19fe4, + 0x1a000, 0x1a004, + 0x1a010, 0x1a06c, + 0x1a0b0, 0x1a0e4, + 0x1a0ec, 0x1a0f8, + 0x1a100, 0x1a108, + 0x1a114, 0x1a120, + 0x1a128, 0x1a130, + 0x1a138, 0x1a138, + 0x1a190, 0x1a1c4, + 0x1a1fc, 0x1a1fc, + 0x1e008, 0x1e00c, + 0x1e040, 0x1e044, + 0x1e04c, 0x1e04c, + 0x1e284, 0x1e290, + 0x1e2c0, 0x1e2c0, + 0x1e2e0, 0x1e2e0, + 0x1e300, 0x1e384, + 0x1e3c0, 0x1e3c8, + 0x1e408, 0x1e40c, + 0x1e440, 0x1e444, + 0x1e44c, 0x1e44c, + 0x1e684, 0x1e690, + 0x1e6c0, 0x1e6c0, + 0x1e6e0, 0x1e6e0, + 0x1e700, 0x1e784, + 0x1e7c0, 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0x4c774, + 0x4c780, 0x4c7ac, + 0x4c7b4, 0x4c7b8, + 0x4c7c0, 0x4c854, + 0x4c85c, 0x4c878, + 0x4c8c0, 0x4c974, + 0x4c980, 0x4c9ac, + 0x4c9b4, 0x4c9b8, + 0x4c9c0, 0x4c9fc, + 0x4d000, 0x4d004, + 0x4d010, 0x4d030, + 0x4d040, 0x4d060, + 0x4d068, 0x4d068, + 0x4d080, 0x4d084, + 0x4d0a0, 0x4d0b0, + 0x4d200, 0x4d204, + 0x4d210, 0x4d230, + 0x4d240, 0x4d260, + 0x4d268, 0x4d268, + 0x4d280, 0x4d284, + 0x4d2a0, 0x4d2b0, + 0x4e0c0, 0x4e0e4, + 0x4f000, 0x4f03c, + 0x4f044, 0x4f08c, + 0x4f200, 0x4f250, + 0x4f400, 0x4f408, + 0x4f414, 0x4f420, + 0x4f600, 0x4f618, + 0x4f800, 0x4f814, + 0x50000, 0x50084, + 0x50090, 0x500cc, + 0x50400, 0x50400, + 0x50800, 0x50884, + 0x50890, 0x508cc, + 0x50c00, 0x50c00, + 0x51000, 0x5101c, + 0x51300, 0x51308, + }; + + u32 *buf_end = (u32 *)((char *)buf + buf_size); + const unsigned int *reg_ranges; + int reg_ranges_size, range; + unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip); + + /* Select the right set of register ranges to dump depending on the + * adapter chip type. + */ + switch (chip_version) { + case CHELSIO_T5: + reg_ranges = t5_reg_ranges; + reg_ranges_size = ARRAY_SIZE(t5_reg_ranges); + break; + + default: + dev_err(adap, + "Unsupported chip version %d\n", chip_version); + return; + } + + /* Clear the register buffer and insert the appropriate register + * values selected by the above register ranges. + */ + memset(buf, 0, buf_size); + for (range = 0; range < reg_ranges_size; range += 2) { + unsigned int reg = reg_ranges[range]; + unsigned int last_reg = reg_ranges[range + 1]; + u32 *bufp = (u32 *)((char *)buf + reg); + + /* Iterate across the register range filling in the register + * buffer but don't write past the end of the register buffer. + */ + while (reg <= last_reg && bufp < buf_end) { + *bufp++ = t4_read_reg(adap, reg); + reg += sizeof(u32); + } + } +} + /* EEPROM reads take a few tens of us while writes can take a bit over 5 ms. */ #define EEPROM_DELAY 10 /* 10us per poll spin */ #define EEPROM_MAX_POLL 5000 /* x 5000 == 50ms */ diff --git a/drivers/net/cxgbe/cxgbe_ethdev.c b/drivers/net/cxgbe/cxgbe_ethdev.c index dbc3800..6c130ed 100644 --- a/drivers/net/cxgbe/cxgbe_ethdev.c +++ b/drivers/net/cxgbe/cxgbe_ethdev.c @@ -920,6 +920,29 @@ out: return err; } +static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev) +{ + struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); + struct adapter *adapter = pi->adapter; + + return t4_get_regs_len(adapter) / sizeof(uint32_t); +} + +static int cxgbe_get_regs(struct rte_eth_dev *eth_dev, + struct rte_dev_reg_info *regs) +{ + struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); + struct adapter *adapter = pi->adapter; + + regs->length = cxgbe_get_regs_len(eth_dev); + regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) | + (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) | + (1 << 16); + t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t))); + + return 0; +} + static const struct eth_dev_ops cxgbe_eth_dev_ops = { .dev_start = cxgbe_dev_start, .dev_stop = cxgbe_dev_stop, @@ -948,6 +971,8 @@ static const struct eth_dev_ops cxgbe_eth_dev_ops = { .get_eeprom_length = cxgbe_get_eeprom_length, .get_eeprom = cxgbe_get_eeprom, .set_eeprom = cxgbe_set_eeprom, + .get_reg_length = cxgbe_get_regs_len, + .get_reg = cxgbe_get_regs, }; /* -- 2.5.3 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 0/5] cxgbe: add features to CXGBE PMD 2016-05-06 7:43 [PATCH 0/5] cxgbe: add features to CXGBE PMD Rahul Lakkireddy ` (4 preceding siblings ...) 2016-05-06 7:43 ` [PATCH 5/5] cxgbe: add support to get register dump Rahul Lakkireddy @ 2016-06-02 14:43 ` Bruce Richardson 5 siblings, 0 replies; 9+ messages in thread From: Bruce Richardson @ 2016-06-02 14:43 UTC (permalink / raw) To: Rahul Lakkireddy; +Cc: dev, Kumar Sanghvi, Nirranjan Kirubaharan On Fri, May 06, 2016 at 01:13:14PM +0530, Rahul Lakkireddy wrote: > This patch series add some features to CXGBE PMD. > > Patch 1 fixes a bug where reading/writing PCI config space in BSD fails > with EPERM due to missing write permission when opening /dev/pci/. > > Patch 2 adds support to access PCI config space for CXGBE PMD. > > Patch 3 programs PCIe completion timeout to 4 sec. > > Patch 4 adds support to get/set EEPROM. > > Patch 5 adds support to get register dump. > > Rahul Lakkireddy (5): > pci: fix access to PCI config space in bsd > cxgbe: add support to access PCI config space > cxgbe: set default PCIe completion timeout > cxgbe: add support to get/set EEPROM > cxgbe: add support to get register dump > Applied to dpdk-next-net/rel_16_07 /Bruce ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2016-06-02 14:53 UTC | newest] Thread overview: 9+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2016-05-06 7:43 [PATCH 0/5] cxgbe: add features to CXGBE PMD Rahul Lakkireddy 2016-05-06 7:43 ` [PATCH 1/5] pci: fix access to PCI config space in bsd Rahul Lakkireddy 2016-05-31 16:20 ` Bruce Richardson 2016-06-01 8:34 ` Rahul Lakkireddy 2016-05-06 7:43 ` [PATCH 2/5] cxgbe: add support to access PCI config space Rahul Lakkireddy 2016-05-06 7:43 ` [PATCH 3/5] cxgbe: set default PCIe completion timeout Rahul Lakkireddy 2016-05-06 7:43 ` [PATCH 4/5] cxgbe: add support to get/set EEPROM Rahul Lakkireddy 2016-05-06 7:43 ` [PATCH 5/5] cxgbe: add support to get register dump Rahul Lakkireddy 2016-06-02 14:43 ` [PATCH 0/5] cxgbe: add features to CXGBE PMD Bruce Richardson
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