* [PATCH 0/2] ARM: dts: Add support for the MDM9615 @ 2016-06-17 10:35 ` Neil Armstrong 0 siblings, 0 replies; 13+ messages in thread From: Neil Armstrong @ 2016-06-17 10:35 UTC (permalink / raw) To: andy.gross, david.brown, linux, sboyd Cc: Neil Armstrong, devicetree, linux-kernel, linux-arm-msm, linux-soc, linux-arm-kernel In order to support the Qualcomm MDM9615 in the Sierra Wireless WP8548 Modules, add the MDM9615 DTSI and update its dt-bindings. This patchset depends on pinctrl [1], clk [2], pmic [3] and arm-soc [4] patchsets. This patchset is part of a global SoC + Module + Board support for the Sierra Wireless mangOH Board support with the WP8548 module. [1] http://lkml.kernel.org/r/1466158535-17962-1-git-send-email-narmstrong@baylibre.com [2] http://lkml.kernel.org/r/1466157875-14428-1-git-send-email-narmstrong@baylibre.com [3] http://lkml.kernel.org/r/1466158929-19524-1-git-send-email-narmstrong@baylibre.com [4] http://lkml.kernel.org/r/1466159484-21858-1-git-send-email-narmstrong@baylibre.com Neil Armstrong (2): ARM: dts: Add MSM9615 dtsi dt-bindings: qcom: Add MDM9615 bindings Documentation/devicetree/bindings/arm/qcom.txt | 1 + arch/arm/boot/dts/qcom-mdm9615.dtsi | 650 +++++++++++++++++++++++++ 2 files changed, 651 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-mdm9615.dtsi -- 1.9.1 ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 0/2] ARM: dts: Add support for the MDM9615 @ 2016-06-17 10:35 ` Neil Armstrong 0 siblings, 0 replies; 13+ messages in thread From: Neil Armstrong @ 2016-06-17 10:35 UTC (permalink / raw) To: linux-arm-kernel In order to support the Qualcomm MDM9615 in the Sierra Wireless WP8548 Modules, add the MDM9615 DTSI and update its dt-bindings. This patchset depends on pinctrl [1], clk [2], pmic [3] and arm-soc [4] patchsets. This patchset is part of a global SoC + Module + Board support for the Sierra Wireless mangOH Board support with the WP8548 module. [1] http://lkml.kernel.org/r/1466158535-17962-1-git-send-email-narmstrong at baylibre.com [2] http://lkml.kernel.org/r/1466157875-14428-1-git-send-email-narmstrong at baylibre.com [3] http://lkml.kernel.org/r/1466158929-19524-1-git-send-email-narmstrong at baylibre.com [4] http://lkml.kernel.org/r/1466159484-21858-1-git-send-email-narmstrong at baylibre.com Neil Armstrong (2): ARM: dts: Add MSM9615 dtsi dt-bindings: qcom: Add MDM9615 bindings Documentation/devicetree/bindings/arm/qcom.txt | 1 + arch/arm/boot/dts/qcom-mdm9615.dtsi | 650 +++++++++++++++++++++++++ 2 files changed, 651 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-mdm9615.dtsi -- 1.9.1 ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 1/2] ARM: dts: Add MSM9615 dtsi 2016-06-17 10:35 ` Neil Armstrong @ 2016-06-17 10:35 ` Neil Armstrong -1 siblings, 0 replies; 13+ messages in thread From: Neil Armstrong @ 2016-06-17 10:35 UTC (permalink / raw) To: andy.gross, david.brown, linux, sboyd Cc: Neil Armstrong, devicetree, linux-kernel, linux-arm-msm, linux-soc, linux-arm-kernel In order to support the Qualcomm MSM9615 SoC, add the SoC dtsi. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- arch/arm/boot/dts/qcom-mdm9615.dtsi | 650 ++++++++++++++++++++++++++++++++++++ 1 file changed, 650 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-mdm9615.dtsi diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi new file mode 100644 index 0000000..6dc7dcf --- /dev/null +++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi @@ -0,0 +1,650 @@ +/* + * Device Tree Source for Qualcomm MDM9615 SoC + * + * Copyright (C) 2016 BayLibre, SAS. + * Author : Neil Armstrong <narmstrong@baylibre.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +/include/ "skeleton.dtsi" + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/qcom,gcc-mdm9615.h> +#include <dt-bindings/reset/qcom,gcc-mdm9615.h> +#include <dt-bindings/mfd/qcom-rpm.h> +#include <dt-bindings/soc/qcom,gsbi.h> + +/ { + model = "Qualcomm MDM9615"; + compatible = "qcom,mdm9615"; + interrupt-parent = <&intc>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 14 0x304>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a5"; + device_type = "cpu"; + next-level-cache = <&L2>; + }; + }; + + cpu-pmu { + compatible = "arm,cortex-a5-pmu"; + interrupts = <GIC_SPI 10 0x304>; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + L2: l2-cache { + compatible = "arm,pl310-cache"; + reg = <0x02040000 0x1000>; + arm,data-latency = <2 2 0>; + cache-unified; + cache-level = <2>; + }; + + intc: interrupt-controller@2000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x02000000 0x1000>, + <0x02002000 0x1000>; + }; + + timer@200a000 { + compatible = "qcom,kpss-timer", "qcom,msm-timer"; + interrupts = <GIC_PPI 1 0x301>, + <GIC_PPI 2 0x301>, + <GIC_PPI 3 0x301>; + reg = <0x0200a000 0x100>; + clock-frequency = <27000000>, + <32768>; + cpu-offset = <0x80000>; + }; + + msmgpio: pinctrl@800000 { + compatible = "qcom,mdm9615-pinctrl", "syscon"; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x800000 0x4000>; + }; + + gcc: clock-controller@900000 { + compatible = "qcom,gcc-mdm9615"; + #clock-cells = <1>; + #reset-cells = <1>; + reg = <0x900000 0x4000>; + }; + + lcc: clock-controller@28000000 { + compatible = "qcom,lcc-mdm9615"; + reg = <0x28000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + l2cc: clock-controller@2011000 { + compatible = "syscon"; + reg = <0x02011000 0x1000>; + }; + + rng@1a500000 { + compatible = "qcom,prng"; + reg = <0x1a500000 0x200>; + clocks = <&gcc PRNG_CLK>; + clock-names = "core"; + assigned-clocks = <&gcc PRNG_CLK>; + assigned-clock-rates = <32000000>; + }; + + vsdcc_fixed: vsdcc-regulator { + compatible = "regulator-fixed"; + regulator-name = "SDCC Power"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + regulator-always-on; + }; + + gsbi2: gsbi@16100000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <2>; + reg = <0x16100000 0x100>; + clocks = <&gcc GSBI2_H_CLK>; + clock-names = "iface"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gsbi2_i2c: i2c@16180000 { + compatible = "qcom,i2c-qup-v1.1.1"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x16180000 0x1000>; + interrupts = <GIC_SPI 149 IRQ_TYPE_NONE>; + + clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + }; + + gsbi3: gsbi@16200000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <3>; + reg = <0x16200000 0x100>; + clocks = <&gcc GSBI3_H_CLK>; + clock-names = "iface"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gsbi3_spi: spi@16280000 { + compatible = "qcom,spi-qup-v1.1.1"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x16280000 0x1000>; + interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>; + spi-max-frequency = <24000000>; + + clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + }; + + gsbi4: gsbi@16300000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <4>; + reg = <0x16300000 0x100>; + clocks = <&gcc GSBI4_H_CLK>; + clock-names = "iface"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon-tcsr = <&tcsr>; + + gsbi4_serial: serial@16340000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16340000 0x1000>, + <0x16300000 0x1000>; + interrupts = <GIC_SPI 152 IRQ_TYPE_NONE>; + clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + }; + + gsbi5: gsbi@16400000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <5>; + reg = <0x16400000 0x100>; + clocks = <&gcc GSBI5_H_CLK>; + clock-names = "iface"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon-tcsr = <&tcsr>; + + gsbi5_i2c: i2c@16480000 { + compatible = "qcom,i2c-qup-v1.1.1"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x16480000 0x1000>; + interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>; + + /* QUP clock is not initialized, set rate */ + assigned-clocks = <&gcc GSBI5_QUP_CLK>; + assigned-clock-rates = <24000000>; + + clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + gsbi5_serial: serial@16440000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16440000 0x1000>, + <0x16400000 0x1000>; + interrupts = <GIC_SPI 154 IRQ_TYPE_NONE>; + clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + }; + + qcom,ssbi@500000 { + compatible = "qcom,ssbi"; + reg = <0x500000 0x1000>; + qcom,controller-type = "pmic-arbiter"; + + pmicintc: pmic@0 { + compatible = "qcom,pm8018"; + interrupts = <GIC_PPI 226 IRQ_TYPE_NONE>; + #interrupt-cells = <2>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + + pwrkey@1c { + compatible = "qcom,pm8018-pwrkey"; + reg = <0x1c>; + interrupt-parent = <&pmicintc>; + interrupts = <50 IRQ_TYPE_EDGE_RISING>, + <51 IRQ_TYPE_EDGE_RISING>; + debounce = <15625>; + pull-up; + }; + + pmicmpp: mpp@50 { + compatible = "qcom,pm8018-mpp"; + interrupt-parent = <&pmicintc>; + interrupts = <24 IRQ_TYPE_EDGE_RISING>, + <25 IRQ_TYPE_EDGE_RISING>, + <26 IRQ_TYPE_EDGE_RISING>, + <27 IRQ_TYPE_EDGE_RISING>, + <28 IRQ_TYPE_EDGE_RISING>, + <29 IRQ_TYPE_EDGE_RISING>; + reg = <0x50>; + gpio-controller; + #gpio-cells = <2>; + }; + + rtc@11d { + compatible = "qcom,pm8018-rtc"; + interrupt-parent = <&pmicintc>; + interrupts = <39 IRQ_TYPE_EDGE_RISING>; + reg = <0x11d>; + allow-set-time; + }; + + pmicgpio: gpio@150 { + compatible = "qcom,pm8018-gpio"; + interrupt-parent = <&pmicintc>; + interrupts = <24 IRQ_TYPE_EDGE_RISING>, + <25 IRQ_TYPE_EDGE_RISING>, + <26 IRQ_TYPE_EDGE_RISING>, + <27 IRQ_TYPE_EDGE_RISING>, + <28 IRQ_TYPE_EDGE_RISING>, + <29 IRQ_TYPE_EDGE_RISING>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + }; + + sdcc1bam:dma@12182000{ + compatible = "qcom,bam-v1.3.0"; + reg = <0x12182000 0x8000>; + interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>; + clocks = <&gcc SDC1_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + sdcc2bam:dma@12142000{ + compatible = "qcom,bam-v1.3.0"; + reg = <0x12142000 0x8000>; + interrupts = <GIC_SPI 97 IRQ_TYPE_NONE>; + clocks = <&gcc SDC2_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + sdcc1: sdcc@12180000 { + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + reg = <0x12180000 0x2000>; + interrupts = <GIC_SPI 104 IRQ_TYPE_NONE>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <48000000>; + cap-sd-highspeed; + cap-mmc-highspeed; + vmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; + dma-names = "tx", "rx"; + assigned-clocks = <&gcc SDC1_CLK>; + assigned-clock-rates = <400000>; + }; + + sdcc2: sdcc@12140000 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + status = "disabled"; + reg = <0x12140000 0x2000>; + interrupts = <GIC_SPI 103 IRQ_TYPE_NONE>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <48000000>; + no-1-8-v; + vmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc2bam 2>, <&sdcc2bam 1>; + dma-names = "tx", "rx"; + assigned-clocks = <&gcc SDC2_CLK>; + assigned-clock-rates = <400000>; + }; + }; + + tcsr: syscon@1a400000 { + compatible = "qcom,tcsr-mdm9615", "syscon"; + reg = <0x1a400000 0x100>; + }; + + rpm: rpm@108000 { + compatible = "qcom,rpm-mdm9615"; + reg = <0x108000 0x1000>; + + qcom,ipc = <&l2cc 0x8 2>; + + interrupts = <0 19 0>, <0 21 0>, <0 22 0>; + interrupt-names = "ack", "err", "wakeup"; + + regulators { + compatible = "qcom,rpm-pm8018-regulators"; + + vin_lvs1-supply = <&pm8018_s3>; + + vdd_l7-supply = <&pm8018_s4>; + vdd_l8-supply = <&pm8018_s3>; + vdd_l9_l10_l11_l12-supply = <&pm8018_s5>; + + /* Buck SMPS */ + pm8018_s1: s1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1150000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + pm8018_s2: s2 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1300000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + pm8018_s3: s3 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + pm8018_s4: s4 { + regulator-min-microvolt = <2100000>; + regulator-max-microvolt = <2200000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + pm8018_s5: s5 { + regulator-always-on; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + /* PMOS LDO */ + pm8018_l2: l2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + pm8018_l3: l3 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + pm8018_l4: l4 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + bias-pull-down; + }; + + pm8018_l5: l5 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + bias-pull-down; + }; + + pm8018_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2850000>; + bias-pull-down; + }; + + pm8018_l7: l7 { + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <1900000>; + bias-pull-down; + }; + + pm8018_l8: l8 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + bias-pull-down; + }; + + pm8018_l9: l9 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1150000>; + bias-pull-down; + }; + + pm8018_l10: l10 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + bias-pull-down; + }; + + pm8018_l11: l11 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + bias-pull-down; + }; + + pm8018_l12: l12 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + bias-pull-down; + }; + + pm8018_l13: l13 { + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + pm8018_l14: l14 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + bias-pull-down; + }; + + /* Low Voltage Switch */ + pm8018_lvs1: lvs1 { + bias-pull-down; + }; + + pm8018_vdd_dig_corner: dig_corner { + regulator-min-microvolt = <1>; + regulator-max-microvolt = <4>; + }; + }; + }; + + /* OTG */ + usb1_phy: phy@12500000 { + compatible = "qcom,usb-otg-snps"; + reg = <0x12500000 0x400>; + interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>; + dr_mode = "otg"; + status = "disabled"; + + clocks = <&gcc USB_HS1_H_CLK>, + <&gcc USB_HS1_SYSTEM_CLK>; + clock-names = "iface", "core"; + + resets = <&gcc USB_HS1_RESET>; + reset-names = "link"; + vddcx-supply = <&pm8018_vdd_dig_corner>; + qcom,vdd-levels = <1 2 4>; + v3p3-supply = <&pm8018_l4>; + v1p8-supply = <&pm8018_l2>; + }; + + /* OTG */ + usb1bam: dma@12502000{ + compatible = "qcom,bam-v1.3.0"; + reg = <0x12502000 0x8000>; + interrupts = <GIC_SPI 94 IRQ_TYPE_NONE>; + clocks = <&gcc DMA_BAM_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + status = "disabled"; + }; + + usb1: usb@12500000 { + compatible = "qcom,ehci-host"; + reg = <0x12500000 0x400>; + interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>; + status = "disabled"; + usb-phy = <&usb1_phy>; + }; + + gadget1: gadget@12500000 { + compatible = "qcom,ci-hdrc"; + reg = <0x12500000 0x400>; + interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>; + status = "disabled"; + dr_mode = "peripheral"; + usb-phy = <&usb1_phy>; + }; + + usb2_phy: phy@12540000 { + compatible = "qcom,usb-hsic-phy"; + reg = <0x12540000 0x400>; + interrupts = <GIC_SPI 232 IRQ_TYPE_NONE>; + status = "disabled"; + dr_mode = "host"; + + clocks = <&gcc USB_HSIC_SYSTEM_CLK>, + <&gcc USB_HSIC_XCVR_FS_CLK>, + <&gcc USB_HSIC_HSIC_CLK>, + <&gcc USB_HSIC_HSIO_CAL_CLK>, + <&gcc USB_HSIC_H_CLK>; + clock-names = "core", "alt-core", "phy", "cal", "iface"; + assigned-clocks = <&gcc USB_HSIC_XCVR_FS_CLK>, + <&gcc USB_HSIC_SYSTEM_CLK>, + <&gcc USB_HSIC_HSIC_CLK>; + assigned-clock-rates = <60000000>, + <64000000>, + <480000000>; + resets = <&gcc USB_HSIC_RESET>; + reset-names = "link"; + vddcx-supply = <&pm8018_vdd_dig_corner>; + qcom,vdd-levels = <1 2 4>; + phy_type = "hsic"; + + qcom,tlmm = <&msmgpio>; + qcom,tlmm-cfg = <0x20CC 0x034A4E10 + 0x20C8 0x034A4E10>; + }; + + usb2bam: dma@12542000{ + compatible = "qcom,bam-v1.3.0"; + reg = <0x12542000 0x8000>; + interrupts = <GIC_SPI 231 IRQ_TYPE_NONE>; + clocks = <&gcc DMA_BAM_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + status = "disabled"; + }; + + usb2: usb@12540000 { + compatible = "qcom,ehci-host"; + reg = <0x12540000 0x400>; + interrupts = <GIC_SPI 232 IRQ_TYPE_NONE>; + status = "disabled"; + usb-phy = <&usb2_phy>; + dr_mode = "host"; + }; + }; +}; -- 1.9.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 1/2] ARM: dts: Add MSM9615 dtsi @ 2016-06-17 10:35 ` Neil Armstrong 0 siblings, 0 replies; 13+ messages in thread From: Neil Armstrong @ 2016-06-17 10:35 UTC (permalink / raw) To: linux-arm-kernel In order to support the Qualcomm MSM9615 SoC, add the SoC dtsi. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- arch/arm/boot/dts/qcom-mdm9615.dtsi | 650 ++++++++++++++++++++++++++++++++++++ 1 file changed, 650 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-mdm9615.dtsi diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi new file mode 100644 index 0000000..6dc7dcf --- /dev/null +++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi @@ -0,0 +1,650 @@ +/* + * Device Tree Source for Qualcomm MDM9615 SoC + * + * Copyright (C) 2016 BayLibre, SAS. + * Author : Neil Armstrong <narmstrong@baylibre.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +/include/ "skeleton.dtsi" + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/qcom,gcc-mdm9615.h> +#include <dt-bindings/reset/qcom,gcc-mdm9615.h> +#include <dt-bindings/mfd/qcom-rpm.h> +#include <dt-bindings/soc/qcom,gsbi.h> + +/ { + model = "Qualcomm MDM9615"; + compatible = "qcom,mdm9615"; + interrupt-parent = <&intc>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 14 0x304>; + + cpu0: cpu at 0 { + compatible = "arm,cortex-a5"; + device_type = "cpu"; + next-level-cache = <&L2>; + }; + }; + + cpu-pmu { + compatible = "arm,cortex-a5-pmu"; + interrupts = <GIC_SPI 10 0x304>; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + L2: l2-cache { + compatible = "arm,pl310-cache"; + reg = <0x02040000 0x1000>; + arm,data-latency = <2 2 0>; + cache-unified; + cache-level = <2>; + }; + + intc: interrupt-controller at 2000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x02000000 0x1000>, + <0x02002000 0x1000>; + }; + + timer at 200a000 { + compatible = "qcom,kpss-timer", "qcom,msm-timer"; + interrupts = <GIC_PPI 1 0x301>, + <GIC_PPI 2 0x301>, + <GIC_PPI 3 0x301>; + reg = <0x0200a000 0x100>; + clock-frequency = <27000000>, + <32768>; + cpu-offset = <0x80000>; + }; + + msmgpio: pinctrl at 800000 { + compatible = "qcom,mdm9615-pinctrl", "syscon"; + gpio-controller; + #gpio-cells = <2>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x800000 0x4000>; + }; + + gcc: clock-controller at 900000 { + compatible = "qcom,gcc-mdm9615"; + #clock-cells = <1>; + #reset-cells = <1>; + reg = <0x900000 0x4000>; + }; + + lcc: clock-controller at 28000000 { + compatible = "qcom,lcc-mdm9615"; + reg = <0x28000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + l2cc: clock-controller at 2011000 { + compatible = "syscon"; + reg = <0x02011000 0x1000>; + }; + + rng at 1a500000 { + compatible = "qcom,prng"; + reg = <0x1a500000 0x200>; + clocks = <&gcc PRNG_CLK>; + clock-names = "core"; + assigned-clocks = <&gcc PRNG_CLK>; + assigned-clock-rates = <32000000>; + }; + + vsdcc_fixed: vsdcc-regulator { + compatible = "regulator-fixed"; + regulator-name = "SDCC Power"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + regulator-always-on; + }; + + gsbi2: gsbi at 16100000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <2>; + reg = <0x16100000 0x100>; + clocks = <&gcc GSBI2_H_CLK>; + clock-names = "iface"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gsbi2_i2c: i2c at 16180000 { + compatible = "qcom,i2c-qup-v1.1.1"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x16180000 0x1000>; + interrupts = <GIC_SPI 149 IRQ_TYPE_NONE>; + + clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + }; + + gsbi3: gsbi at 16200000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <3>; + reg = <0x16200000 0x100>; + clocks = <&gcc GSBI3_H_CLK>; + clock-names = "iface"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gsbi3_spi: spi at 16280000 { + compatible = "qcom,spi-qup-v1.1.1"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x16280000 0x1000>; + interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>; + spi-max-frequency = <24000000>; + + clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + }; + + gsbi4: gsbi at 16300000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <4>; + reg = <0x16300000 0x100>; + clocks = <&gcc GSBI4_H_CLK>; + clock-names = "iface"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon-tcsr = <&tcsr>; + + gsbi4_serial: serial at 16340000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16340000 0x1000>, + <0x16300000 0x1000>; + interrupts = <GIC_SPI 152 IRQ_TYPE_NONE>; + clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + }; + + gsbi5: gsbi at 16400000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <5>; + reg = <0x16400000 0x100>; + clocks = <&gcc GSBI5_H_CLK>; + clock-names = "iface"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon-tcsr = <&tcsr>; + + gsbi5_i2c: i2c at 16480000 { + compatible = "qcom,i2c-qup-v1.1.1"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x16480000 0x1000>; + interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>; + + /* QUP clock is not initialized, set rate */ + assigned-clocks = <&gcc GSBI5_QUP_CLK>; + assigned-clock-rates = <24000000>; + + clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + gsbi5_serial: serial at 16440000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16440000 0x1000>, + <0x16400000 0x1000>; + interrupts = <GIC_SPI 154 IRQ_TYPE_NONE>; + clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + }; + + qcom,ssbi at 500000 { + compatible = "qcom,ssbi"; + reg = <0x500000 0x1000>; + qcom,controller-type = "pmic-arbiter"; + + pmicintc: pmic at 0 { + compatible = "qcom,pm8018"; + interrupts = <GIC_PPI 226 IRQ_TYPE_NONE>; + #interrupt-cells = <2>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + + pwrkey at 1c { + compatible = "qcom,pm8018-pwrkey"; + reg = <0x1c>; + interrupt-parent = <&pmicintc>; + interrupts = <50 IRQ_TYPE_EDGE_RISING>, + <51 IRQ_TYPE_EDGE_RISING>; + debounce = <15625>; + pull-up; + }; + + pmicmpp: mpp at 50 { + compatible = "qcom,pm8018-mpp"; + interrupt-parent = <&pmicintc>; + interrupts = <24 IRQ_TYPE_EDGE_RISING>, + <25 IRQ_TYPE_EDGE_RISING>, + <26 IRQ_TYPE_EDGE_RISING>, + <27 IRQ_TYPE_EDGE_RISING>, + <28 IRQ_TYPE_EDGE_RISING>, + <29 IRQ_TYPE_EDGE_RISING>; + reg = <0x50>; + gpio-controller; + #gpio-cells = <2>; + }; + + rtc at 11d { + compatible = "qcom,pm8018-rtc"; + interrupt-parent = <&pmicintc>; + interrupts = <39 IRQ_TYPE_EDGE_RISING>; + reg = <0x11d>; + allow-set-time; + }; + + pmicgpio: gpio at 150 { + compatible = "qcom,pm8018-gpio"; + interrupt-parent = <&pmicintc>; + interrupts = <24 IRQ_TYPE_EDGE_RISING>, + <25 IRQ_TYPE_EDGE_RISING>, + <26 IRQ_TYPE_EDGE_RISING>, + <27 IRQ_TYPE_EDGE_RISING>, + <28 IRQ_TYPE_EDGE_RISING>, + <29 IRQ_TYPE_EDGE_RISING>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + }; + + sdcc1bam:dma at 12182000{ + compatible = "qcom,bam-v1.3.0"; + reg = <0x12182000 0x8000>; + interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>; + clocks = <&gcc SDC1_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + sdcc2bam:dma at 12142000{ + compatible = "qcom,bam-v1.3.0"; + reg = <0x12142000 0x8000>; + interrupts = <GIC_SPI 97 IRQ_TYPE_NONE>; + clocks = <&gcc SDC2_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + sdcc1: sdcc at 12180000 { + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + reg = <0x12180000 0x2000>; + interrupts = <GIC_SPI 104 IRQ_TYPE_NONE>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <48000000>; + cap-sd-highspeed; + cap-mmc-highspeed; + vmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; + dma-names = "tx", "rx"; + assigned-clocks = <&gcc SDC1_CLK>; + assigned-clock-rates = <400000>; + }; + + sdcc2: sdcc at 12140000 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + status = "disabled"; + reg = <0x12140000 0x2000>; + interrupts = <GIC_SPI 103 IRQ_TYPE_NONE>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <48000000>; + no-1-8-v; + vmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc2bam 2>, <&sdcc2bam 1>; + dma-names = "tx", "rx"; + assigned-clocks = <&gcc SDC2_CLK>; + assigned-clock-rates = <400000>; + }; + }; + + tcsr: syscon at 1a400000 { + compatible = "qcom,tcsr-mdm9615", "syscon"; + reg = <0x1a400000 0x100>; + }; + + rpm: rpm at 108000 { + compatible = "qcom,rpm-mdm9615"; + reg = <0x108000 0x1000>; + + qcom,ipc = <&l2cc 0x8 2>; + + interrupts = <0 19 0>, <0 21 0>, <0 22 0>; + interrupt-names = "ack", "err", "wakeup"; + + regulators { + compatible = "qcom,rpm-pm8018-regulators"; + + vin_lvs1-supply = <&pm8018_s3>; + + vdd_l7-supply = <&pm8018_s4>; + vdd_l8-supply = <&pm8018_s3>; + vdd_l9_l10_l11_l12-supply = <&pm8018_s5>; + + /* Buck SMPS */ + pm8018_s1: s1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1150000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + pm8018_s2: s2 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1300000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + pm8018_s3: s3 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + pm8018_s4: s4 { + regulator-min-microvolt = <2100000>; + regulator-max-microvolt = <2200000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + pm8018_s5: s5 { + regulator-always-on; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + /* PMOS LDO */ + pm8018_l2: l2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + pm8018_l3: l3 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + pm8018_l4: l4 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + bias-pull-down; + }; + + pm8018_l5: l5 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + bias-pull-down; + }; + + pm8018_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2850000>; + bias-pull-down; + }; + + pm8018_l7: l7 { + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <1900000>; + bias-pull-down; + }; + + pm8018_l8: l8 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + bias-pull-down; + }; + + pm8018_l9: l9 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1150000>; + bias-pull-down; + }; + + pm8018_l10: l10 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + bias-pull-down; + }; + + pm8018_l11: l11 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + bias-pull-down; + }; + + pm8018_l12: l12 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + bias-pull-down; + }; + + pm8018_l13: l13 { + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + pm8018_l14: l14 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + bias-pull-down; + }; + + /* Low Voltage Switch */ + pm8018_lvs1: lvs1 { + bias-pull-down; + }; + + pm8018_vdd_dig_corner: dig_corner { + regulator-min-microvolt = <1>; + regulator-max-microvolt = <4>; + }; + }; + }; + + /* OTG */ + usb1_phy: phy at 12500000 { + compatible = "qcom,usb-otg-snps"; + reg = <0x12500000 0x400>; + interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>; + dr_mode = "otg"; + status = "disabled"; + + clocks = <&gcc USB_HS1_H_CLK>, + <&gcc USB_HS1_SYSTEM_CLK>; + clock-names = "iface", "core"; + + resets = <&gcc USB_HS1_RESET>; + reset-names = "link"; + vddcx-supply = <&pm8018_vdd_dig_corner>; + qcom,vdd-levels = <1 2 4>; + v3p3-supply = <&pm8018_l4>; + v1p8-supply = <&pm8018_l2>; + }; + + /* OTG */ + usb1bam: dma at 12502000{ + compatible = "qcom,bam-v1.3.0"; + reg = <0x12502000 0x8000>; + interrupts = <GIC_SPI 94 IRQ_TYPE_NONE>; + clocks = <&gcc DMA_BAM_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + status = "disabled"; + }; + + usb1: usb at 12500000 { + compatible = "qcom,ehci-host"; + reg = <0x12500000 0x400>; + interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>; + status = "disabled"; + usb-phy = <&usb1_phy>; + }; + + gadget1: gadget at 12500000 { + compatible = "qcom,ci-hdrc"; + reg = <0x12500000 0x400>; + interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>; + status = "disabled"; + dr_mode = "peripheral"; + usb-phy = <&usb1_phy>; + }; + + usb2_phy: phy at 12540000 { + compatible = "qcom,usb-hsic-phy"; + reg = <0x12540000 0x400>; + interrupts = <GIC_SPI 232 IRQ_TYPE_NONE>; + status = "disabled"; + dr_mode = "host"; + + clocks = <&gcc USB_HSIC_SYSTEM_CLK>, + <&gcc USB_HSIC_XCVR_FS_CLK>, + <&gcc USB_HSIC_HSIC_CLK>, + <&gcc USB_HSIC_HSIO_CAL_CLK>, + <&gcc USB_HSIC_H_CLK>; + clock-names = "core", "alt-core", "phy", "cal", "iface"; + assigned-clocks = <&gcc USB_HSIC_XCVR_FS_CLK>, + <&gcc USB_HSIC_SYSTEM_CLK>, + <&gcc USB_HSIC_HSIC_CLK>; + assigned-clock-rates = <60000000>, + <64000000>, + <480000000>; + resets = <&gcc USB_HSIC_RESET>; + reset-names = "link"; + vddcx-supply = <&pm8018_vdd_dig_corner>; + qcom,vdd-levels = <1 2 4>; + phy_type = "hsic"; + + qcom,tlmm = <&msmgpio>; + qcom,tlmm-cfg = <0x20CC 0x034A4E10 + 0x20C8 0x034A4E10>; + }; + + usb2bam: dma at 12542000{ + compatible = "qcom,bam-v1.3.0"; + reg = <0x12542000 0x8000>; + interrupts = <GIC_SPI 231 IRQ_TYPE_NONE>; + clocks = <&gcc DMA_BAM_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + status = "disabled"; + }; + + usb2: usb at 12540000 { + compatible = "qcom,ehci-host"; + reg = <0x12540000 0x400>; + interrupts = <GIC_SPI 232 IRQ_TYPE_NONE>; + status = "disabled"; + usb-phy = <&usb2_phy>; + dr_mode = "host"; + }; + }; +}; -- 1.9.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 2/2] dt-bindings: qcom: Add MDM9615 bindings 2016-06-17 10:35 ` Neil Armstrong (?) @ 2016-06-17 10:35 ` Neil Armstrong -1 siblings, 0 replies; 13+ messages in thread From: Neil Armstrong @ 2016-06-17 10:35 UTC (permalink / raw) To: andy.gross, david.brown, linux, sboyd Cc: devicetree, Neil Armstrong, linux-arm-msm, linux-kernel, linux-soc, linux-arm-kernel Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- Documentation/devicetree/bindings/arm/qcom.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.txt b/Documentation/devicetree/bindings/arm/qcom.txt index 3e24518..43abf4e 100644 --- a/Documentation/devicetree/bindings/arm/qcom.txt +++ b/Documentation/devicetree/bindings/arm/qcom.txt @@ -22,6 +22,7 @@ The 'SoC' element must be one of the following strings: msm8916 msm8974 msm8996 + mdm9615 The 'board' element must be one of the following strings: -- 1.9.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 2/2] dt-bindings: qcom: Add MDM9615 bindings @ 2016-06-17 10:35 ` Neil Armstrong 0 siblings, 0 replies; 13+ messages in thread From: Neil Armstrong @ 2016-06-17 10:35 UTC (permalink / raw) To: andy.gross, david.brown, linux, sboyd Cc: Neil Armstrong, devicetree, linux-kernel, linux-arm-msm, linux-soc, linux-arm-kernel Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- Documentation/devicetree/bindings/arm/qcom.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.txt b/Documentation/devicetree/bindings/arm/qcom.txt index 3e24518..43abf4e 100644 --- a/Documentation/devicetree/bindings/arm/qcom.txt +++ b/Documentation/devicetree/bindings/arm/qcom.txt @@ -22,6 +22,7 @@ The 'SoC' element must be one of the following strings: msm8916 msm8974 msm8996 + mdm9615 The 'board' element must be one of the following strings: -- 1.9.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 2/2] dt-bindings: qcom: Add MDM9615 bindings @ 2016-06-17 10:35 ` Neil Armstrong 0 siblings, 0 replies; 13+ messages in thread From: Neil Armstrong @ 2016-06-17 10:35 UTC (permalink / raw) To: linux-arm-kernel Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- Documentation/devicetree/bindings/arm/qcom.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.txt b/Documentation/devicetree/bindings/arm/qcom.txt index 3e24518..43abf4e 100644 --- a/Documentation/devicetree/bindings/arm/qcom.txt +++ b/Documentation/devicetree/bindings/arm/qcom.txt @@ -22,6 +22,7 @@ The 'SoC' element must be one of the following strings: msm8916 msm8974 msm8996 + mdm9615 The 'board' element must be one of the following strings: -- 1.9.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 2/2] dt-bindings: qcom: Add MDM9615 bindings 2016-06-17 10:35 ` Neil Armstrong (?) @ 2016-06-20 16:26 ` Rob Herring -1 siblings, 0 replies; 13+ messages in thread From: Rob Herring @ 2016-06-20 16:26 UTC (permalink / raw) To: Neil Armstrong Cc: devicetree, linux-arm-msm, sboyd, linux, linux-kernel, david.brown, andy.gross, linux-soc, linux-arm-kernel On Fri, Jun 17, 2016 at 12:35:04PM +0200, Neil Armstrong wrote: > Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> > --- > Documentation/devicetree/bindings/arm/qcom.txt | 1 + > 1 file changed, 1 insertion(+) Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/2] dt-bindings: qcom: Add MDM9615 bindings @ 2016-06-20 16:26 ` Rob Herring 0 siblings, 0 replies; 13+ messages in thread From: Rob Herring @ 2016-06-20 16:26 UTC (permalink / raw) To: Neil Armstrong Cc: andy.gross, david.brown, linux, sboyd, devicetree, linux-kernel, linux-arm-msm, linux-soc, linux-arm-kernel On Fri, Jun 17, 2016 at 12:35:04PM +0200, Neil Armstrong wrote: > Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> > --- > Documentation/devicetree/bindings/arm/qcom.txt | 1 + > 1 file changed, 1 insertion(+) Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 2/2] dt-bindings: qcom: Add MDM9615 bindings @ 2016-06-20 16:26 ` Rob Herring 0 siblings, 0 replies; 13+ messages in thread From: Rob Herring @ 2016-06-20 16:26 UTC (permalink / raw) To: linux-arm-kernel On Fri, Jun 17, 2016 at 12:35:04PM +0200, Neil Armstrong wrote: > Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> > --- > Documentation/devicetree/bindings/arm/qcom.txt | 1 + > 1 file changed, 1 insertion(+) Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/2] dt-bindings: qcom: Add MDM9615 bindings 2016-06-17 10:35 ` Neil Armstrong (?) @ 2016-06-20 23:54 ` Stephen Boyd -1 siblings, 0 replies; 13+ messages in thread From: Stephen Boyd @ 2016-06-20 23:54 UTC (permalink / raw) To: Neil Armstrong Cc: devicetree, linux-arm-msm, linux, linux-kernel, david.brown, andy.gross, linux-soc, linux-arm-kernel On 06/17, Neil Armstrong wrote: > Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> > --- Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/2] dt-bindings: qcom: Add MDM9615 bindings @ 2016-06-20 23:54 ` Stephen Boyd 0 siblings, 0 replies; 13+ messages in thread From: Stephen Boyd @ 2016-06-20 23:54 UTC (permalink / raw) To: Neil Armstrong Cc: andy.gross, david.brown, linux, devicetree, linux-kernel, linux-arm-msm, linux-soc, linux-arm-kernel On 06/17, Neil Armstrong wrote: > Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> > --- Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 2/2] dt-bindings: qcom: Add MDM9615 bindings @ 2016-06-20 23:54 ` Stephen Boyd 0 siblings, 0 replies; 13+ messages in thread From: Stephen Boyd @ 2016-06-20 23:54 UTC (permalink / raw) To: linux-arm-kernel On 06/17, Neil Armstrong wrote: > Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> > --- Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project ^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2016-06-20 23:58 UTC | newest] Thread overview: 13+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2016-06-17 10:35 [PATCH 0/2] ARM: dts: Add support for the MDM9615 Neil Armstrong 2016-06-17 10:35 ` Neil Armstrong 2016-06-17 10:35 ` [PATCH 1/2] ARM: dts: Add MSM9615 dtsi Neil Armstrong 2016-06-17 10:35 ` Neil Armstrong 2016-06-17 10:35 ` [PATCH 2/2] dt-bindings: qcom: Add MDM9615 bindings Neil Armstrong 2016-06-17 10:35 ` Neil Armstrong 2016-06-17 10:35 ` Neil Armstrong 2016-06-20 16:26 ` Rob Herring 2016-06-20 16:26 ` Rob Herring 2016-06-20 16:26 ` Rob Herring 2016-06-20 23:54 ` Stephen Boyd 2016-06-20 23:54 ` Stephen Boyd 2016-06-20 23:54 ` Stephen Boyd
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