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From: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
To: William Wu <william.wu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Cc: gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org,
	balbi-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
	heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	briannorris-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org,
	dianders-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org,
	kever.yang-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
	huangtao-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
	frank.wang-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
	eddie.cai-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
	John.Youn-HKixBCOQz3hWk0Htik3J/w@public.gmane.org,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-usb-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	sergei.shtylyov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org,
	mark.rutland-5wv7dgnIgG8@public.gmane.org,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH v5 3/5] usb: dwc3: add phyif_utmi_quirk
Date: Thu, 30 Jun 2016 21:35:52 -0500	[thread overview]
Message-ID: <20160701023552.GA26314@rob-hp-laptop> (raw)
In-Reply-To: <1467285176-25222-4-git-send-email-william.wu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>

On Thu, Jun 30, 2016 at 07:12:54PM +0800, William Wu wrote:
> Add a quirk to configure the core to support the
> UTMI+ PHY with an 8- or 16-bit interface. UTMI+ PHY
> interface is hardware property, and it's platform
> dependent. Normall, the PHYIf can be configured
> during coreconsultant. But for some specific usb
> cores(e.g. rk3399 soc dwc3), the default PHYIf
> configuration value is fault, so we need to
> reconfigure it by software.
> 
> And refer to the dwc3 databook, the GUSB2PHYCFG.USBTRDTIM
> must be set to the corresponding value according to
> the UTMI+ PHY interface.
> 
> Signed-off-by: William Wu <william.wu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> ---
> Changes in v5:
> - None
> 
> Changes in v4:
> - rebase on top of balbi testing/next, remove pdata (balbi)
> 
> Changes in v3:
> - None
> 
> Changes in v2:
> - add a quirk for phyif_utmi (balbi)
> 
>  Documentation/devicetree/bindings/usb/dwc3.txt |  4 ++++
>  drivers/usb/dwc3/core.c                        | 19 +++++++++++++++++++
>  drivers/usb/dwc3/core.h                        | 12 ++++++++++++
>  3 files changed, 35 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
> index 1ada121..34d13a5 100644
> --- a/Documentation/devicetree/bindings/usb/dwc3.txt
> +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
> @@ -42,6 +42,10 @@ Optional properties:
>   - snps,dis_u2_freeclk_exists_quirk: when set, clear the u2_freeclk_exists
>  			in GUSB2PHYCFG, specify that USB2 PHY doesn't provide
>  			a free-running PHY clock.
> + - snps,phyif_utmi_quirk: when set core will set phyif UTMI+ interface.

This isn't really what I'd call a quirk.

> + - snps,phyif_utmi: the value to configure the core to support a UTMI+ PHY
> +			with an 8- or 16-bit interface. Value 0 select 8-bit
> +			interface, value 1 select 16-bit interface.

These seem like they should be standard properties for setting the phy 
type/mode. I think we already have something defined in fact.

Rob
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WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: William Wu <william.wu@rock-chips.com>
Cc: gregkh@linuxfoundation.org, balbi@kernel.org, heiko@sntech.de,
	linux-rockchip@lists.infradead.org, briannorris@google.com,
	dianders@google.com, kever.yang@rock-chips.com,
	huangtao@rock-chips.com, frank.wang@rock-chips.com,
	eddie.cai@rock-chips.com, John.Youn@synopsys.com,
	linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org,
	sergei.shtylyov@cogentembedded.com, mark.rutland@arm.com,
	devicetree@vger.kernel.org
Subject: Re: [PATCH v5 3/5] usb: dwc3: add phyif_utmi_quirk
Date: Thu, 30 Jun 2016 21:35:52 -0500	[thread overview]
Message-ID: <20160701023552.GA26314@rob-hp-laptop> (raw)
In-Reply-To: <1467285176-25222-4-git-send-email-william.wu@rock-chips.com>

On Thu, Jun 30, 2016 at 07:12:54PM +0800, William Wu wrote:
> Add a quirk to configure the core to support the
> UTMI+ PHY with an 8- or 16-bit interface. UTMI+ PHY
> interface is hardware property, and it's platform
> dependent. Normall, the PHYIf can be configured
> during coreconsultant. But for some specific usb
> cores(e.g. rk3399 soc dwc3), the default PHYIf
> configuration value is fault, so we need to
> reconfigure it by software.
> 
> And refer to the dwc3 databook, the GUSB2PHYCFG.USBTRDTIM
> must be set to the corresponding value according to
> the UTMI+ PHY interface.
> 
> Signed-off-by: William Wu <william.wu@rock-chips.com>
> ---
> Changes in v5:
> - None
> 
> Changes in v4:
> - rebase on top of balbi testing/next, remove pdata (balbi)
> 
> Changes in v3:
> - None
> 
> Changes in v2:
> - add a quirk for phyif_utmi (balbi)
> 
>  Documentation/devicetree/bindings/usb/dwc3.txt |  4 ++++
>  drivers/usb/dwc3/core.c                        | 19 +++++++++++++++++++
>  drivers/usb/dwc3/core.h                        | 12 ++++++++++++
>  3 files changed, 35 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
> index 1ada121..34d13a5 100644
> --- a/Documentation/devicetree/bindings/usb/dwc3.txt
> +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
> @@ -42,6 +42,10 @@ Optional properties:
>   - snps,dis_u2_freeclk_exists_quirk: when set, clear the u2_freeclk_exists
>  			in GUSB2PHYCFG, specify that USB2 PHY doesn't provide
>  			a free-running PHY clock.
> + - snps,phyif_utmi_quirk: when set core will set phyif UTMI+ interface.

This isn't really what I'd call a quirk.

> + - snps,phyif_utmi: the value to configure the core to support a UTMI+ PHY
> +			with an 8- or 16-bit interface. Value 0 select 8-bit
> +			interface, value 1 select 16-bit interface.

These seem like they should be standard properties for setting the phy 
type/mode. I think we already have something defined in fact.

Rob

  parent reply	other threads:[~2016-07-01  2:35 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-06-30 11:12 [PATCH v5 0/5] support rockchip dwc3 driver William Wu
2016-06-30 11:12 ` William Wu
2016-06-30 11:12 ` [PATCH v5 3/5] usb: dwc3: add phyif_utmi_quirk William Wu
     [not found]   ` <1467285176-25222-4-git-send-email-william.wu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2016-07-01  2:35     ` Rob Herring [this message]
2016-07-01  2:35       ` Rob Herring
2016-07-01  3:45       ` [PATCH v5 3/5] usb: dwc3: add phyif_utmi_quirk[Involving remittance information, please pay attention to the safety of property] William Wu
2016-07-01  3:53       ` William Wu
     [not found] ` <1467285176-25222-1-git-send-email-william.wu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2016-06-30 11:12   ` [PATCH v5 1/5] usb: dwc3: of-simple: add compatible for rockchip rk3399 William Wu
2016-06-30 11:12     ` William Wu
2016-06-30 11:12   ` [PATCH v5 2/5] usb: dwc3: add dis_u2_freeclk_exists_quirk William Wu
2016-06-30 11:12     ` William Wu
2016-07-01  2:32     ` Rob Herring
2016-07-01  2:49       ` [PATCH v5 2/5] usb: dwc3: add dis_u2_freeclk_exists_quirk[Involving remittance information, please pay attention to the safety of property] William Wu
2016-07-01  2:49         ` William Wu
2016-06-30 11:12   ` [PATCH v5 4/5] usb: dwc3: add dis_del_phy_power_chg_quirk William Wu
2016-06-30 11:12     ` William Wu
     [not found]     ` <1467285176-25222-5-git-send-email-william.wu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2016-07-01  2:38       ` Rob Herring
2016-07-01  2:38         ` Rob Herring
2016-07-01  2:51         ` [PATCH v5 4/5] usb: dwc3: add dis_del_phy_power_chg_quirk[Involving remittance information, please pay attention to the safety of property] William Wu
2016-06-30 11:16 ` [PATCH v5 5/5] usb: dwc3: rockchip: add devicetree bindings documentation William Wu
2016-06-30 12:15   ` Heiko Stuebner
2016-07-01  1:20     ` William Wu
2016-07-01  1:20       ` William Wu

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