From: "Michael S. Tsirkin" <mst@redhat.com>
To: Peter Xu <peterx@redhat.com>
Cc: qemu-devel@nongnu.org, imammedo@redhat.com, rth@twiddle.net,
ehabkost@redhat.com, jasowang@redhat.com, marcel@redhat.com,
pbonzini@redhat.com, jan.kiszka@web.de, rkrcmar@redhat.com,
alex.williamson@redhat.com, wexu@redhat.com,
davidkiarie4@gmail.com
Subject: Re: [Qemu-devel] [PATCH v10 02/26] x86-iommu: provide x86_iommu_get_default
Date: Mon, 4 Jul 2016 18:17:47 +0300 [thread overview]
Message-ID: <20160704181729-mutt-send-email-mst@redhat.com> (raw)
In-Reply-To: <1466495274-5011-3-git-send-email-peterx@redhat.com>
On Tue, Jun 21, 2016 at 03:47:30PM +0800, Peter Xu wrote:
> Instead of searching the device tree every time, one static variable is
> declared for the default system x86 IOMMU device. Also, some VT-d
> macros are replaced by x86 ones.
In the future pls don't mix unrelated changes in same patch like this.
>
> Signed-off-by: Peter Xu <peterx@redhat.com>
> ---
> hw/i386/acpi-build.c | 9 ++-------
> hw/i386/intel_iommu.c | 9 ++++++---
> hw/i386/x86-iommu.c | 23 +++++++++++++++++++++++
> include/hw/i386/intel_iommu.h | 1 -
> include/hw/i386/x86-iommu.h | 9 +++++++++
> 5 files changed, 40 insertions(+), 11 deletions(-)
>
> diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
> index 8ca2032..161f089 100644
> --- a/hw/i386/acpi-build.c
> +++ b/hw/i386/acpi-build.c
> @@ -50,7 +50,7 @@
> #include "hw/i386/ich9.h"
> #include "hw/pci/pci_bus.h"
> #include "hw/pci-host/q35.h"
> -#include "hw/i386/intel_iommu.h"
> +#include "hw/i386/x86-iommu.h"
> #include "hw/timer/hpet.h"
>
> #include "hw/acpi/aml-build.h"
> @@ -2500,12 +2500,7 @@ static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
>
> static bool acpi_has_iommu(void)
> {
> - bool ambiguous;
> - Object *intel_iommu;
> -
> - intel_iommu = object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE,
> - &ambiguous);
> - return intel_iommu && !ambiguous;
> + return !!x86_iommu_get_default();
> }
>
> static
> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> index 2734f6b..1936c41 100644
> --- a/hw/i386/intel_iommu.c
> +++ b/hw/i386/intel_iommu.c
> @@ -26,6 +26,8 @@
> #include "hw/pci/pci.h"
> #include "hw/pci/pci_bus.h"
> #include "hw/i386/pc.h"
> +#include "hw/boards.h"
> +#include "hw/i386/x86-iommu.h"
>
> /*#define DEBUG_INTEL_IOMMU*/
> #ifdef DEBUG_INTEL_IOMMU
> @@ -192,7 +194,7 @@ static void vtd_reset_context_cache(IntelIOMMUState *s)
>
> VTD_DPRINTF(CACHE, "global context_cache_gen=1");
> while (g_hash_table_iter_next (&bus_it, NULL, (void**)&vtd_bus)) {
> - for (devfn_it = 0; devfn_it < VTD_PCI_DEVFN_MAX; ++devfn_it) {
> + for (devfn_it = 0; devfn_it < X86_IOMMU_PCI_DEVFN_MAX; ++devfn_it) {
> vtd_as = vtd_bus->dev_as[devfn_it];
> if (!vtd_as) {
> continue;
> @@ -964,7 +966,7 @@ static void vtd_context_device_invalidate(IntelIOMMUState *s,
> vtd_bus = vtd_find_as_from_bus_num(s, VTD_SID_TO_BUS(source_id));
> if (vtd_bus) {
> devfn = VTD_SID_TO_DEVFN(source_id);
> - for (devfn_it = 0; devfn_it < VTD_PCI_DEVFN_MAX; ++devfn_it) {
> + for (devfn_it = 0; devfn_it < X86_IOMMU_PCI_DEVFN_MAX; ++devfn_it) {
> vtd_as = vtd_bus->dev_as[devfn_it];
> if (vtd_as && ((devfn_it & mask) == (devfn & mask))) {
> VTD_DPRINTF(INV, "invalidate context-cahce of devfn 0x%"PRIx16,
> @@ -1906,7 +1908,8 @@ VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn)
>
> if (!vtd_bus) {
> /* No corresponding free() */
> - vtd_bus = g_malloc0(sizeof(VTDBus) + sizeof(VTDAddressSpace *) * VTD_PCI_DEVFN_MAX);
> + vtd_bus = g_malloc0(sizeof(VTDBus) + sizeof(VTDAddressSpace *) * \
> + X86_IOMMU_PCI_DEVFN_MAX);
> vtd_bus->bus = bus;
> key = (uintptr_t)bus;
> g_hash_table_insert(s->vtd_as_by_busptr, &key, vtd_bus);
> diff --git a/hw/i386/x86-iommu.c b/hw/i386/x86-iommu.c
> index d739afb..f395139 100644
> --- a/hw/i386/x86-iommu.c
> +++ b/hw/i386/x86-iommu.c
> @@ -21,6 +21,28 @@
> #include "hw/sysbus.h"
> #include "hw/boards.h"
> #include "hw/i386/x86-iommu.h"
> +#include "qemu/error-report.h"
> +
> +/* Default X86 IOMMU device */
> +static X86IOMMUState *x86_iommu_default = NULL;
> +
> +static void x86_iommu_set_default(X86IOMMUState *x86_iommu)
> +{
> + assert(x86_iommu);
> +
> + if (x86_iommu_default) {
> + error_report("QEMU does not support multiple vIOMMUs "
> + "for x86 yet.");
> + exit(1);
> + }
> +
> + x86_iommu_default = x86_iommu;
> +}
> +
> +X86IOMMUState *x86_iommu_get_default(void)
> +{
> + return x86_iommu_default;
> +}
>
> static void x86_iommu_realize(DeviceState *dev, Error **errp)
> {
> @@ -28,6 +50,7 @@ static void x86_iommu_realize(DeviceState *dev, Error **errp)
> if (x86_class->realize) {
> x86_class->realize(dev, errp);
> }
> + x86_iommu_set_default(X86_IOMMU_DEVICE(dev));
> }
>
> static void x86_iommu_class_init(ObjectClass *klass, void *data)
> diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h
> index 680a0c4..0794309 100644
> --- a/include/hw/i386/intel_iommu.h
> +++ b/include/hw/i386/intel_iommu.h
> @@ -35,7 +35,6 @@
> #define VTD_PCI_BUS_MAX 256
> #define VTD_PCI_SLOT_MAX 32
> #define VTD_PCI_FUNC_MAX 8
> -#define VTD_PCI_DEVFN_MAX 256
> #define VTD_PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
> #define VTD_PCI_FUNC(devfn) ((devfn) & 0x07)
> #define VTD_SID_TO_BUS(sid) (((sid) >> 8) & 0xff)
> diff --git a/include/hw/i386/x86-iommu.h b/include/hw/i386/x86-iommu.h
> index 924f39a..d6991cb 100644
> --- a/include/hw/i386/x86-iommu.h
> +++ b/include/hw/i386/x86-iommu.h
> @@ -30,6 +30,9 @@
> #define X86_IOMMU_GET_CLASS(obj) \
> OBJECT_GET_CLASS(X86IOMMUClass, obj, TYPE_X86_IOMMU_DEVICE)
>
> +#define X86_IOMMU_PCI_DEVFN_MAX 256
> +#define X86_IOMMU_SID_INVALID (0xffff)
> +
> typedef struct X86IOMMUState X86IOMMUState;
> typedef struct X86IOMMUClass X86IOMMUClass;
>
> @@ -43,4 +46,10 @@ struct X86IOMMUState {
> SysBusDevice busdev;
> };
>
> +/**
> + * x86_iommu_get_default - get default IOMMU device
> + * @return: pointer to default IOMMU device
> + */
> +X86IOMMUState *x86_iommu_get_default(void);
> +
> #endif
> --
> 2.4.11
next prev parent reply other threads:[~2016-07-04 15:17 UTC|newest]
Thread overview: 63+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-21 7:47 [Qemu-devel] [PATCH v10 00/26] IOMMU: Enable interrupt remapping for Intel IOMMU Peter Xu
2016-06-21 7:47 ` [Qemu-devel] [PATCH v10 01/26] x86-iommu: introduce parent class Peter Xu
2016-06-24 7:10 ` [Qemu-devel] [PATCH v10 27/26] intel_iommu: disallow kernel-irqchip=on with IR Peter Xu
2016-06-24 9:20 ` Peter Xu
2016-07-04 15:39 ` Michael S. Tsirkin
2016-07-05 3:51 ` Peter Xu
2016-07-11 10:17 ` David Kiarie
2016-07-11 12:08 ` Peter Xu
2016-06-21 7:47 ` [Qemu-devel] [PATCH v10 02/26] x86-iommu: provide x86_iommu_get_default Peter Xu
2016-07-04 15:16 ` Michael S. Tsirkin
2016-07-05 5:11 ` Peter Xu
2016-07-04 15:17 ` Michael S. Tsirkin [this message]
2016-07-05 5:12 ` Peter Xu
2016-06-21 7:47 ` [Qemu-devel] [PATCH v10 03/26] x86-iommu: q35: generalize find_add_as() Peter Xu
2016-07-04 15:16 ` Michael S. Tsirkin
2016-07-04 16:08 ` Paolo Bonzini
2016-07-04 16:35 ` Michael S. Tsirkin
2016-07-04 16:40 ` Paolo Bonzini
2016-06-21 7:47 ` [Qemu-devel] [PATCH v10 04/26] x86-iommu: introduce "intremap" property Peter Xu
2016-06-21 7:47 ` [Qemu-devel] [PATCH v10 05/26] acpi: enable INTR for DMAR report structure Peter Xu
2016-07-04 15:14 ` Michael S. Tsirkin
2016-07-05 6:39 ` Peter Xu
2016-06-21 7:47 ` [Qemu-devel] [PATCH v10 06/26] intel_iommu: allow queued invalidation for IR Peter Xu
2016-06-21 7:47 ` [Qemu-devel] [PATCH v10 07/26] intel_iommu: set IR bit for ECAP register Peter Xu
2016-06-21 7:47 ` [Qemu-devel] [PATCH v10 08/26] acpi: add DMAR scope definition for root IOAPIC Peter Xu
2016-07-04 15:22 ` Michael S. Tsirkin
2016-07-05 7:30 ` Peter Xu
2016-06-21 7:47 ` [Qemu-devel] [PATCH v10 09/26] intel_iommu: define interrupt remap table addr register Peter Xu
2016-06-21 7:47 ` [Qemu-devel] [PATCH v10 10/26] intel_iommu: handle interrupt remap enable Peter Xu
2016-06-21 7:47 ` [Qemu-devel] [PATCH v10 11/26] intel_iommu: define several structs for IOMMU IR Peter Xu
2016-06-21 7:47 ` [Qemu-devel] [PATCH v10 12/26] intel_iommu: add IR translation faults defines Peter Xu
2016-06-21 7:47 ` [Qemu-devel] [PATCH v10 13/26] intel_iommu: Add support for PCI MSI remap Peter Xu
2016-06-21 7:47 ` [Qemu-devel] [PATCH v10 14/26] q35: ioapic: add support for emulated IOAPIC IR Peter Xu
2016-06-21 7:47 ` [Qemu-devel] [PATCH v10 15/26] ioapic: introduce ioapic_entry_parse() helper Peter Xu
2016-06-21 7:47 ` [Qemu-devel] [PATCH v10 16/26] intel_iommu: add support for split irqchip Peter Xu
2016-06-25 8:08 ` Jan Kiszka
2016-06-25 13:18 ` Peter Xu
2016-06-25 15:18 ` Jan Kiszka
2016-06-26 1:48 ` Peter Xu
2016-06-26 13:27 ` Jan Kiszka
2016-06-28 6:10 ` Michael S. Tsirkin
2016-06-28 7:25 ` Peter Xu
2017-01-03 6:15 ` Peter Xu
2017-01-04 10:33 ` Jan Kiszka
2017-01-05 2:21 ` Peter Xu
2016-07-04 14:32 ` Paolo Bonzini
2016-06-21 7:47 ` [Qemu-devel] [PATCH v10 17/26] x86-iommu: introduce IEC notifiers Peter Xu
2016-07-04 14:22 ` Paolo Bonzini
2016-07-05 7:32 ` Peter Xu
2016-06-21 7:47 ` [Qemu-devel] [PATCH v10 18/26] ioapic: register IOMMU IEC notifier for ioapic Peter Xu
2016-06-21 7:47 ` [Qemu-devel] [PATCH v10 19/26] intel_iommu: Add support for Extended Interrupt Mode Peter Xu
2016-06-21 7:47 ` [Qemu-devel] [PATCH v10 20/26] intel_iommu: add SID validation for IR Peter Xu
2016-06-21 7:47 ` [Qemu-devel] [PATCH v10 21/26] kvm-irqchip: simplify kvm_irqchip_add_msi_route Peter Xu
2016-06-21 7:47 ` [Qemu-devel] [PATCH v10 22/26] kvm-irqchip: i386: add hook for add/remove virq Peter Xu
2016-06-21 7:47 ` [Qemu-devel] [PATCH v10 23/26] kvm-irqchip: x86: add msi route notify fn Peter Xu
2016-06-21 7:47 ` [Qemu-devel] [PATCH v10 24/26] kvm-irqchip: do explicit commit when update irq Peter Xu
2016-06-22 3:42 ` [Qemu-devel] [PATCH v10.2 24/26] kvm-irqchip: introduce kvm_irqchip_update_msi_route_no_commit Peter Xu
2016-07-04 14:23 ` [Qemu-devel] [PATCH v10 24/26] kvm-irqchip: do explicit commit when update irq Paolo Bonzini
2016-07-05 7:35 ` Peter Xu
2016-06-21 7:47 ` [Qemu-devel] [PATCH v10 25/26] intel_iommu: support all masks in interrupt entry cache invalidation Peter Xu
2016-06-21 7:47 ` [Qemu-devel] [PATCH v10 26/26] kvm-all: add trace events for kvm irqchip ops Peter Xu
2016-07-04 14:33 ` [Qemu-devel] [PATCH v10 00/26] IOMMU: Enable interrupt remapping for Intel IOMMU Paolo Bonzini
2016-07-04 16:39 ` Michael S. Tsirkin
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