From: David Gibson <david@gibson.dropbear.id.au>
To: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
aneesh.kumar@linux.vnet.ibm.com, benh@kernel.crashing.org,
Swapnil Bokade <bokadeswapnil@gmail.com>,
Sandipan Das <sandipandas1990@gmail.com>
Subject: Re: [Qemu-devel] [RFC v1 09/13] target-ppc: add cmpeqb instruction
Date: Fri, 22 Jul 2016 14:57:49 +1000 [thread overview]
Message-ID: <20160722045749.GP15941@voom.fritz.box> (raw)
In-Reply-To: <1468861517-2508-10-git-send-email-nikunj@linux.vnet.ibm.com>
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On Mon, Jul 18, 2016 at 10:35:13PM +0530, Nikunj A Dadhania wrote:
> From: Swapnil Bokade <bokadeswapnil@gmail.com>
>
> Search a byte in the stream of 8bytes provided in the register
>
> Signed-off-by: Sandipan Das <sandipandas1990@gmail.com>
> [ Modified the logic to use lesser temporaries ]
> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
rth's reference may obsolete the suggestions below.
> ---
> target-ppc/translate.c | 27 +++++++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index a57f7dd..8f7ff49 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -856,6 +856,32 @@ static void gen_cmprb(DisasContext *ctx)
> tcg_temp_free(src2hi);
> }
>
> +/* cmpeqb */
> +static void gen_cmpeqb(DisasContext *ctx)
> +{
> + TCGLabel *l1 = gen_new_label();
> + TCGLabel *l2 = gen_new_label();
> + TCGv src1 = tcg_temp_local_new();
> + TCGv t0 = tcg_temp_local_new();
> + TCGv arg1 = cpu_gpr[rB(ctx->opcode)];
> + int i;
> +
> + tcg_gen_andi_tl(src1, cpu_gpr[rA(ctx->opcode)], 0xFF);
> + for (i = 0; i < 64; i += 8) {
> + tcg_gen_shri_tl(t0, arg1, i);
> + tcg_gen_andi_tl(t0, t0, 0xFF);
Shifting direct from the original arg each time seems awkward when you
can just shift a working reg by 8 bits each loop. I suspect that
could save you a temporary.
> + tcg_gen_brcond_tl(TCG_COND_EQ, src1, t0, l1);
> + }
> + tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0);
> + tcg_gen_br(l2);
> + gen_set_label(l1);
> + /* Set match bit, i.e. CRF_GT */
> + tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 1 << CRF_GT);
> + gen_set_label(l2);
You should only need one branch at most, either by initializing the
CRF first, or by moving a variable to it.
> + tcg_temp_free(src1);
> + tcg_temp_free(t0);
> +}
> +
> /* isel (PowerPC 2.03 specification) */
> static void gen_isel(DisasContext *ctx)
> {
> @@ -10040,6 +10066,7 @@ GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
> GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
> GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
> GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
> +GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
> GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
> GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
> GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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next prev parent reply other threads:[~2016-07-22 5:07 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-07-18 17:05 [Qemu-devel] [RFC v1 00/13] POWER9 TCG enablements - part1 Nikunj A Dadhania
2016-07-18 17:05 ` [Qemu-devel] [RFC v1 01/13] target-ppc: Introduce Power9 family Nikunj A Dadhania
2016-07-18 17:05 ` [Qemu-devel] [RFC v1 02/13] target-ppc: Introduce POWER ISA 3.0 flag Nikunj A Dadhania
2016-07-18 17:05 ` [Qemu-devel] [RFC v1 03/13] target-ppc: adding addpcis instruction Nikunj A Dadhania
2016-07-21 7:53 ` Nikunj A Dadhania
2016-07-18 17:05 ` [Qemu-devel] [RFC v1 04/13] target-ppc: add cmprb instruction Nikunj A Dadhania
2016-07-18 17:05 ` [Qemu-devel] [RFC v1 05/13] target-ppc: add modulo word operations Nikunj A Dadhania
2016-07-22 4:51 ` David Gibson
2016-07-22 5:29 ` Nikunj A Dadhania
2016-07-22 6:09 ` David Gibson
2016-07-22 6:54 ` Nikunj A Dadhania
2016-07-22 7:12 ` David Gibson
2016-07-22 8:00 ` Nikunj A Dadhania
2016-07-18 17:05 ` [Qemu-devel] [RFC v1 06/13] target-ppc: add modulo dword operations Nikunj A Dadhania
2016-07-18 17:05 ` [Qemu-devel] [RFC v1 07/13] target-ppc: add cnttzd[.] instruction Nikunj A Dadhania
2016-07-21 6:28 ` Richard Henderson
2016-07-21 7:54 ` Nikunj A Dadhania
2016-07-18 17:05 ` [Qemu-devel] [RFC v1 08/13] target-ppc: add cnttzw[.] instruction Nikunj A Dadhania
2016-07-21 6:29 ` Richard Henderson
2016-07-21 7:54 ` Nikunj A Dadhania
2016-07-18 17:05 ` [Qemu-devel] [RFC v1 09/13] target-ppc: add cmpeqb instruction Nikunj A Dadhania
2016-07-18 17:12 ` Nikunj A Dadhania
2016-07-21 6:41 ` Richard Henderson
2016-07-21 8:02 ` Nikunj A Dadhania
2016-07-22 19:28 ` Nikunj A Dadhania
2016-07-23 1:17 ` Richard Henderson
2016-07-23 6:08 ` Nikunj A Dadhania
2016-07-23 16:01 ` Richard Henderson
2016-07-22 4:57 ` David Gibson [this message]
2016-07-18 17:05 ` [Qemu-devel] [RFC v1 10/13] target-ppc: add setb instruction Nikunj A Dadhania
2016-07-21 6:49 ` Richard Henderson
2016-07-22 4:59 ` David Gibson
2016-07-22 5:30 ` Nikunj A Dadhania
2016-07-18 17:05 ` [Qemu-devel] [RFC v1 11/13] target-ppc: add maddld instruction Nikunj A Dadhania
2016-07-21 6:54 ` Richard Henderson
2016-07-21 6:59 ` Richard Henderson
2016-07-18 17:05 ` [Qemu-devel] [RFC v1 12/13] target-ppc: add maddhd and maddhdu instruction Nikunj A Dadhania
2016-07-21 7:02 ` Richard Henderson
2016-07-18 17:05 ` [Qemu-devel] [RFC v1 13/13] target-ppc: introduce opc4 for Expanded Opcode Nikunj A Dadhania
2016-07-22 5:07 ` David Gibson
2016-07-22 5:35 ` Nikunj A Dadhania
2016-07-22 6:08 ` David Gibson
2016-07-22 6:58 ` Nikunj A Dadhania
2016-07-22 9:49 ` Bharata B Rao
2016-07-22 10:00 ` Nikunj A Dadhania
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