From: David Gibson <david@gibson.dropbear.id.au>
To: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
aneesh.kumar@linux.vnet.ibm.com, benh@kernel.crashing.org
Subject: Re: [Qemu-devel] [RFC v1 13/13] target-ppc: introduce opc4 for Expanded Opcode
Date: Fri, 22 Jul 2016 15:07:14 +1000 [thread overview]
Message-ID: <20160722050714.GR15941@voom.fritz.box> (raw)
In-Reply-To: <1468861517-2508-14-git-send-email-nikunj@linux.vnet.ibm.com>
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On Mon, Jul 18, 2016 at 10:35:17PM +0530, Nikunj A Dadhania wrote:
> ISA 3.0 has introduced EO - Expanded Opcode. Introduce third level
> indirect opcode table and corresponding parsing routines.
>
> EO (11:12) Expanded opcode field
> Formats: XX1
>
> EO (11:15) Expanded opcode field
> Formats: VX, X, XX2
>
> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
> ---
> target-ppc/translate.c | 73 +++++++++++++++++++++++++------
> target-ppc/translate_init.c | 103 ++++++++++++++++++++++++++++++++------------
> 2 files changed, 136 insertions(+), 40 deletions(-)
>
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 6c5a4a6..733d68d 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -40,6 +40,7 @@
> /* Include definitions for instructions classes and implementations flags */
> //#define PPC_DEBUG_DISAS
> //#define DO_PPC_STATISTICS
> +//#define PPC_DUMP_CPU
>
> #ifdef PPC_DEBUG_DISAS
> # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
> @@ -367,12 +368,15 @@ GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
> #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
> GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
>
> +#define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \
> +GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
> +
> typedef struct opcode_t {
> - unsigned char opc1, opc2, opc3;
> + unsigned char opc1, opc2, opc3, opc4;
> #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
> - unsigned char pad[5];
> + unsigned char pad[4];
> #else
> - unsigned char pad[1];
> + unsigned char pad[4]; /* 4-byte pad to maintain pad in opcode table */
IIUC the point here is to align entries to the wordsize. If the
worsize is 32-bit you shouldn't need any extra padding here.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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next prev parent reply other threads:[~2016-07-22 5:07 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-07-18 17:05 [Qemu-devel] [RFC v1 00/13] POWER9 TCG enablements - part1 Nikunj A Dadhania
2016-07-18 17:05 ` [Qemu-devel] [RFC v1 01/13] target-ppc: Introduce Power9 family Nikunj A Dadhania
2016-07-18 17:05 ` [Qemu-devel] [RFC v1 02/13] target-ppc: Introduce POWER ISA 3.0 flag Nikunj A Dadhania
2016-07-18 17:05 ` [Qemu-devel] [RFC v1 03/13] target-ppc: adding addpcis instruction Nikunj A Dadhania
2016-07-21 7:53 ` Nikunj A Dadhania
2016-07-18 17:05 ` [Qemu-devel] [RFC v1 04/13] target-ppc: add cmprb instruction Nikunj A Dadhania
2016-07-18 17:05 ` [Qemu-devel] [RFC v1 05/13] target-ppc: add modulo word operations Nikunj A Dadhania
2016-07-22 4:51 ` David Gibson
2016-07-22 5:29 ` Nikunj A Dadhania
2016-07-22 6:09 ` David Gibson
2016-07-22 6:54 ` Nikunj A Dadhania
2016-07-22 7:12 ` David Gibson
2016-07-22 8:00 ` Nikunj A Dadhania
2016-07-18 17:05 ` [Qemu-devel] [RFC v1 06/13] target-ppc: add modulo dword operations Nikunj A Dadhania
2016-07-18 17:05 ` [Qemu-devel] [RFC v1 07/13] target-ppc: add cnttzd[.] instruction Nikunj A Dadhania
2016-07-21 6:28 ` Richard Henderson
2016-07-21 7:54 ` Nikunj A Dadhania
2016-07-18 17:05 ` [Qemu-devel] [RFC v1 08/13] target-ppc: add cnttzw[.] instruction Nikunj A Dadhania
2016-07-21 6:29 ` Richard Henderson
2016-07-21 7:54 ` Nikunj A Dadhania
2016-07-18 17:05 ` [Qemu-devel] [RFC v1 09/13] target-ppc: add cmpeqb instruction Nikunj A Dadhania
2016-07-18 17:12 ` Nikunj A Dadhania
2016-07-21 6:41 ` Richard Henderson
2016-07-21 8:02 ` Nikunj A Dadhania
2016-07-22 19:28 ` Nikunj A Dadhania
2016-07-23 1:17 ` Richard Henderson
2016-07-23 6:08 ` Nikunj A Dadhania
2016-07-23 16:01 ` Richard Henderson
2016-07-22 4:57 ` David Gibson
2016-07-18 17:05 ` [Qemu-devel] [RFC v1 10/13] target-ppc: add setb instruction Nikunj A Dadhania
2016-07-21 6:49 ` Richard Henderson
2016-07-22 4:59 ` David Gibson
2016-07-22 5:30 ` Nikunj A Dadhania
2016-07-18 17:05 ` [Qemu-devel] [RFC v1 11/13] target-ppc: add maddld instruction Nikunj A Dadhania
2016-07-21 6:54 ` Richard Henderson
2016-07-21 6:59 ` Richard Henderson
2016-07-18 17:05 ` [Qemu-devel] [RFC v1 12/13] target-ppc: add maddhd and maddhdu instruction Nikunj A Dadhania
2016-07-21 7:02 ` Richard Henderson
2016-07-18 17:05 ` [Qemu-devel] [RFC v1 13/13] target-ppc: introduce opc4 for Expanded Opcode Nikunj A Dadhania
2016-07-22 5:07 ` David Gibson [this message]
2016-07-22 5:35 ` Nikunj A Dadhania
2016-07-22 6:08 ` David Gibson
2016-07-22 6:58 ` Nikunj A Dadhania
2016-07-22 9:49 ` Bharata B Rao
2016-07-22 10:00 ` Nikunj A Dadhania
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