From: will.deacon@arm.com (Will Deacon)
To: linux-arm-kernel@lists.infradead.org
Subject: Problem with atomic accesses in pstore on some ARM CPUs
Date: Tue, 16 Aug 2016 14:21:03 +0100 [thread overview]
Message-ID: <20160816132103.GD27088@arm.com> (raw)
In-Reply-To: <CABXOdTfg2T2tZrQOd2S5SjeySAMbfQX0weFuvRXBr2o8Of9nVQ@mail.gmail.com>
On Tue, Aug 16, 2016 at 06:14:53AM -0700, Guenter Roeck wrote:
> On Tue, Aug 16, 2016 at 3:32 AM, Robin Murphy <robin.murphy@arm.com> wrote:
> > On 16/08/16 00:19, Guenter Roeck wrote:
> >> we are having a problem with atomic accesses in pstore on some ARM
> >> CPUs (specifically rk3288 and rk3399). With those chips, atomic
> >> accesses fail with both pgprot_noncached and pgprot_writecombine
> >> memory. Atomic accesses do work when selecting PAGE_KERNEL protection.
> >
> > What's the pstore backed by? I'm guessing it's not normal DRAM.
> >
>
> it is normal DRAM.
In which case, why does it need to be mapped with weird attributes?
Is there an alias in the linear map you can use?
Will
WARNING: multiple messages have this Message-ID (diff)
From: Will Deacon <will.deacon@arm.com>
To: Guenter Roeck <groeck@google.com>
Cc: Robin Murphy <robin.murphy@arm.com>,
Kees Cook <keescook@chromium.org>,
Jeffy Chen <jeffy.chen@rock-chips.com>,
Colin Cross <ccross@android.com>, Tony Luck <tony.luck@intel.com>,
Douglas Anderson <dianders@chromium.org>,
linux-kernel <linux-kernel@vger.kernel.org>,
linux-arm-kernel@lists.infradead.org
Subject: Re: Problem with atomic accesses in pstore on some ARM CPUs
Date: Tue, 16 Aug 2016 14:21:03 +0100 [thread overview]
Message-ID: <20160816132103.GD27088@arm.com> (raw)
In-Reply-To: <CABXOdTfg2T2tZrQOd2S5SjeySAMbfQX0weFuvRXBr2o8Of9nVQ@mail.gmail.com>
On Tue, Aug 16, 2016 at 06:14:53AM -0700, Guenter Roeck wrote:
> On Tue, Aug 16, 2016 at 3:32 AM, Robin Murphy <robin.murphy@arm.com> wrote:
> > On 16/08/16 00:19, Guenter Roeck wrote:
> >> we are having a problem with atomic accesses in pstore on some ARM
> >> CPUs (specifically rk3288 and rk3399). With those chips, atomic
> >> accesses fail with both pgprot_noncached and pgprot_writecombine
> >> memory. Atomic accesses do work when selecting PAGE_KERNEL protection.
> >
> > What's the pstore backed by? I'm guessing it's not normal DRAM.
> >
>
> it is normal DRAM.
In which case, why does it need to be mapped with weird attributes?
Is there an alias in the linear map you can use?
Will
next prev parent reply other threads:[~2016-08-16 13:21 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-15 23:19 Problem with atomic accesses in pstore on some ARM CPUs Guenter Roeck
2016-08-15 23:19 ` Guenter Roeck
2016-08-16 10:32 ` Robin Murphy
2016-08-16 10:32 ` Robin Murphy
2016-08-16 10:45 ` Will Deacon
2016-08-16 10:45 ` Will Deacon
2016-08-16 13:21 ` Guenter Roeck
2016-08-16 13:21 ` Guenter Roeck
2016-08-16 13:14 ` Guenter Roeck
2016-08-16 13:14 ` Guenter Roeck
2016-08-16 13:21 ` Will Deacon [this message]
2016-08-16 13:21 ` Will Deacon
2016-08-16 15:02 ` Guenter Roeck
2016-08-16 15:02 ` Guenter Roeck
2016-08-15 22:15 ` Mark Rutland
2016-08-15 22:15 ` Mark Rutland
2016-08-16 17:35 ` Colin Cross
2016-08-16 17:35 ` Colin Cross
2016-08-16 20:26 ` Guenter Roeck
2016-08-16 20:26 ` Guenter Roeck
2016-08-16 20:50 ` Kees Cook
2016-08-16 20:50 ` Kees Cook
2016-08-17 0:26 ` Guenter Roeck
2016-08-17 0:26 ` Guenter Roeck
2016-08-18 14:02 ` Tony Lindgren
2016-08-19 9:35 ` Russell King - ARM Linux
2016-08-19 9:35 ` Russell King - ARM Linux
2016-08-19 12:47 ` Guenter Roeck
2016-08-19 12:47 ` Guenter Roeck
2016-08-22 21:03 ` Arnd Bergmann
2016-08-22 21:03 ` Arnd Bergmann
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