From: will.deacon@arm.com (Will Deacon)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 6/8] arm64: Introduce raw_{d,i}cache_line_size
Date: Mon, 22 Aug 2016 11:00:07 +0100 [thread overview]
Message-ID: <20160822100007.GB14680@arm.com> (raw)
In-Reply-To: <1471525832-21209-7-git-send-email-suzuki.poulose@arm.com>
On Thu, Aug 18, 2016 at 02:10:30PM +0100, Suzuki K Poulose wrote:
> On systems with mismatched i/d cache min line sizes, we need to use
> the smallest size possible across all CPUs. This will be done by fetching
> the system wide safe value from CPU feature infrastructure.
> However the some special users(e.g kexec, hibernate) would need the line
> size on the CPU (rather than the system wide), when the system wide
> feature may not be accessible. Provide another helper which will fetch
> cache line size on the current CPU.
Why are these users "special"? Using a smaller line size shouldn't affect
correctness, and I don't see kexec and hibernate as being performance
critical in their cache maintenance.
Will
WARNING: multiple messages have this Message-ID (diff)
From: Will Deacon <will.deacon@arm.com>
To: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, catalin.marinas@arm.com,
mark.rutland@arm.com, andre.przywara@arm.com,
James Morse <james.morse@arm.com>,
Geoff Levand <geoff@infradead.org>
Subject: Re: [PATCH 6/8] arm64: Introduce raw_{d,i}cache_line_size
Date: Mon, 22 Aug 2016 11:00:07 +0100 [thread overview]
Message-ID: <20160822100007.GB14680@arm.com> (raw)
In-Reply-To: <1471525832-21209-7-git-send-email-suzuki.poulose@arm.com>
On Thu, Aug 18, 2016 at 02:10:30PM +0100, Suzuki K Poulose wrote:
> On systems with mismatched i/d cache min line sizes, we need to use
> the smallest size possible across all CPUs. This will be done by fetching
> the system wide safe value from CPU feature infrastructure.
> However the some special users(e.g kexec, hibernate) would need the line
> size on the CPU (rather than the system wide), when the system wide
> feature may not be accessible. Provide another helper which will fetch
> cache line size on the current CPU.
Why are these users "special"? Using a smaller line size shouldn't affect
correctness, and I don't see kexec and hibernate as being performance
critical in their cache maintenance.
Will
next prev parent reply other threads:[~2016-08-22 10:00 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-18 13:10 [RESEND] [PATCH 0/8] arm64: Work around for mismatched cache line size Suzuki K Poulose
2016-08-18 13:10 ` Suzuki K Poulose
2016-08-18 13:10 ` [PATCH 1/8] arm64: Set the safe value for L1 icache policy Suzuki K Poulose
2016-08-18 13:10 ` Suzuki K Poulose
2016-08-18 13:10 ` [PATCH 2/8] arm64: Use consistent naming for errata handling Suzuki K Poulose
2016-08-18 13:10 ` Suzuki K Poulose
2016-08-18 13:10 ` [PATCH 3/8] arm64: Rearrange CPU errata workaround checks Suzuki K Poulose
2016-08-18 13:10 ` Suzuki K Poulose
2016-08-18 13:10 ` [PATCH 4/8] arm64: insn: Add helpers for adrp offsets Suzuki K Poulose
2016-08-18 13:10 ` Suzuki K Poulose
2016-08-18 14:47 ` Marc Zyngier
2016-08-18 14:47 ` Marc Zyngier
2016-08-18 14:52 ` Suzuki K Poulose
2016-08-18 14:52 ` Suzuki K Poulose
2016-08-18 13:10 ` [PATCH 5/8] arm64: alternative: Add support for patching adrp instructions Suzuki K Poulose
2016-08-18 13:10 ` Suzuki K Poulose
2016-08-22 11:19 ` Will Deacon
2016-08-22 11:19 ` Will Deacon
2016-08-23 9:39 ` Suzuki K Poulose
2016-08-23 9:39 ` Suzuki K Poulose
2016-08-22 11:45 ` Ard Biesheuvel
2016-08-22 11:45 ` Ard Biesheuvel
2016-08-23 9:16 ` Suzuki K Poulose
2016-08-23 9:16 ` Suzuki K Poulose
2016-08-23 11:32 ` Ard Biesheuvel
2016-08-23 11:32 ` Ard Biesheuvel
2016-08-18 13:10 ` [PATCH 6/8] arm64: Introduce raw_{d,i}cache_line_size Suzuki K Poulose
2016-08-18 13:10 ` Suzuki K Poulose
2016-08-18 17:57 ` Geoff Levand
2016-08-18 17:57 ` Geoff Levand
2016-08-22 10:00 ` Will Deacon [this message]
2016-08-22 10:00 ` Will Deacon
2016-08-23 10:07 ` Suzuki K Poulose
2016-08-23 10:07 ` Suzuki K Poulose
2016-08-18 13:10 ` [PATCH 7/8] arm64: Refactor sysinstr exception handling Suzuki K Poulose
2016-08-18 13:10 ` Suzuki K Poulose
2016-08-22 12:53 ` Will Deacon
2016-08-22 12:53 ` Will Deacon
2016-08-23 10:19 ` Suzuki K Poulose
2016-08-23 10:19 ` Suzuki K Poulose
2016-08-18 13:10 ` [PATCH 8/8] arm64: Work around systems with mismatched cache line sizes Suzuki K Poulose
2016-08-18 13:10 ` Suzuki K Poulose
2016-08-22 13:02 ` Will Deacon
2016-08-22 13:02 ` Will Deacon
2016-08-24 13:23 ` Suzuki K Poulose
2016-08-24 13:23 ` Suzuki K Poulose
-- strict thread matches above, loose matches on Subject: below --
2016-07-08 11:37 [PATCH 0/8] arm64: Work around for mismatched cache line size Suzuki K Poulose
2016-07-08 11:37 ` [PATCH 6/8] arm64: Introduce raw_{d,i}cache_line_size Suzuki K Poulose
2016-07-08 11:37 ` Suzuki K Poulose
2016-07-11 21:55 ` Geoff Levand
2016-07-11 21:55 ` Geoff Levand
2016-08-09 16:22 ` James Morse
2016-08-09 16:22 ` James Morse
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