diff for duplicates of <20160824175419.GD19826@codeaurora.org> diff --git a/a/1.txt b/N1/1.txt index 95a05f4..9555adc 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,5 +1,5 @@ On 08/24, Thierry Reding wrote: -> From: Vince Hsu <vinceh@nvidia.com> +> From: Vince Hsu <vinceh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> > > Tegra114 has a HW bug that the PLLD/PLLD2 lock bit cannot be asserted when > the DIS power domain is during up-powergating process but the clamp to this @@ -8,9 +8,9 @@ On 08/24, Thierry Reding wrote: > alarm, we don't use the lock for PLLD/PLLD2. Just wait 1ms and treat the > clocks as locked. > -> Signed-off-by: Vince Hsu <vinceh@nvidia.com> -> Tested-by: Jonathan Hunter <jonathanh@nvidia.com> -> Signed-off-by: Thierry Reding <treding@nvidia.com> +> Signed-off-by: Vince Hsu <vinceh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> +> Tested-by: Jonathan Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> +> Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> > --- Applied to clk-fixes diff --git a/a/content_digest b/N1/content_digest index 8c0b364..0021367 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,16 +1,17 @@ "ref\020160824135656.5025-1-thierry.reding@gmail.com\0" - "From\0Stephen Boyd <sboyd@codeaurora.org>\0" + "ref\020160824135656.5025-1-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org\0" + "From\0Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>\0" "Subject\0Re: [PATCH] clk: tegra: remove TEGRA_PLL_USE_LOCK for PLLD/PLLD2\0" "Date\0Wed, 24 Aug 2016 10:54:19 -0700\0" - "To\0Thierry Reding <thierry.reding@gmail.com>\0" - "Cc\0Michael Turquette <mturquette@baylibre.com>" - Jonathan Hunter <jonathanh@nvidia.com> - linux-clk@vger.kernel.org - " linux-tegra@vger.kernel.org\0" + "To\0Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\0" + "Cc\0Michael Turquette <mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>" + Jonathan Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> + linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + " linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\0" "\00:1\0" "b\0" "On 08/24, Thierry Reding wrote:\n" - "> From: Vince Hsu <vinceh@nvidia.com>\n" + "> From: Vince Hsu <vinceh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" "> \n" "> Tegra114 has a HW bug that the PLLD/PLLD2 lock bit cannot be asserted when\n" "> the DIS power domain is during up-powergating process but the clamp to this\n" @@ -19,9 +20,9 @@ "> alarm, we don't use the lock for PLLD/PLLD2. Just wait 1ms and treat the\n" "> clocks as locked.\n" "> \n" - "> Signed-off-by: Vince Hsu <vinceh@nvidia.com>\n" - "> Tested-by: Jonathan Hunter <jonathanh@nvidia.com>\n" - "> Signed-off-by: Thierry Reding <treding@nvidia.com>\n" + "> Signed-off-by: Vince Hsu <vinceh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" + "> Tested-by: Jonathan Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" + "> Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" "> ---\n" "\n" "Applied to clk-fixes\n" @@ -30,4 +31,4 @@ "Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,\n" a Linux Foundation Collaborative Project -350e6b9ffb96e376ddc2552f736bef1b4429ee66c6585fd663d19580230f5f8d +e76040bc156516a4af49f5ba3cbb945e7123a5b053349ee6375a0eb3219dfcf9
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