From: Stephen Boyd <sboyd@codeaurora.org>
To: Thierry Reding <thierry.reding@gmail.com>
Cc: Michael Turquette <mturquette@baylibre.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org
Subject: Re: [PATCH] clk: tegra: remove TEGRA_PLL_USE_LOCK for PLLD/PLLD2
Date: Wed, 24 Aug 2016 10:54:19 -0700 [thread overview]
Message-ID: <20160824175419.GD19826@codeaurora.org> (raw)
In-Reply-To: <20160824135656.5025-1-thierry.reding@gmail.com>
On 08/24, Thierry Reding wrote:
> From: Vince Hsu <vinceh@nvidia.com>
>
> Tegra114 has a HW bug that the PLLD/PLLD2 lock bit cannot be asserted when
> the DIS power domain is during up-powergating process but the clamp to this
> domain is not removed yet. That causes a timeout and aborts the power
> sequence, although the PLLD/PLLD2 has already locked. To remove the false
> alarm, we don't use the lock for PLLD/PLLD2. Just wait 1ms and treat the
> clocks as locked.
>
> Signed-off-by: Vince Hsu <vinceh@nvidia.com>
> Tested-by: Jonathan Hunter <jonathanh@nvidia.com>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
Applied to clk-fixes
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
WARNING: multiple messages have this Message-ID (diff)
From: Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
To: Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Michael Turquette
<mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>,
Jonathan Hunter
<jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH] clk: tegra: remove TEGRA_PLL_USE_LOCK for PLLD/PLLD2
Date: Wed, 24 Aug 2016 10:54:19 -0700 [thread overview]
Message-ID: <20160824175419.GD19826@codeaurora.org> (raw)
In-Reply-To: <20160824135656.5025-1-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On 08/24, Thierry Reding wrote:
> From: Vince Hsu <vinceh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>
> Tegra114 has a HW bug that the PLLD/PLLD2 lock bit cannot be asserted when
> the DIS power domain is during up-powergating process but the clamp to this
> domain is not removed yet. That causes a timeout and aborts the power
> sequence, although the PLLD/PLLD2 has already locked. To remove the false
> alarm, we don't use the lock for PLLD/PLLD2. Just wait 1ms and treat the
> clocks as locked.
>
> Signed-off-by: Vince Hsu <vinceh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> Tested-by: Jonathan Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
Applied to clk-fixes
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2016-08-24 17:54 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-24 13:56 [PATCH] clk: tegra: remove TEGRA_PLL_USE_LOCK for PLLD/PLLD2 Thierry Reding
2016-08-24 13:56 ` Thierry Reding
2016-08-24 17:54 ` Stephen Boyd [this message]
2016-08-24 17:54 ` Stephen Boyd
-- strict thread matches above, loose matches on Subject: below --
2015-08-21 15:33 Jon Hunter
2015-08-21 15:33 ` Jon Hunter
2015-08-21 15:33 ` Jon Hunter
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