From: will.deacon@arm.com (Will Deacon)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 8/9] arm64: Refactor sysinstr exception handling
Date: Wed, 7 Sep 2016 09:44:37 +0100 [thread overview]
Message-ID: <20160907084436.GD32499@arm.com> (raw)
In-Reply-To: <1473069509-2317-9-git-send-email-suzuki.poulose@arm.com>
On Mon, Sep 05, 2016 at 10:58:28AM +0100, Suzuki K Poulose wrote:
> Right now we trap some of the user space data cache operations
> based on a few Errata (ARM 819472, 826319, 827319 and 824069).
> We need to trap userspace access to CTR_EL0, if we detect mismatched
> cache line size. Since both these traps share the EC, refactor
> the handler a little bit to make it a bit more reader friendly.
>
> Cc: Andre Przywara <andre.przywara@arm.com>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Will Deacon <will.deacon@arm.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
> arch/arm64/include/asm/esr.h | 76 ++++++++++++++++++++++++++++++++++++++------
> arch/arm64/kernel/traps.c | 73 +++++++++++++++++++++++++++---------------
> 2 files changed, 114 insertions(+), 35 deletions(-)
This looks fine to me, but I'd really like to see Andre's ack on the
refactoring of the errata workarounds.
Andre, can you take a look please?
Will
WARNING: multiple messages have this Message-ID (diff)
From: Will Deacon <will.deacon@arm.com>
To: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, catalin.marinas@arm.com,
marc.zyngier@arm.com, mark.rutland@arm.com, james.morse@arm.com,
ard.biesheuvel@linaro.org, andre.przywara@arm.com
Subject: Re: [PATCH v3 8/9] arm64: Refactor sysinstr exception handling
Date: Wed, 7 Sep 2016 09:44:37 +0100 [thread overview]
Message-ID: <20160907084436.GD32499@arm.com> (raw)
In-Reply-To: <1473069509-2317-9-git-send-email-suzuki.poulose@arm.com>
On Mon, Sep 05, 2016 at 10:58:28AM +0100, Suzuki K Poulose wrote:
> Right now we trap some of the user space data cache operations
> based on a few Errata (ARM 819472, 826319, 827319 and 824069).
> We need to trap userspace access to CTR_EL0, if we detect mismatched
> cache line size. Since both these traps share the EC, refactor
> the handler a little bit to make it a bit more reader friendly.
>
> Cc: Andre Przywara <andre.przywara@arm.com>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Will Deacon <will.deacon@arm.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
> arch/arm64/include/asm/esr.h | 76 ++++++++++++++++++++++++++++++++++++++------
> arch/arm64/kernel/traps.c | 73 +++++++++++++++++++++++++++---------------
> 2 files changed, 114 insertions(+), 35 deletions(-)
This looks fine to me, but I'd really like to see Andre's ack on the
refactoring of the errata workarounds.
Andre, can you take a look please?
Will
next prev parent reply other threads:[~2016-09-07 8:44 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-05 9:58 [PATCH v3 0/9] arm64: Work around for mismatched cache line size Suzuki K Poulose
2016-09-05 9:58 ` Suzuki K Poulose
2016-09-05 9:58 ` [PATCH v3 1/9] arm64: Set the safe value for L1 icache policy Suzuki K Poulose
2016-09-05 9:58 ` Suzuki K Poulose
2016-09-05 9:58 ` [PATCH v3 2/9] arm64: Use consistent naming for errata handling Suzuki K Poulose
2016-09-05 9:58 ` Suzuki K Poulose
2016-09-07 10:36 ` Andre Przywara
2016-09-07 10:36 ` Andre Przywara
2016-09-05 9:58 ` [PATCH v3 3/9] arm64: Rearrange CPU errata workaround checks Suzuki K Poulose
2016-09-05 9:58 ` Suzuki K Poulose
2016-09-05 9:58 ` [PATCH v3 4/9] arm64: alternative: Disallow patching instructions using literals Suzuki K Poulose
2016-09-05 9:58 ` Suzuki K Poulose
2016-09-05 9:58 ` [PATCH v3 5/9] arm64: insn: Add helpers for adrp offsets Suzuki K Poulose
2016-09-05 9:58 ` Suzuki K Poulose
2016-09-05 9:58 ` [PATCH v3 6/9] arm64: alternative: Add support for patching adrp instructions Suzuki K Poulose
2016-09-05 9:58 ` Suzuki K Poulose
2016-09-05 9:58 ` [PATCH v3 7/9] arm64: Introduce raw_{d,i}cache_line_size Suzuki K Poulose
2016-09-05 9:58 ` Suzuki K Poulose
2016-09-05 9:58 ` [PATCH v3 8/9] arm64: Refactor sysinstr exception handling Suzuki K Poulose
2016-09-05 9:58 ` Suzuki K Poulose
2016-09-07 8:44 ` Will Deacon [this message]
2016-09-07 8:44 ` Will Deacon
2016-09-07 11:29 ` Andre Przywara
2016-09-07 11:29 ` Andre Przywara
2016-09-05 9:58 ` [PATCH v3 9/9] arm64: Work around systems with mismatched cache line sizes Suzuki K Poulose
2016-09-05 9:58 ` Suzuki K Poulose
2016-09-05 10:10 ` Ard Biesheuvel
2016-09-05 10:10 ` Ard Biesheuvel
2016-09-05 10:24 ` Suzuki K Poulose
2016-09-05 10:24 ` Suzuki K Poulose
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