From: Stephen Boyd <sboyd@codeaurora.org>
To: Chen-Yu Tsai <wens@csie.org>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>,
Michael Turquette <mturquette@baylibre.com>,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 1/3] clk: sunxi-ng: sun6i-a31: Set CLK_SET_RATE_PARENT for display output clocks
Date: Fri, 16 Sep 2016 16:04:07 -0700 [thread overview]
Message-ID: <20160916230407.GS7243@codeaurora.org> (raw)
In-Reply-To: <20160915065740.13664-2-wens@csie.org>
On 09/15, Chen-Yu Tsai wrote:
> The LCD controller and HDMI controller use the LCDx-CHy and HDMI clocks
> to generate their dot clocks. To be able to generate a full range of
> possible clock rates, the parent PLL clock rates should also be changed.
>
> Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks")
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
WARNING: multiple messages have this Message-ID (diff)
From: sboyd@codeaurora.org (Stephen Boyd)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/3] clk: sunxi-ng: sun6i-a31: Set CLK_SET_RATE_PARENT for display output clocks
Date: Fri, 16 Sep 2016 16:04:07 -0700 [thread overview]
Message-ID: <20160916230407.GS7243@codeaurora.org> (raw)
In-Reply-To: <20160915065740.13664-2-wens@csie.org>
On 09/15, Chen-Yu Tsai wrote:
> The LCD controller and HDMI controller use the LCDx-CHy and HDMI clocks
> to generate their dot clocks. To be able to generate a full range of
> possible clock rates, the parent PLL clock rates should also be changed.
>
> Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks")
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2016-09-16 23:04 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-15 6:57 [PATCH 0/3] clk: sunxi-ng: sun6i-a31: Register offset and clk flag fixes Chen-Yu Tsai
2016-09-15 6:57 ` Chen-Yu Tsai
2016-09-15 6:57 ` [PATCH 1/3] clk: sunxi-ng: sun6i-a31: Set CLK_SET_RATE_PARENT for display output clocks Chen-Yu Tsai
2016-09-15 6:57 ` Chen-Yu Tsai
2016-09-16 23:04 ` Stephen Boyd [this message]
2016-09-16 23:04 ` Stephen Boyd
2016-09-15 6:57 ` [PATCH 2/3] clk: sunxi-ng: sun6i-a31: set CLK_SET_RATE_UNGATE for all PLLs Chen-Yu Tsai
2016-09-15 6:57 ` Chen-Yu Tsai
2016-09-15 6:57 ` [PATCH 3/3] clk: sunxi-ng: sun6i-a31: Fix register offset for mipi-csi clk Chen-Yu Tsai
2016-09-15 6:57 ` Chen-Yu Tsai
2016-09-16 23:04 ` Stephen Boyd
2016-09-16 23:04 ` Stephen Boyd
2016-09-15 8:34 ` [PATCH 0/3] clk: sunxi-ng: sun6i-a31: Register offset and clk flag fixes Maxime Ripard
2016-09-15 8:34 ` Maxime Ripard
2016-09-15 23:11 ` Stephen Boyd
2016-09-15 23:11 ` Stephen Boyd
2016-09-18 20:30 ` Maxime Ripard
2016-09-18 20:30 ` Maxime Ripard
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