* [Qemu-devel] [PATCH v1 1/1] target-arm: A64: Fix decoding of iss_sf in disas_ld_lit
@ 2016-09-30 10:19 ` Edgar E. Iglesias
0 siblings, 0 replies; 16+ messages in thread
From: Edgar E. Iglesias @ 2016-09-30 10:19 UTC (permalink / raw)
To: qemu-devel, peter.maydell; +Cc: edgar.iglesias, qemu-arm
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Fix the decoding of iss_sf in disas_ld_lit.
The SF (Sixty-Four) field in the ISS (Instruction Specific Syndrome)
is a bit that specifies the width of the register that the
instruction loads to.
If cleared it specifies 32 bits.
If set it specifies 64 bits.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
target-arm/translate-a64.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index ddf52f5..eae25c3 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -2025,7 +2025,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
do_fp_ld(s, rt, tcg_addr, size);
} else {
/* Only unsigned 32bit loads target 32bit registers. */
- bool iss_sf = opc == 0 ? 32 : 64;
+ bool iss_sf = opc == 0 ? false : true;
do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, false,
true, rt, iss_sf, false);
--
2.7.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* [Qemu-devel] [PATCH v1 1/1] target-arm: A64: Fix decoding of iss_sf in disas_ld_lit
@ 2016-09-30 10:19 ` Edgar E. Iglesias
0 siblings, 0 replies; 16+ messages in thread
From: Edgar E. Iglesias @ 2016-09-30 10:19 UTC (permalink / raw)
To: qemu-devel, peter.maydell; +Cc: qemu-arm, edgar.iglesias
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Fix the decoding of iss_sf in disas_ld_lit.
The SF (Sixty-Four) field in the ISS (Instruction Specific Syndrome)
is a bit that specifies the width of the register that the
instruction loads to.
If cleared it specifies 32 bits.
If set it specifies 64 bits.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
target-arm/translate-a64.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index ddf52f5..eae25c3 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -2025,7 +2025,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
do_fp_ld(s, rt, tcg_addr, size);
} else {
/* Only unsigned 32bit loads target 32bit registers. */
- bool iss_sf = opc == 0 ? 32 : 64;
+ bool iss_sf = opc == 0 ? false : true;
do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, false,
true, rt, iss_sf, false);
--
2.7.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [Qemu-arm] [Qemu-devel] [PATCH v1 1/1] target-arm: A64: Fix decoding of iss_sf in disas_ld_lit
2016-09-30 10:19 ` Edgar E. Iglesias
@ 2016-09-30 10:42 ` Thomas Huth
-1 siblings, 0 replies; 16+ messages in thread
From: Thomas Huth @ 2016-09-30 10:42 UTC (permalink / raw)
To: Edgar E. Iglesias, qemu-devel, peter.maydell; +Cc: edgar.iglesias, qemu-arm
On 30.09.2016 12:19, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Fix the decoding of iss_sf in disas_ld_lit.
> The SF (Sixty-Four) field in the ISS (Instruction Specific Syndrome)
> is a bit that specifies the width of the register that the
> instruction loads to.
>
> If cleared it specifies 32 bits.
> If set it specifies 64 bits.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> ---
> target-arm/translate-a64.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
> index ddf52f5..eae25c3 100644
> --- a/target-arm/translate-a64.c
> +++ b/target-arm/translate-a64.c
> @@ -2025,7 +2025,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
> do_fp_ld(s, rt, tcg_addr, size);
> } else {
> /* Only unsigned 32bit loads target 32bit registers. */
> - bool iss_sf = opc == 0 ? 32 : 64;
> + bool iss_sf = opc == 0 ? false : true;
You could simplify that to:
bool iss_sf = !(opc == 0);
Thomas
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [Qemu-devel] [PATCH v1 1/1] target-arm: A64: Fix decoding of iss_sf in disas_ld_lit
@ 2016-09-30 10:42 ` Thomas Huth
0 siblings, 0 replies; 16+ messages in thread
From: Thomas Huth @ 2016-09-30 10:42 UTC (permalink / raw)
To: Edgar E. Iglesias, qemu-devel, peter.maydell; +Cc: edgar.iglesias, qemu-arm
On 30.09.2016 12:19, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Fix the decoding of iss_sf in disas_ld_lit.
> The SF (Sixty-Four) field in the ISS (Instruction Specific Syndrome)
> is a bit that specifies the width of the register that the
> instruction loads to.
>
> If cleared it specifies 32 bits.
> If set it specifies 64 bits.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> ---
> target-arm/translate-a64.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
> index ddf52f5..eae25c3 100644
> --- a/target-arm/translate-a64.c
> +++ b/target-arm/translate-a64.c
> @@ -2025,7 +2025,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
> do_fp_ld(s, rt, tcg_addr, size);
> } else {
> /* Only unsigned 32bit loads target 32bit registers. */
> - bool iss_sf = opc == 0 ? 32 : 64;
> + bool iss_sf = opc == 0 ? false : true;
You could simplify that to:
bool iss_sf = !(opc == 0);
Thomas
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [Qemu-devel] [PATCH v1 1/1] target-arm: A64: Fix decoding of iss_sf in disas_ld_lit
2016-09-30 10:42 ` Thomas Huth
@ 2016-09-30 10:49 ` Edgar E. Iglesias
-1 siblings, 0 replies; 16+ messages in thread
From: Edgar E. Iglesias @ 2016-09-30 10:49 UTC (permalink / raw)
To: Thomas Huth; +Cc: edgar.iglesias, peter.maydell, qemu-arm, qemu-devel
On Fri, Sep 30, 2016 at 12:42:27PM +0200, Thomas Huth wrote:
> On 30.09.2016 12:19, Edgar E. Iglesias wrote:
> > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> >
> > Fix the decoding of iss_sf in disas_ld_lit.
> > The SF (Sixty-Four) field in the ISS (Instruction Specific Syndrome)
> > is a bit that specifies the width of the register that the
> > instruction loads to.
> >
> > If cleared it specifies 32 bits.
> > If set it specifies 64 bits.
> >
> > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> > ---
> > target-arm/translate-a64.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
> > index ddf52f5..eae25c3 100644
> > --- a/target-arm/translate-a64.c
> > +++ b/target-arm/translate-a64.c
> > @@ -2025,7 +2025,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
> > do_fp_ld(s, rt, tcg_addr, size);
> > } else {
> > /* Only unsigned 32bit loads target 32bit registers. */
> > - bool iss_sf = opc == 0 ? 32 : 64;
> > + bool iss_sf = opc == 0 ? false : true;
>
> You could simplify that to:
>
> bool iss_sf = !(opc == 0);
I don't really see how that is simpler/clearer.
I considered:
bool iss_sf = opc != 0;
but felt the expanded one was clearer in particular as a patch for review.
In any case, I have no strong opinion on the syntax.
Cheers,
Edgar
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [Qemu-devel] [PATCH v1 1/1] target-arm: A64: Fix decoding of iss_sf in disas_ld_lit
@ 2016-09-30 10:49 ` Edgar E. Iglesias
0 siblings, 0 replies; 16+ messages in thread
From: Edgar E. Iglesias @ 2016-09-30 10:49 UTC (permalink / raw)
To: Thomas Huth; +Cc: qemu-devel, peter.maydell, edgar.iglesias, qemu-arm
On Fri, Sep 30, 2016 at 12:42:27PM +0200, Thomas Huth wrote:
> On 30.09.2016 12:19, Edgar E. Iglesias wrote:
> > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> >
> > Fix the decoding of iss_sf in disas_ld_lit.
> > The SF (Sixty-Four) field in the ISS (Instruction Specific Syndrome)
> > is a bit that specifies the width of the register that the
> > instruction loads to.
> >
> > If cleared it specifies 32 bits.
> > If set it specifies 64 bits.
> >
> > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> > ---
> > target-arm/translate-a64.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
> > index ddf52f5..eae25c3 100644
> > --- a/target-arm/translate-a64.c
> > +++ b/target-arm/translate-a64.c
> > @@ -2025,7 +2025,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
> > do_fp_ld(s, rt, tcg_addr, size);
> > } else {
> > /* Only unsigned 32bit loads target 32bit registers. */
> > - bool iss_sf = opc == 0 ? 32 : 64;
> > + bool iss_sf = opc == 0 ? false : true;
>
> You could simplify that to:
>
> bool iss_sf = !(opc == 0);
I don't really see how that is simpler/clearer.
I considered:
bool iss_sf = opc != 0;
but felt the expanded one was clearer in particular as a patch for review.
In any case, I have no strong opinion on the syntax.
Cheers,
Edgar
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [Qemu-devel] [PATCH v1 1/1] target-arm: A64: Fix decoding of iss_sf in disas_ld_lit
2016-09-30 10:49 ` Edgar E. Iglesias
@ 2016-09-30 17:34 ` Peter Maydell
-1 siblings, 0 replies; 16+ messages in thread
From: Peter Maydell @ 2016-09-30 17:34 UTC (permalink / raw)
To: Edgar E. Iglesias; +Cc: Edgar Iglesias, Thomas Huth, qemu-arm, QEMU Developers
On 30 September 2016 at 03:49, Edgar E. Iglesias
<edgar.iglesias@gmail.com> wrote:
> On Fri, Sep 30, 2016 at 12:42:27PM +0200, Thomas Huth wrote:
>> On 30.09.2016 12:19, Edgar E. Iglesias wrote:
>> > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>> >
>> > Fix the decoding of iss_sf in disas_ld_lit.
>> > The SF (Sixty-Four) field in the ISS (Instruction Specific Syndrome)
>> > is a bit that specifies the width of the register that the
>> > instruction loads to.
>> >
>> > If cleared it specifies 32 bits.
>> > If set it specifies 64 bits.
>> >
>> > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
>> > ---
>> > target-arm/translate-a64.c | 2 +-
>> > 1 file changed, 1 insertion(+), 1 deletion(-)
>> >
>> > diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
>> > index ddf52f5..eae25c3 100644
>> > --- a/target-arm/translate-a64.c
>> > +++ b/target-arm/translate-a64.c
>> > @@ -2025,7 +2025,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
>> > do_fp_ld(s, rt, tcg_addr, size);
>> > } else {
>> > /* Only unsigned 32bit loads target 32bit registers. */
>> > - bool iss_sf = opc == 0 ? 32 : 64;
>> > + bool iss_sf = opc == 0 ? false : true;
>>
>> You could simplify that to:
>>
>> bool iss_sf = !(opc == 0);
>
> I don't really see how that is simpler/clearer.
>
> I considered:
> bool iss_sf = opc != 0;
>
> but felt the expanded one was clearer in particular as a patch for review.
I would probably personally have written it without the ?:, but
I don't think it's significant enough to bother respinning.
thanks
-- PMM
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [Qemu-devel] [PATCH v1 1/1] target-arm: A64: Fix decoding of iss_sf in disas_ld_lit
@ 2016-09-30 17:34 ` Peter Maydell
0 siblings, 0 replies; 16+ messages in thread
From: Peter Maydell @ 2016-09-30 17:34 UTC (permalink / raw)
To: Edgar E. Iglesias; +Cc: Thomas Huth, QEMU Developers, Edgar Iglesias, qemu-arm
On 30 September 2016 at 03:49, Edgar E. Iglesias
<edgar.iglesias@gmail.com> wrote:
> On Fri, Sep 30, 2016 at 12:42:27PM +0200, Thomas Huth wrote:
>> On 30.09.2016 12:19, Edgar E. Iglesias wrote:
>> > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>> >
>> > Fix the decoding of iss_sf in disas_ld_lit.
>> > The SF (Sixty-Four) field in the ISS (Instruction Specific Syndrome)
>> > is a bit that specifies the width of the register that the
>> > instruction loads to.
>> >
>> > If cleared it specifies 32 bits.
>> > If set it specifies 64 bits.
>> >
>> > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
>> > ---
>> > target-arm/translate-a64.c | 2 +-
>> > 1 file changed, 1 insertion(+), 1 deletion(-)
>> >
>> > diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
>> > index ddf52f5..eae25c3 100644
>> > --- a/target-arm/translate-a64.c
>> > +++ b/target-arm/translate-a64.c
>> > @@ -2025,7 +2025,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
>> > do_fp_ld(s, rt, tcg_addr, size);
>> > } else {
>> > /* Only unsigned 32bit loads target 32bit registers. */
>> > - bool iss_sf = opc == 0 ? 32 : 64;
>> > + bool iss_sf = opc == 0 ? false : true;
>>
>> You could simplify that to:
>>
>> bool iss_sf = !(opc == 0);
>
> I don't really see how that is simpler/clearer.
>
> I considered:
> bool iss_sf = opc != 0;
>
> but felt the expanded one was clearer in particular as a patch for review.
I would probably personally have written it without the ?:, but
I don't think it's significant enough to bother respinning.
thanks
-- PMM
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [Qemu-arm] [Qemu-devel] [PATCH v1 1/1] target-arm: A64: Fix decoding of iss_sf in disas_ld_lit
2016-09-30 17:34 ` Peter Maydell
@ 2016-09-30 18:36 ` Eric Blake
-1 siblings, 0 replies; 16+ messages in thread
From: Eric Blake @ 2016-09-30 18:36 UTC (permalink / raw)
To: Peter Maydell, Edgar E. Iglesias
Cc: Edgar Iglesias, Thomas Huth, qemu-arm, QEMU Developers
[-- Attachment #1.1: Type: text/plain, Size: 476 bytes --]
On 09/30/2016 12:34 PM, Peter Maydell wrote:
>>>> + bool iss_sf = opc == 0 ? false : true;
Feels like a double negative.
>>>
>>> You could simplify that to:
>>>
>>> bool iss_sf = !(opc == 0);
>>
>> I don't really see how that is simpler/clearer.
>>
>> I considered:
>> bool iss_sf = opc != 0;
Or even shorter:
bool iss_sf = !opc;
--
Eric Blake eblake redhat com +1-919-301-3266
Libvirt virtualization library http://libvirt.org
[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 604 bytes --]
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Qemu-arm] [Qemu-devel] [PATCH v1 1/1] target-arm: A64: Fix decoding of iss_sf in disas_ld_lit
2016-09-30 17:34 ` Peter Maydell
@ 2016-09-30 21:42 ` Edgar Iglesias
-1 siblings, 0 replies; 16+ messages in thread
From: Edgar Iglesias @ 2016-09-30 21:42 UTC (permalink / raw)
To: Peter Maydell, Edgar E. Iglesias; +Cc: Thomas Huth, qemu-arm, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 2432 bytes --]
Peter, feel free to change the syntax to whatever you feel is best.
Cheers,
Edgar
---
Sent from my phone
-------- Original Message --------
Subject: Re: [Qemu-devel] [PATCH v1 1/1] target-arm: A64: Fix decoding of iss_sf in disas_ld_lit
From: Peter Maydell <peter.maydell@linaro.org>
Date: 30 Sep 2016, 19:34
To: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
On 30 September 2016 at 03:49, Edgar E. Iglesias
<edgar.iglesias@gmail.com> wrote:
> On Fri, Sep 30, 2016 at 12:42:27PM +0200, Thomas Huth wrote:
>> On 30.09.2016 12:19, Edgar E. Iglesias wrote:
>> > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>> >
>> > Fix the decoding of iss_sf in disas_ld_lit.
>> > The SF (Sixty-Four) field in the ISS (Instruction Specific Syndrome)
>> > is a bit that specifies the width of the register that the
>> > instruction loads to.
>> >
>> > If cleared it specifies 32 bits.
>> > If set it specifies 64 bits.
>> >
>> > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
>> > ---
>> > target-arm/translate-a64.c | 2 +-
>> > 1 file changed, 1 insertion(+), 1 deletion(-)
>> >
>> > diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
>> > index ddf52f5..eae25c3 100644
>> > --- a/target-arm/translate-a64.c
>> > +++ b/target-arm/translate-a64.c
>> > @@ -2025,7 +2025,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
>> > do_fp_ld(s, rt, tcg_addr, size);
>> > } else {
>> > /* Only unsigned 32bit loads target 32bit registers. */
>> > - bool iss_sf = opc == 0 ? 32 : 64;
>> > + bool iss_sf = opc == 0 ? false : true;
>>
>> You could simplify that to:
>>
>> bool iss_sf = !(opc == 0);
>
> I don't really see how that is simpler/clearer.
>
> I considered:
> bool iss_sf = opc != 0;
>
> but felt the expanded one was clearer in particular as a patch for review.
I would probably personally have written it without the ?:, but
I don't think it's significant enough to bother respinning.
thanks
-- PMM
This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.
[-- Attachment #2: Type: text/html, Size: 3809 bytes --]
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [Qemu-devel] [PATCH v1 1/1] target-arm: A64: Fix decoding of iss_sf in disas_ld_lit
@ 2016-09-30 21:42 ` Edgar Iglesias
0 siblings, 0 replies; 16+ messages in thread
From: Edgar Iglesias @ 2016-09-30 21:42 UTC (permalink / raw)
To: Peter Maydell, Edgar E. Iglesias; +Cc: Thomas Huth, qemu-devel, qemu-arm
Peter, feel free to change the syntax to whatever you feel is best.
Cheers,
Edgar
---
Sent from my phone
-------- Original Message --------
Subject: Re: [Qemu-devel] [PATCH v1 1/1] target-arm: A64: Fix decoding of iss_sf in disas_ld_lit
From: Peter Maydell <peter.maydell@linaro.org>
Date: 30 Sep 2016, 19:34
To: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
On 30 September 2016 at 03:49, Edgar E. Iglesias
<edgar.iglesias@gmail.com> wrote:
> On Fri, Sep 30, 2016 at 12:42:27PM +0200, Thomas Huth wrote:
>> On 30.09.2016 12:19, Edgar E. Iglesias wrote:
>> > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>> >
>> > Fix the decoding of iss_sf in disas_ld_lit.
>> > The SF (Sixty-Four) field in the ISS (Instruction Specific Syndrome)
>> > is a bit that specifies the width of the register that the
>> > instruction loads to.
>> >
>> > If cleared it specifies 32 bits.
>> > If set it specifies 64 bits.
>> >
>> > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
>> > ---
>> > target-arm/translate-a64.c | 2 +-
>> > 1 file changed, 1 insertion(+), 1 deletion(-)
>> >
>> > diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
>> > index ddf52f5..eae25c3 100644
>> > --- a/target-arm/translate-a64.c
>> > +++ b/target-arm/translate-a64.c
>> > @@ -2025,7 +2025,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
>> > do_fp_ld(s, rt, tcg_addr, size);
>> > } else {
>> > /* Only unsigned 32bit loads target 32bit registers. */
>> > - bool iss_sf = opc == 0 ? 32 : 64;
>> > + bool iss_sf = opc == 0 ? false : true;
>>
>> You could simplify that to:
>>
>> bool iss_sf = !(opc == 0);
>
> I don't really see how that is simpler/clearer.
>
> I considered:
> bool iss_sf = opc != 0;
>
> but felt the expanded one was clearer in particular as a patch for review.
I would probably personally have written it without the ?:, but
I don't think it's significant enough to bother respinning.
thanks
-- PMM
This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [Qemu-arm] [Qemu-devel] [PATCH v1 1/1] target-arm: A64: Fix decoding of iss_sf in disas_ld_lit
2016-09-30 21:42 ` Edgar Iglesias
@ 2016-09-30 23:19 ` Peter Maydell
-1 siblings, 0 replies; 16+ messages in thread
From: Peter Maydell @ 2016-09-30 23:19 UTC (permalink / raw)
To: Edgar Iglesias; +Cc: Thomas Huth, qemu-arm, qemu-devel
On 30 September 2016 at 14:42, Edgar Iglesias <edgar.iglesias@xilinx.com> wrote:
> Peter, feel free to change the syntax to whatever you feel is best.
Applied to target-arm.next, thanks. I picked "iss_sf = opc != 0;"
-- PMM
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [PATCH v1 1/1] target-arm: A64: Fix decoding of iss_sf in disas_ld_lit
@ 2016-09-30 23:19 ` Peter Maydell
0 siblings, 0 replies; 16+ messages in thread
From: Peter Maydell @ 2016-09-30 23:19 UTC (permalink / raw)
To: Edgar Iglesias; +Cc: Edgar E. Iglesias, Thomas Huth, qemu-devel, qemu-arm
On 30 September 2016 at 14:42, Edgar Iglesias <edgar.iglesias@xilinx.com> wrote:
> Peter, feel free to change the syntax to whatever you feel is best.
Applied to target-arm.next, thanks. I picked "iss_sf = opc != 0;"
-- PMM
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Qemu-arm] [Qemu-devel] [PATCH v1 1/1] target-arm: A64: Fix decoding of iss_sf in disas_ld_lit
2016-09-30 23:19 ` Peter Maydell
@ 2016-10-01 1:15 ` Edgar Iglesias
-1 siblings, 0 replies; 16+ messages in thread
From: Edgar Iglesias @ 2016-10-01 1:15 UTC (permalink / raw)
To: Peter Maydell; +Cc: Thomas Huth, qemu-arm, qemu-devel
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Thanks :-)
Edgar
---
Sent from my phone
-------- Original Message --------
Subject: Re: [Qemu-devel] [PATCH v1 1/1] target-arm: A64: Fix decoding of iss_sf in disas_ld_lit
From: Peter Maydell <peter.maydell@linaro.org>
Date: 1 Oct 2016, 01:20
To: Edgar Iglesias <edgari@xilinx.com>
On 30 September 2016 at 14:42, Edgar Iglesias <edgar.iglesias@xilinx.com> wrote:
> Peter, feel free to change the syntax to whatever you feel is best.
Applied to target-arm.next, thanks. I picked "iss_sf = opc != 0;"
-- PMM
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^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [PATCH v1 1/1] target-arm: A64: Fix decoding of iss_sf in disas_ld_lit
@ 2016-10-01 1:15 ` Edgar Iglesias
0 siblings, 0 replies; 16+ messages in thread
From: Edgar Iglesias @ 2016-10-01 1:15 UTC (permalink / raw)
To: Peter Maydell; +Cc: Edgar E. Iglesias, Thomas Huth, qemu-devel, qemu-arm
Thanks :-)
Edgar
---
Sent from my phone
-------- Original Message --------
Subject: Re: [Qemu-devel] [PATCH v1 1/1] target-arm: A64: Fix decoding of iss_sf in disas_ld_lit
From: Peter Maydell <peter.maydell@linaro.org>
Date: 1 Oct 2016, 01:20
To: Edgar Iglesias <edgari@xilinx.com>
On 30 September 2016 at 14:42, Edgar Iglesias <edgar.iglesias@xilinx.com> wrote:
> Peter, feel free to change the syntax to whatever you feel is best.
Applied to target-arm.next, thanks. I picked "iss_sf = opc != 0;"
-- PMM
This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2016-10-01 1:15 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2016-09-30 10:19 [Qemu-devel] [PATCH v1 1/1] target-arm: A64: Fix decoding of iss_sf in disas_ld_lit Edgar E. Iglesias
2016-09-30 10:19 ` Edgar E. Iglesias
2016-09-30 10:42 ` [Qemu-arm] " Thomas Huth
2016-09-30 10:42 ` Thomas Huth
2016-09-30 10:49 ` Edgar E. Iglesias
2016-09-30 10:49 ` Edgar E. Iglesias
2016-09-30 17:34 ` Peter Maydell
2016-09-30 17:34 ` Peter Maydell
2016-09-30 18:36 ` [Qemu-arm] " Eric Blake
2016-09-30 18:36 ` Eric Blake
2016-09-30 21:42 ` [Qemu-arm] " Edgar Iglesias
2016-09-30 21:42 ` Edgar Iglesias
2016-09-30 23:19 ` [Qemu-arm] " Peter Maydell
2016-09-30 23:19 ` Peter Maydell
2016-10-01 1:15 ` [Qemu-arm] " Edgar Iglesias
2016-10-01 1:15 ` Edgar Iglesias
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