Re: [Qemu-devel] [PATCH v4 00/20] ppc/pnv: booting the kernel and reaching user space

[no-reply@patchew.org]

Hi,

Your series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 1475479496-16158-1-git-send-email-clg@kaod.org
Subject: [Qemu-devel] [PATCH v4 00/20] ppc/pnv: booting the kernel and reaching user space

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

# Useful git options
git config --local diff.renamelimit 0
git config --local diff.renames True

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
    echo "Checking PATCH $n/$total: $(git show --no-patch --format=%s $c)..."
    if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
        failed=1
        echo
    fi
    n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 * [new tag]         patchew/1475479496-16158-1-git-send-email-clg@kaod.org -> patchew/1475479496-16158-1-git-send-email-clg@kaod.org
Switched to a new branch 'test'
fcda1d2 ppc/pnv: add support for POWER9 LPC Controller
668c237 ppc/pnv: Add Naples chip support for LPC interrupts
49b9443 ppc/pnv: Add OCC model stub with interrupt support
a02fded ppc/pnv: Add cut down PSI bridge model and hookup external interrupt
9f27258 ppc/pnv: add a XICS native to each PowerNV chip
75067d5 ppc/xics: Add "native" XICS subclass
6a7865a ppc/xics: introduce a helper to insert a new ics
e25d4e5 ppc/xics: introduce helpers to find an ICP from some (CPU) index
75e1e0a ppc/xics: Add xics to the monitor "info pic" command
a1d20d4 ppc/xics: Split ICS into ics-base and ics class
1397a8c ppc/xics: Make the ICSState a list
8a8ae07 ppc/pnv: add a ISA bus
32f029b ppc/pnv: add a LPC controller
7a3791a ppc/pnv: add XSCOM handlers to PnvCore
358a0c8 ppc/pnv: add XSCOM infrastructure
bf2c920 ppc/pnv: add a PnvCore object
281f8e4 ppc/pnv: add a PIR handler to PnvChip
1d6f976 ppc/pnv: add a core mask to PnvChip
e1c6449 ppc/pnv: add a PnvChip object
e40906f ppc/pnv: add skeleton PowerNV platform

=== OUTPUT BEGIN ===
Checking PATCH 1/20: ppc/pnv: add skeleton PowerNV platform...
Checking PATCH 2/20: ppc/pnv: add a PnvChip object...
Checking PATCH 3/20: ppc/pnv: add a core mask to PnvChip...
Checking PATCH 4/20: ppc/pnv: add a PIR handler to PnvChip...
Checking PATCH 5/20: ppc/pnv: add a PnvCore object...
Checking PATCH 6/20: ppc/pnv: add XSCOM infrastructure...
Checking PATCH 7/20: ppc/pnv: add XSCOM handlers to PnvCore...
Checking PATCH 8/20: ppc/pnv: add a LPC controller...
Checking PATCH 9/20: ppc/pnv: add a ISA bus...
Checking PATCH 10/20: ppc/xics: Make the ICSState a list...
Checking PATCH 11/20: ppc/xics: Split ICS into ics-base and ics class...
Checking PATCH 12/20: ppc/xics: Add xics to the monitor "info pic" command...
Checking PATCH 13/20: ppc/xics: introduce helpers to find an ICP from some (CPU) index...
Checking PATCH 14/20: ppc/xics: introduce a helper to insert a new ics...
Checking PATCH 15/20: ppc/xics: Add "native" XICS subclass...
ERROR: spaces required around that '&' (ctx:WxV)
#308: FILE: hw/intc/xics_native.c:246:
+                        (gpointer) &xics->ss[cs->cpu_index]);
                                    ^

total: 1 errors, 0 warnings, 403 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 16/20: ppc/pnv: add a XICS native to each PowerNV chip...
Checking PATCH 17/20: ppc/pnv: Add cut down PSI bridge model and hookup external interrupt...
Checking PATCH 18/20: ppc/pnv: Add OCC model stub with interrupt support...
Checking PATCH 19/20: ppc/pnv: Add Naples chip support for LPC interrupts...
Checking PATCH 20/20: ppc/pnv: add support for POWER9 LPC Controller...
=== OUTPUT END ===

Test command exited with code: 1


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