* [PATCH 1/8] drm/i915/guc: Make the GuC fw loading helper functions general
2016-10-03 18:42 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa
@ 2016-10-03 18:42 ` Anusha Srivatsa
2016-10-13 15:04 ` Jeff McGee
2016-10-24 21:46 ` Carlos Santa
2016-10-03 18:42 ` [PATCH 2/8] drm/i915/huc: Unified css_header struct for GuC and HuC Anusha Srivatsa
` (8 subsequent siblings)
9 siblings, 2 replies; 35+ messages in thread
From: Anusha Srivatsa @ 2016-10-03 18:42 UTC (permalink / raw)
To: intel-gfx
From: Peter Antoine <peter.antoine@intel.com>
Rename some of the GuC fw loading code to make them more general. We
will utilise them for HuC loading as well.
s/intel_guc_fw/intel_uc_fw/g
s/GUC_FIRMWARE/UC_FIRMWARE/g
Struct intel_guc_fw is renamed to intel_uc_fw. Prefix of tts members,
such as 'guc' or 'guc_fw' either is renamed to 'uc' or removed for
same purpose.
v2: rebased on top of nightly.
reapplied the search/replace as upstream code as changed.
v3: rebased again on drm-nightly.
v4: removed G from messages in shared fw fetch function.
v5: rebased.
v7: rebased.
v8: rebased.
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 12 +--
drivers/gpu/drm/i915/i915_guc_submission.c | 4 +-
drivers/gpu/drm/i915/intel_guc.h | 39 ++++----
drivers/gpu/drm/i915/intel_guc_loader.c | 156 ++++++++++++++---------------
4 files changed, 106 insertions(+), 105 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 4fb9d82..44258a8 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2416,7 +2416,7 @@ static int i915_llc(struct seq_file *m, void *data)
static int i915_guc_load_status_info(struct seq_file *m, void *data)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
- struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
+ struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
u32 tmp, i;
if (!HAS_GUC_UCODE(dev_priv))
@@ -2424,15 +2424,15 @@ static int i915_guc_load_status_info(struct seq_file *m, void *data)
seq_printf(m, "GuC firmware status:\n");
seq_printf(m, "\tpath: %s\n",
- guc_fw->guc_fw_path);
+ guc_fw->uc_fw_path);
seq_printf(m, "\tfetch: %s\n",
- intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
+ intel_uc_fw_status_repr(guc_fw->fetch_status));
seq_printf(m, "\tload: %s\n",
- intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
+ intel_uc_fw_status_repr(guc_fw->load_status));
seq_printf(m, "\tversion wanted: %d.%d\n",
- guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
+ guc_fw->major_ver_wanted, guc_fw->minor_ver_wanted);
seq_printf(m, "\tversion found: %d.%d\n",
- guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
+ guc_fw->major_ver_found, guc_fw->minor_ver_found);
seq_printf(m, "\theader: offset is %d; size = %d\n",
guc_fw->header_offset, guc_fw->header_size);
seq_printf(m, "\tuCode: offset is %d; size = %d\n",
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index 43358e1..4b92943 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -1072,7 +1072,7 @@ int intel_guc_suspend(struct drm_device *dev)
struct i915_gem_context *ctx;
u32 data[3];
- if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
+ if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS)
return 0;
ctx = dev_priv->kernel_context;
@@ -1098,7 +1098,7 @@ int intel_guc_resume(struct drm_device *dev)
struct i915_gem_context *ctx;
u32 data[3];
- if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
+ if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS)
return 0;
ctx = dev_priv->kernel_context;
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index b1ba869..b134a41 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -91,29 +91,29 @@ struct i915_guc_client {
uint64_t submissions[I915_NUM_ENGINES];
};
-enum intel_guc_fw_status {
- GUC_FIRMWARE_FAIL = -1,
- GUC_FIRMWARE_NONE = 0,
- GUC_FIRMWARE_PENDING,
- GUC_FIRMWARE_SUCCESS
+enum intel_uc_fw_status {
+ UC_FIRMWARE_FAIL = -1,
+ UC_FIRMWARE_NONE = 0,
+ UC_FIRMWARE_PENDING,
+ UC_FIRMWARE_SUCCESS
};
/*
* This structure encapsulates all the data needed during the process
* of fetching, caching, and loading the firmware image into the GuC.
*/
-struct intel_guc_fw {
- struct drm_device * guc_dev;
- const char * guc_fw_path;
- size_t guc_fw_size;
- struct drm_i915_gem_object * guc_fw_obj;
- enum intel_guc_fw_status guc_fw_fetch_status;
- enum intel_guc_fw_status guc_fw_load_status;
-
- uint16_t guc_fw_major_wanted;
- uint16_t guc_fw_minor_wanted;
- uint16_t guc_fw_major_found;
- uint16_t guc_fw_minor_found;
+struct intel_uc_fw {
+ struct drm_device *uc_dev;
+ const char *uc_fw_path;
+ size_t uc_fw_size;
+ struct drm_i915_gem_object *uc_fw_obj;
+ enum intel_uc_fw_status fetch_status;
+ enum intel_uc_fw_status load_status;
+
+ uint16_t major_ver_wanted;
+ uint16_t minor_ver_wanted;
+ uint16_t major_ver_found;
+ uint16_t minor_ver_found;
uint32_t header_size;
uint32_t header_offset;
@@ -124,7 +124,7 @@ struct intel_guc_fw {
};
struct intel_guc {
- struct intel_guc_fw guc_fw;
+ struct intel_uc_fw guc_fw;
uint32_t log_flags;
struct i915_vma *log_vma;
@@ -152,9 +152,10 @@ struct intel_guc {
extern void intel_guc_init(struct drm_device *dev);
extern int intel_guc_setup(struct drm_device *dev);
extern void intel_guc_fini(struct drm_device *dev);
-extern const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status);
+extern const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status);
extern int intel_guc_suspend(struct drm_device *dev);
extern int intel_guc_resume(struct drm_device *dev);
+void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw);
/* i915_guc_submission.c */
int i915_guc_submission_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 7ace96b..493295d 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -81,16 +81,16 @@ MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
/* User-friendly representation of an enum */
-const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
+const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status)
{
switch (status) {
- case GUC_FIRMWARE_FAIL:
+ case UC_FIRMWARE_FAIL:
return "FAIL";
- case GUC_FIRMWARE_NONE:
+ case UC_FIRMWARE_NONE:
return "NONE";
- case GUC_FIRMWARE_PENDING:
+ case UC_FIRMWARE_PENDING:
return "PENDING";
- case GUC_FIRMWARE_SUCCESS:
+ case UC_FIRMWARE_SUCCESS:
return "SUCCESS";
default:
return "UNKNOWN!";
@@ -274,7 +274,7 @@ static inline bool guc_ucode_response(struct drm_i915_private *dev_priv,
static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
struct i915_vma *vma)
{
- struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
+ struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
unsigned long offset;
struct sg_table *sg = vma->pages;
u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT];
@@ -346,18 +346,18 @@ static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
*/
static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
{
- struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
+ struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
struct drm_device *dev = &dev_priv->drm;
struct i915_vma *vma;
int ret;
- ret = i915_gem_object_set_to_gtt_domain(guc_fw->guc_fw_obj, false);
+ ret = i915_gem_object_set_to_gtt_domain(guc_fw->uc_fw_obj, false);
if (ret) {
DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
return ret;
}
- vma = i915_gem_object_ggtt_pin(guc_fw->guc_fw_obj, NULL, 0, 0, 0);
+ vma = i915_gem_object_ggtt_pin(guc_fw->uc_fw_obj, NULL, 0, 0, 0);
if (IS_ERR(vma)) {
DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
return PTR_ERR(vma);
@@ -448,14 +448,14 @@ static int guc_hw_reset(struct drm_i915_private *dev_priv)
int intel_guc_setup(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
- const char *fw_path = guc_fw->guc_fw_path;
+ struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
+ const char *fw_path = guc_fw->uc_fw_path;
int retries, ret, err;
DRM_DEBUG_DRIVER("GuC fw status: path %s, fetch %s, load %s\n",
fw_path,
- intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
- intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
+ intel_uc_fw_status_repr(guc_fw->fetch_status),
+ intel_uc_fw_status_repr(guc_fw->load_status));
/* Loading forbidden, or no firmware to load? */
if (!i915.enable_guc_loading) {
@@ -473,21 +473,21 @@ int intel_guc_setup(struct drm_device *dev)
}
/* Fetch failed, or already fetched but failed to load? */
- if (guc_fw->guc_fw_fetch_status != GUC_FIRMWARE_SUCCESS) {
+ if (guc_fw->fetch_status != UC_FIRMWARE_SUCCESS) {
err = -EIO;
goto fail;
- } else if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_FAIL) {
+ } else if (guc_fw->load_status == UC_FIRMWARE_FAIL) {
err = -ENOEXEC;
goto fail;
}
guc_interrupts_release(dev_priv);
- guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
+ guc_fw->load_status = UC_FIRMWARE_PENDING;
DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
- intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
- intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
+ intel_uc_fw_status_repr(guc_fw->fetch_status),
+ intel_uc_fw_status_repr(guc_fw->load_status));
err = i915_guc_submission_init(dev_priv);
if (err)
@@ -519,11 +519,11 @@ int intel_guc_setup(struct drm_device *dev)
"retry %d more time(s)\n", err, retries);
}
- guc_fw->guc_fw_load_status = GUC_FIRMWARE_SUCCESS;
+ guc_fw->load_status = UC_FIRMWARE_SUCCESS;
DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
- intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
- intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
+ intel_uc_fw_status_repr(guc_fw->fetch_status),
+ intel_uc_fw_status_repr(guc_fw->load_status));
if (i915.enable_guc_submission) {
err = i915_guc_submission_enable(dev_priv);
@@ -535,8 +535,8 @@ int intel_guc_setup(struct drm_device *dev)
return 0;
fail:
- if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_PENDING)
- guc_fw->guc_fw_load_status = GUC_FIRMWARE_FAIL;
+ if (guc_fw->load_status == UC_FIRMWARE_PENDING)
+ guc_fw->load_status = UC_FIRMWARE_FAIL;
guc_interrupts_release(dev_priv);
i915_guc_submission_disable(dev_priv);
@@ -581,7 +581,7 @@ fail:
return ret;
}
-static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
+void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw)
{
struct pci_dev *pdev = dev->pdev;
struct drm_i915_gem_object *obj;
@@ -590,17 +590,17 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
size_t size;
int err;
- DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n",
- intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
+ DRM_DEBUG_DRIVER("before requesting firmware: uC fw fetch status %s\n",
+ intel_uc_fw_status_repr(uc_fw->fetch_status));
- err = request_firmware(&fw, guc_fw->guc_fw_path, &pdev->dev);
+ err = request_firmware(&fw, uc_fw->uc_fw_path, &pdev->dev);
if (err)
goto fail;
if (!fw)
goto fail;
- DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n",
- guc_fw->guc_fw_path, fw);
+ DRM_DEBUG_DRIVER("fetch uC fw from %s succeeded, fw %p\n",
+ uc_fw->uc_fw_path, fw);
/* Check the size of the blob before examining buffer contents */
if (fw->size < sizeof(struct guc_css_header)) {
@@ -611,36 +611,36 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
css = (struct guc_css_header *)fw->data;
/* Firmware bits always start from header */
- guc_fw->header_offset = 0;
- guc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
+ uc_fw->header_offset = 0;
+ uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
- if (guc_fw->header_size != sizeof(struct guc_css_header)) {
+ if (uc_fw->header_size != sizeof(struct guc_css_header)) {
DRM_NOTE("CSS header definition mismatch\n");
goto fail;
}
/* then, uCode */
- guc_fw->ucode_offset = guc_fw->header_offset + guc_fw->header_size;
- guc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
+ uc_fw->ucode_offset = uc_fw->header_offset + uc_fw->header_size;
+ uc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
/* now RSA */
if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) {
DRM_NOTE("RSA key size is bad\n");
goto fail;
}
- guc_fw->rsa_offset = guc_fw->ucode_offset + guc_fw->ucode_size;
- guc_fw->rsa_size = css->key_size_dw * sizeof(u32);
+ uc_fw->rsa_offset = uc_fw->ucode_offset + uc_fw->ucode_size;
+ uc_fw->rsa_size = css->key_size_dw * sizeof(u32);
/* At least, it should have header, uCode and RSA. Size of all three. */
- size = guc_fw->header_size + guc_fw->ucode_size + guc_fw->rsa_size;
+ size = uc_fw->header_size + uc_fw->ucode_size + uc_fw->rsa_size;
if (fw->size < size) {
DRM_NOTE("Missing firmware components\n");
goto fail;
}
/* Header and uCode will be loaded to WOPCM. Size of the two. */
- size = guc_fw->header_size + guc_fw->ucode_size;
+ size = uc_fw->header_size + uc_fw->ucode_size;
if (size > guc_wopcm_size(to_i915(dev))) {
DRM_NOTE("Firmware is too large to fit in WOPCM\n");
goto fail;
@@ -652,21 +652,21 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
* TWO bytes each (i.e. u16), although all pointers and offsets are defined
* in terms of bytes (u8).
*/
- guc_fw->guc_fw_major_found = css->guc_sw_version >> 16;
- guc_fw->guc_fw_minor_found = css->guc_sw_version & 0xFFFF;
-
- if (guc_fw->guc_fw_major_found != guc_fw->guc_fw_major_wanted ||
- guc_fw->guc_fw_minor_found < guc_fw->guc_fw_minor_wanted) {
- DRM_NOTE("GuC firmware version %d.%d, required %d.%d\n",
- guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
- guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
+ uc_fw->major_ver_found = css->guc_sw_version >> 16;
+ uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
+
+ if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
+ uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) {
+ DRM_NOTE("uC firmware version %d.%d, required %d.%d\n",
+ uc_fw->major_ver_found, uc_fw->minor_ver_found,
+ uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
err = -ENOEXEC;
goto fail;
}
DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n",
- guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
- guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
+ uc_fw->major_ver_found, uc_fw->minor_ver_found,
+ uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
mutex_lock(&dev->struct_mutex);
obj = i915_gem_object_create_from_data(dev, fw->data, fw->size);
@@ -676,31 +676,31 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
goto fail;
}
- guc_fw->guc_fw_obj = obj;
- guc_fw->guc_fw_size = fw->size;
+ uc_fw->uc_fw_obj = obj;
+ uc_fw->uc_fw_size = fw->size;
- DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n",
- guc_fw->guc_fw_obj);
+ DRM_DEBUG_DRIVER("uC fw fetch status SUCCESS, obj %p\n",
+ uc_fw->uc_fw_obj);
release_firmware(fw);
- guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_SUCCESS;
+ uc_fw->fetch_status = UC_FIRMWARE_SUCCESS;
return;
fail:
- DRM_WARN("Failed to fetch valid GuC firmware from %s (error %d)\n",
- guc_fw->guc_fw_path, err);
- DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n",
- err, fw, guc_fw->guc_fw_obj);
+ DRM_WARN("Failed to fetch valid uC firmware from %s (error %d)\n",
+ uc_fw->uc_fw_path, err);
+ DRM_DEBUG_DRIVER("uC fw fetch status FAIL; err %d, fw %p, obj %p\n",
+ err, fw, uc_fw->uc_fw_obj);
mutex_lock(&dev->struct_mutex);
- obj = guc_fw->guc_fw_obj;
+ obj = uc_fw->uc_fw_obj;
if (obj)
i915_gem_object_put(obj);
- guc_fw->guc_fw_obj = NULL;
+ uc_fw->uc_fw_obj = NULL;
mutex_unlock(&dev->struct_mutex);
release_firmware(fw); /* OK even if fw is NULL */
- guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
+ uc_fw->fetch_status = UC_FIRMWARE_FAIL;
}
/**
@@ -715,7 +715,7 @@ fail:
void intel_guc_init(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
+ struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
const char *fw_path;
/* A negative value means "use platform default" */
@@ -728,24 +728,24 @@ void intel_guc_init(struct drm_device *dev)
fw_path = NULL;
} else if (IS_SKYLAKE(dev)) {
fw_path = I915_SKL_GUC_UCODE;
- guc_fw->guc_fw_major_wanted = SKL_FW_MAJOR;
- guc_fw->guc_fw_minor_wanted = SKL_FW_MINOR;
+ guc_fw->major_ver_wanted = SKL_FW_MAJOR;
+ guc_fw->minor_ver_wanted = SKL_FW_MINOR;
} else if (IS_BROXTON(dev)) {
fw_path = I915_BXT_GUC_UCODE;
- guc_fw->guc_fw_major_wanted = BXT_FW_MAJOR;
- guc_fw->guc_fw_minor_wanted = BXT_FW_MINOR;
+ guc_fw->major_ver_wanted = BXT_FW_MAJOR;
+ guc_fw->minor_ver_wanted = BXT_FW_MINOR;
} else if (IS_KABYLAKE(dev)) {
fw_path = I915_KBL_GUC_UCODE;
- guc_fw->guc_fw_major_wanted = KBL_FW_MAJOR;
- guc_fw->guc_fw_minor_wanted = KBL_FW_MINOR;
+ guc_fw->major_ver_wanted = KBL_FW_MAJOR;
+ guc_fw->minor_ver_wanted = KBL_FW_MINOR;
} else {
fw_path = ""; /* unknown device */
}
- guc_fw->guc_dev = dev;
- guc_fw->guc_fw_path = fw_path;
- guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
- guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE;
+ guc_fw->uc_dev = dev;
+ guc_fw->uc_fw_path = fw_path;
+ guc_fw->fetch_status = UC_FIRMWARE_NONE;
+ guc_fw->load_status = UC_FIRMWARE_NONE;
/* Early (and silent) return if GuC loading is disabled */
if (!i915.enable_guc_loading)
@@ -755,9 +755,9 @@ void intel_guc_init(struct drm_device *dev)
if (*fw_path == '\0')
return;
- guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING;
+ guc_fw->fetch_status = UC_FIRMWARE_PENDING;
DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path);
- guc_fw_fetch(dev, guc_fw);
+ intel_uc_fw_fetch(dev, guc_fw);
/* status must now be FAIL or SUCCESS */
}
@@ -768,17 +768,17 @@ void intel_guc_init(struct drm_device *dev)
void intel_guc_fini(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
+ struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
mutex_lock(&dev->struct_mutex);
guc_interrupts_release(dev_priv);
i915_guc_submission_disable(dev_priv);
i915_guc_submission_fini(dev_priv);
- if (guc_fw->guc_fw_obj)
- i915_gem_object_put(guc_fw->guc_fw_obj);
- guc_fw->guc_fw_obj = NULL;
+ if (guc_fw->uc_fw_obj)
+ i915_gem_object_put(guc_fw->uc_fw_obj);
+ guc_fw->uc_fw_obj = NULL;
mutex_unlock(&dev->struct_mutex);
- guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
+ guc_fw->fetch_status = UC_FIRMWARE_NONE;
}
--
2.7.4
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^ permalink raw reply related [flat|nested] 35+ messages in thread* Re: [PATCH 1/8] drm/i915/guc: Make the GuC fw loading helper functions general
2016-10-03 18:42 ` [PATCH 1/8] drm/i915/guc: Make the GuC fw loading helper functions general Anusha Srivatsa
@ 2016-10-13 15:04 ` Jeff McGee
2016-10-24 21:46 ` Carlos Santa
1 sibling, 0 replies; 35+ messages in thread
From: Jeff McGee @ 2016-10-13 15:04 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
Reviewed-by: Jeff McGee <jeff.mcgee@intel.com>
On Mon, Oct 03, 2016 at 11:42:55AM -0700, Anusha Srivatsa wrote:
> From: Peter Antoine <peter.antoine@intel.com>
>
> Rename some of the GuC fw loading code to make them more general. We
> will utilise them for HuC loading as well.
> s/intel_guc_fw/intel_uc_fw/g
> s/GUC_FIRMWARE/UC_FIRMWARE/g
>
> Struct intel_guc_fw is renamed to intel_uc_fw. Prefix of tts members,
> such as 'guc' or 'guc_fw' either is renamed to 'uc' or removed for
> same purpose.
>
> v2: rebased on top of nightly.
> reapplied the search/replace as upstream code as changed.
> v3: rebased again on drm-nightly.
> v4: removed G from messages in shared fw fetch function.
> v5: rebased.
> v7: rebased.
> v8: rebased.
>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 12 +--
> drivers/gpu/drm/i915/i915_guc_submission.c | 4 +-
> drivers/gpu/drm/i915/intel_guc.h | 39 ++++----
> drivers/gpu/drm/i915/intel_guc_loader.c | 156 ++++++++++++++---------------
> 4 files changed, 106 insertions(+), 105 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 4fb9d82..44258a8 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2416,7 +2416,7 @@ static int i915_llc(struct seq_file *m, void *data)
> static int i915_guc_load_status_info(struct seq_file *m, void *data)
> {
> struct drm_i915_private *dev_priv = node_to_i915(m->private);
> - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> u32 tmp, i;
>
> if (!HAS_GUC_UCODE(dev_priv))
> @@ -2424,15 +2424,15 @@ static int i915_guc_load_status_info(struct seq_file *m, void *data)
>
> seq_printf(m, "GuC firmware status:\n");
> seq_printf(m, "\tpath: %s\n",
> - guc_fw->guc_fw_path);
> + guc_fw->uc_fw_path);
> seq_printf(m, "\tfetch: %s\n",
> - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
> + intel_uc_fw_status_repr(guc_fw->fetch_status));
> seq_printf(m, "\tload: %s\n",
> - intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
> + intel_uc_fw_status_repr(guc_fw->load_status));
> seq_printf(m, "\tversion wanted: %d.%d\n",
> - guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
> + guc_fw->major_ver_wanted, guc_fw->minor_ver_wanted);
> seq_printf(m, "\tversion found: %d.%d\n",
> - guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
> + guc_fw->major_ver_found, guc_fw->minor_ver_found);
> seq_printf(m, "\theader: offset is %d; size = %d\n",
> guc_fw->header_offset, guc_fw->header_size);
> seq_printf(m, "\tuCode: offset is %d; size = %d\n",
> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
> index 43358e1..4b92943 100644
> --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> @@ -1072,7 +1072,7 @@ int intel_guc_suspend(struct drm_device *dev)
> struct i915_gem_context *ctx;
> u32 data[3];
>
> - if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
> + if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS)
> return 0;
>
> ctx = dev_priv->kernel_context;
> @@ -1098,7 +1098,7 @@ int intel_guc_resume(struct drm_device *dev)
> struct i915_gem_context *ctx;
> u32 data[3];
>
> - if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
> + if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS)
> return 0;
>
> ctx = dev_priv->kernel_context;
> diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
> index b1ba869..b134a41 100644
> --- a/drivers/gpu/drm/i915/intel_guc.h
> +++ b/drivers/gpu/drm/i915/intel_guc.h
> @@ -91,29 +91,29 @@ struct i915_guc_client {
> uint64_t submissions[I915_NUM_ENGINES];
> };
>
> -enum intel_guc_fw_status {
> - GUC_FIRMWARE_FAIL = -1,
> - GUC_FIRMWARE_NONE = 0,
> - GUC_FIRMWARE_PENDING,
> - GUC_FIRMWARE_SUCCESS
> +enum intel_uc_fw_status {
> + UC_FIRMWARE_FAIL = -1,
> + UC_FIRMWARE_NONE = 0,
> + UC_FIRMWARE_PENDING,
> + UC_FIRMWARE_SUCCESS
> };
>
> /*
> * This structure encapsulates all the data needed during the process
> * of fetching, caching, and loading the firmware image into the GuC.
> */
> -struct intel_guc_fw {
> - struct drm_device * guc_dev;
> - const char * guc_fw_path;
> - size_t guc_fw_size;
> - struct drm_i915_gem_object * guc_fw_obj;
> - enum intel_guc_fw_status guc_fw_fetch_status;
> - enum intel_guc_fw_status guc_fw_load_status;
> -
> - uint16_t guc_fw_major_wanted;
> - uint16_t guc_fw_minor_wanted;
> - uint16_t guc_fw_major_found;
> - uint16_t guc_fw_minor_found;
> +struct intel_uc_fw {
> + struct drm_device *uc_dev;
> + const char *uc_fw_path;
> + size_t uc_fw_size;
> + struct drm_i915_gem_object *uc_fw_obj;
> + enum intel_uc_fw_status fetch_status;
> + enum intel_uc_fw_status load_status;
> +
> + uint16_t major_ver_wanted;
> + uint16_t minor_ver_wanted;
> + uint16_t major_ver_found;
> + uint16_t minor_ver_found;
>
> uint32_t header_size;
> uint32_t header_offset;
> @@ -124,7 +124,7 @@ struct intel_guc_fw {
> };
>
> struct intel_guc {
> - struct intel_guc_fw guc_fw;
> + struct intel_uc_fw guc_fw;
> uint32_t log_flags;
> struct i915_vma *log_vma;
>
> @@ -152,9 +152,10 @@ struct intel_guc {
> extern void intel_guc_init(struct drm_device *dev);
> extern int intel_guc_setup(struct drm_device *dev);
> extern void intel_guc_fini(struct drm_device *dev);
> -extern const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status);
> +extern const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status);
> extern int intel_guc_suspend(struct drm_device *dev);
> extern int intel_guc_resume(struct drm_device *dev);
> +void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw);
>
> /* i915_guc_submission.c */
> int i915_guc_submission_init(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 7ace96b..493295d 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -81,16 +81,16 @@ MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
> MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
>
> /* User-friendly representation of an enum */
> -const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
> +const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status)
> {
> switch (status) {
> - case GUC_FIRMWARE_FAIL:
> + case UC_FIRMWARE_FAIL:
> return "FAIL";
> - case GUC_FIRMWARE_NONE:
> + case UC_FIRMWARE_NONE:
> return "NONE";
> - case GUC_FIRMWARE_PENDING:
> + case UC_FIRMWARE_PENDING:
> return "PENDING";
> - case GUC_FIRMWARE_SUCCESS:
> + case UC_FIRMWARE_SUCCESS:
> return "SUCCESS";
> default:
> return "UNKNOWN!";
> @@ -274,7 +274,7 @@ static inline bool guc_ucode_response(struct drm_i915_private *dev_priv,
> static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
> struct i915_vma *vma)
> {
> - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> unsigned long offset;
> struct sg_table *sg = vma->pages;
> u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT];
> @@ -346,18 +346,18 @@ static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
> */
> static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
> {
> - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> struct drm_device *dev = &dev_priv->drm;
> struct i915_vma *vma;
> int ret;
>
> - ret = i915_gem_object_set_to_gtt_domain(guc_fw->guc_fw_obj, false);
> + ret = i915_gem_object_set_to_gtt_domain(guc_fw->uc_fw_obj, false);
> if (ret) {
> DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
> return ret;
> }
>
> - vma = i915_gem_object_ggtt_pin(guc_fw->guc_fw_obj, NULL, 0, 0, 0);
> + vma = i915_gem_object_ggtt_pin(guc_fw->uc_fw_obj, NULL, 0, 0, 0);
> if (IS_ERR(vma)) {
> DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
> return PTR_ERR(vma);
> @@ -448,14 +448,14 @@ static int guc_hw_reset(struct drm_i915_private *dev_priv)
> int intel_guc_setup(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
> - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> - const char *fw_path = guc_fw->guc_fw_path;
> + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> + const char *fw_path = guc_fw->uc_fw_path;
> int retries, ret, err;
>
> DRM_DEBUG_DRIVER("GuC fw status: path %s, fetch %s, load %s\n",
> fw_path,
> - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
> - intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
> + intel_uc_fw_status_repr(guc_fw->fetch_status),
> + intel_uc_fw_status_repr(guc_fw->load_status));
>
> /* Loading forbidden, or no firmware to load? */
> if (!i915.enable_guc_loading) {
> @@ -473,21 +473,21 @@ int intel_guc_setup(struct drm_device *dev)
> }
>
> /* Fetch failed, or already fetched but failed to load? */
> - if (guc_fw->guc_fw_fetch_status != GUC_FIRMWARE_SUCCESS) {
> + if (guc_fw->fetch_status != UC_FIRMWARE_SUCCESS) {
> err = -EIO;
> goto fail;
> - } else if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_FAIL) {
> + } else if (guc_fw->load_status == UC_FIRMWARE_FAIL) {
> err = -ENOEXEC;
> goto fail;
> }
>
> guc_interrupts_release(dev_priv);
>
> - guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
> + guc_fw->load_status = UC_FIRMWARE_PENDING;
>
> DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
> - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
> - intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
> + intel_uc_fw_status_repr(guc_fw->fetch_status),
> + intel_uc_fw_status_repr(guc_fw->load_status));
>
> err = i915_guc_submission_init(dev_priv);
> if (err)
> @@ -519,11 +519,11 @@ int intel_guc_setup(struct drm_device *dev)
> "retry %d more time(s)\n", err, retries);
> }
>
> - guc_fw->guc_fw_load_status = GUC_FIRMWARE_SUCCESS;
> + guc_fw->load_status = UC_FIRMWARE_SUCCESS;
>
> DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
> - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
> - intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
> + intel_uc_fw_status_repr(guc_fw->fetch_status),
> + intel_uc_fw_status_repr(guc_fw->load_status));
>
> if (i915.enable_guc_submission) {
> err = i915_guc_submission_enable(dev_priv);
> @@ -535,8 +535,8 @@ int intel_guc_setup(struct drm_device *dev)
> return 0;
>
> fail:
> - if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_PENDING)
> - guc_fw->guc_fw_load_status = GUC_FIRMWARE_FAIL;
> + if (guc_fw->load_status == UC_FIRMWARE_PENDING)
> + guc_fw->load_status = UC_FIRMWARE_FAIL;
>
> guc_interrupts_release(dev_priv);
> i915_guc_submission_disable(dev_priv);
> @@ -581,7 +581,7 @@ fail:
> return ret;
> }
>
> -static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
> +void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw)
> {
> struct pci_dev *pdev = dev->pdev;
> struct drm_i915_gem_object *obj;
> @@ -590,17 +590,17 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
> size_t size;
> int err;
>
> - DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n",
> - intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
> + DRM_DEBUG_DRIVER("before requesting firmware: uC fw fetch status %s\n",
> + intel_uc_fw_status_repr(uc_fw->fetch_status));
>
> - err = request_firmware(&fw, guc_fw->guc_fw_path, &pdev->dev);
> + err = request_firmware(&fw, uc_fw->uc_fw_path, &pdev->dev);
> if (err)
> goto fail;
> if (!fw)
> goto fail;
>
> - DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n",
> - guc_fw->guc_fw_path, fw);
> + DRM_DEBUG_DRIVER("fetch uC fw from %s succeeded, fw %p\n",
> + uc_fw->uc_fw_path, fw);
>
> /* Check the size of the blob before examining buffer contents */
> if (fw->size < sizeof(struct guc_css_header)) {
> @@ -611,36 +611,36 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
> css = (struct guc_css_header *)fw->data;
>
> /* Firmware bits always start from header */
> - guc_fw->header_offset = 0;
> - guc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
> + uc_fw->header_offset = 0;
> + uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
> css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
>
> - if (guc_fw->header_size != sizeof(struct guc_css_header)) {
> + if (uc_fw->header_size != sizeof(struct guc_css_header)) {
> DRM_NOTE("CSS header definition mismatch\n");
> goto fail;
> }
>
> /* then, uCode */
> - guc_fw->ucode_offset = guc_fw->header_offset + guc_fw->header_size;
> - guc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
> + uc_fw->ucode_offset = uc_fw->header_offset + uc_fw->header_size;
> + uc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
>
> /* now RSA */
> if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) {
> DRM_NOTE("RSA key size is bad\n");
> goto fail;
> }
> - guc_fw->rsa_offset = guc_fw->ucode_offset + guc_fw->ucode_size;
> - guc_fw->rsa_size = css->key_size_dw * sizeof(u32);
> + uc_fw->rsa_offset = uc_fw->ucode_offset + uc_fw->ucode_size;
> + uc_fw->rsa_size = css->key_size_dw * sizeof(u32);
>
> /* At least, it should have header, uCode and RSA. Size of all three. */
> - size = guc_fw->header_size + guc_fw->ucode_size + guc_fw->rsa_size;
> + size = uc_fw->header_size + uc_fw->ucode_size + uc_fw->rsa_size;
> if (fw->size < size) {
> DRM_NOTE("Missing firmware components\n");
> goto fail;
> }
>
> /* Header and uCode will be loaded to WOPCM. Size of the two. */
> - size = guc_fw->header_size + guc_fw->ucode_size;
> + size = uc_fw->header_size + uc_fw->ucode_size;
> if (size > guc_wopcm_size(to_i915(dev))) {
> DRM_NOTE("Firmware is too large to fit in WOPCM\n");
> goto fail;
> @@ -652,21 +652,21 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
> * TWO bytes each (i.e. u16), although all pointers and offsets are defined
> * in terms of bytes (u8).
> */
> - guc_fw->guc_fw_major_found = css->guc_sw_version >> 16;
> - guc_fw->guc_fw_minor_found = css->guc_sw_version & 0xFFFF;
> -
> - if (guc_fw->guc_fw_major_found != guc_fw->guc_fw_major_wanted ||
> - guc_fw->guc_fw_minor_found < guc_fw->guc_fw_minor_wanted) {
> - DRM_NOTE("GuC firmware version %d.%d, required %d.%d\n",
> - guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
> - guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
> + uc_fw->major_ver_found = css->guc_sw_version >> 16;
> + uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
> +
> + if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
> + uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) {
> + DRM_NOTE("uC firmware version %d.%d, required %d.%d\n",
> + uc_fw->major_ver_found, uc_fw->minor_ver_found,
> + uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
> err = -ENOEXEC;
> goto fail;
> }
>
> DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n",
> - guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
> - guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
> + uc_fw->major_ver_found, uc_fw->minor_ver_found,
> + uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
>
> mutex_lock(&dev->struct_mutex);
> obj = i915_gem_object_create_from_data(dev, fw->data, fw->size);
> @@ -676,31 +676,31 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
> goto fail;
> }
>
> - guc_fw->guc_fw_obj = obj;
> - guc_fw->guc_fw_size = fw->size;
> + uc_fw->uc_fw_obj = obj;
> + uc_fw->uc_fw_size = fw->size;
>
> - DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n",
> - guc_fw->guc_fw_obj);
> + DRM_DEBUG_DRIVER("uC fw fetch status SUCCESS, obj %p\n",
> + uc_fw->uc_fw_obj);
>
> release_firmware(fw);
> - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_SUCCESS;
> + uc_fw->fetch_status = UC_FIRMWARE_SUCCESS;
> return;
>
> fail:
> - DRM_WARN("Failed to fetch valid GuC firmware from %s (error %d)\n",
> - guc_fw->guc_fw_path, err);
> - DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n",
> - err, fw, guc_fw->guc_fw_obj);
> + DRM_WARN("Failed to fetch valid uC firmware from %s (error %d)\n",
> + uc_fw->uc_fw_path, err);
> + DRM_DEBUG_DRIVER("uC fw fetch status FAIL; err %d, fw %p, obj %p\n",
> + err, fw, uc_fw->uc_fw_obj);
>
> mutex_lock(&dev->struct_mutex);
> - obj = guc_fw->guc_fw_obj;
> + obj = uc_fw->uc_fw_obj;
> if (obj)
> i915_gem_object_put(obj);
> - guc_fw->guc_fw_obj = NULL;
> + uc_fw->uc_fw_obj = NULL;
> mutex_unlock(&dev->struct_mutex);
>
> release_firmware(fw); /* OK even if fw is NULL */
> - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
> + uc_fw->fetch_status = UC_FIRMWARE_FAIL;
> }
>
> /**
> @@ -715,7 +715,7 @@ fail:
> void intel_guc_init(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
> - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> const char *fw_path;
>
> /* A negative value means "use platform default" */
> @@ -728,24 +728,24 @@ void intel_guc_init(struct drm_device *dev)
> fw_path = NULL;
> } else if (IS_SKYLAKE(dev)) {
> fw_path = I915_SKL_GUC_UCODE;
> - guc_fw->guc_fw_major_wanted = SKL_FW_MAJOR;
> - guc_fw->guc_fw_minor_wanted = SKL_FW_MINOR;
> + guc_fw->major_ver_wanted = SKL_FW_MAJOR;
> + guc_fw->minor_ver_wanted = SKL_FW_MINOR;
> } else if (IS_BROXTON(dev)) {
> fw_path = I915_BXT_GUC_UCODE;
> - guc_fw->guc_fw_major_wanted = BXT_FW_MAJOR;
> - guc_fw->guc_fw_minor_wanted = BXT_FW_MINOR;
> + guc_fw->major_ver_wanted = BXT_FW_MAJOR;
> + guc_fw->minor_ver_wanted = BXT_FW_MINOR;
> } else if (IS_KABYLAKE(dev)) {
> fw_path = I915_KBL_GUC_UCODE;
> - guc_fw->guc_fw_major_wanted = KBL_FW_MAJOR;
> - guc_fw->guc_fw_minor_wanted = KBL_FW_MINOR;
> + guc_fw->major_ver_wanted = KBL_FW_MAJOR;
> + guc_fw->minor_ver_wanted = KBL_FW_MINOR;
> } else {
> fw_path = ""; /* unknown device */
> }
>
> - guc_fw->guc_dev = dev;
> - guc_fw->guc_fw_path = fw_path;
> - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
> - guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE;
> + guc_fw->uc_dev = dev;
> + guc_fw->uc_fw_path = fw_path;
> + guc_fw->fetch_status = UC_FIRMWARE_NONE;
> + guc_fw->load_status = UC_FIRMWARE_NONE;
>
> /* Early (and silent) return if GuC loading is disabled */
> if (!i915.enable_guc_loading)
> @@ -755,9 +755,9 @@ void intel_guc_init(struct drm_device *dev)
> if (*fw_path == '\0')
> return;
>
> - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING;
> + guc_fw->fetch_status = UC_FIRMWARE_PENDING;
> DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path);
> - guc_fw_fetch(dev, guc_fw);
> + intel_uc_fw_fetch(dev, guc_fw);
> /* status must now be FAIL or SUCCESS */
> }
>
> @@ -768,17 +768,17 @@ void intel_guc_init(struct drm_device *dev)
> void intel_guc_fini(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
> - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
>
> mutex_lock(&dev->struct_mutex);
> guc_interrupts_release(dev_priv);
> i915_guc_submission_disable(dev_priv);
> i915_guc_submission_fini(dev_priv);
>
> - if (guc_fw->guc_fw_obj)
> - i915_gem_object_put(guc_fw->guc_fw_obj);
> - guc_fw->guc_fw_obj = NULL;
> + if (guc_fw->uc_fw_obj)
> + i915_gem_object_put(guc_fw->uc_fw_obj);
> + guc_fw->uc_fw_obj = NULL;
> mutex_unlock(&dev->struct_mutex);
>
> - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
> + guc_fw->fetch_status = UC_FIRMWARE_NONE;
> }
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [PATCH 1/8] drm/i915/guc: Make the GuC fw loading helper functions general
2016-10-03 18:42 ` [PATCH 1/8] drm/i915/guc: Make the GuC fw loading helper functions general Anusha Srivatsa
2016-10-13 15:04 ` Jeff McGee
@ 2016-10-24 21:46 ` Carlos Santa
1 sibling, 0 replies; 35+ messages in thread
From: Carlos Santa @ 2016-10-24 21:46 UTC (permalink / raw)
To: Anusha Srivatsa, intel-gfx
Reviewed-by: Carlos Santa <carlos.santa@intel.com>
Tested-by: Carlos Santa <carlos.santa@intel.com>
On Mon, 2016-10-03 at 11:42 -0700, Anusha Srivatsa wrote:
> From: Peter Antoine <peter.antoine@intel.com>
>
> Rename some of the GuC fw loading code to make them more general. We
> will utilise them for HuC loading as well.
> s/intel_guc_fw/intel_uc_fw/g
> s/GUC_FIRMWARE/UC_FIRMWARE/g
>
> Struct intel_guc_fw is renamed to intel_uc_fw. Prefix of tts members,
> such as 'guc' or 'guc_fw' either is renamed to 'uc' or removed for
> same purpose.
>
> v2: rebased on top of nightly.
> reapplied the search/replace as upstream code as changed.
> v3: rebased again on drm-nightly.
> v4: removed G from messages in shared fw fetch function.
> v5: rebased.
> v7: rebased.
> v8: rebased.
>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 12 +--
> drivers/gpu/drm/i915/i915_guc_submission.c | 4 +-
> drivers/gpu/drm/i915/intel_guc.h | 39 ++++----
> drivers/gpu/drm/i915/intel_guc_loader.c | 156 ++++++++++++++-----
> ----------
> 4 files changed, 106 insertions(+), 105 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 4fb9d82..44258a8 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2416,7 +2416,7 @@ static int i915_llc(struct seq_file *m, void
> *data)
> static int i915_guc_load_status_info(struct seq_file *m, void *data)
> {
> struct drm_i915_private *dev_priv = node_to_i915(m-
> >private);
> - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> u32 tmp, i;
>
> if (!HAS_GUC_UCODE(dev_priv))
> @@ -2424,15 +2424,15 @@ static int i915_guc_load_status_info(struct
> seq_file *m, void *data)
>
> seq_printf(m, "GuC firmware status:\n");
> seq_printf(m, "\tpath: %s\n",
> - guc_fw->guc_fw_path);
> + guc_fw->uc_fw_path);
> seq_printf(m, "\tfetch: %s\n",
> - intel_guc_fw_status_repr(guc_fw-
> >guc_fw_fetch_status));
> + intel_uc_fw_status_repr(guc_fw->fetch_status));
> seq_printf(m, "\tload: %s\n",
> - intel_guc_fw_status_repr(guc_fw-
> >guc_fw_load_status));
> + intel_uc_fw_status_repr(guc_fw->load_status));
> seq_printf(m, "\tversion wanted: %d.%d\n",
> - guc_fw->guc_fw_major_wanted, guc_fw-
> >guc_fw_minor_wanted);
> + guc_fw->major_ver_wanted, guc_fw->minor_ver_wanted);
> seq_printf(m, "\tversion found: %d.%d\n",
> - guc_fw->guc_fw_major_found, guc_fw-
> >guc_fw_minor_found);
> + guc_fw->major_ver_found, guc_fw->minor_ver_found);
> seq_printf(m, "\theader: offset is %d; size = %d\n",
> guc_fw->header_offset, guc_fw->header_size);
> seq_printf(m, "\tuCode: offset is %d; size = %d\n",
> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
> b/drivers/gpu/drm/i915/i915_guc_submission.c
> index 43358e1..4b92943 100644
> --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> @@ -1072,7 +1072,7 @@ int intel_guc_suspend(struct drm_device *dev)
> struct i915_gem_context *ctx;
> u32 data[3];
>
> - if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
> + if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS)
> return 0;
>
> ctx = dev_priv->kernel_context;
> @@ -1098,7 +1098,7 @@ int intel_guc_resume(struct drm_device *dev)
> struct i915_gem_context *ctx;
> u32 data[3];
>
> - if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
> + if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS)
> return 0;
>
> ctx = dev_priv->kernel_context;
> diff --git a/drivers/gpu/drm/i915/intel_guc.h
> b/drivers/gpu/drm/i915/intel_guc.h
> index b1ba869..b134a41 100644
> --- a/drivers/gpu/drm/i915/intel_guc.h
> +++ b/drivers/gpu/drm/i915/intel_guc.h
> @@ -91,29 +91,29 @@ struct i915_guc_client {
> uint64_t submissions[I915_NUM_ENGINES];
> };
>
> -enum intel_guc_fw_status {
> - GUC_FIRMWARE_FAIL = -1,
> - GUC_FIRMWARE_NONE = 0,
> - GUC_FIRMWARE_PENDING,
> - GUC_FIRMWARE_SUCCESS
> +enum intel_uc_fw_status {
> + UC_FIRMWARE_FAIL = -1,
> + UC_FIRMWARE_NONE = 0,
> + UC_FIRMWARE_PENDING,
> + UC_FIRMWARE_SUCCESS
> };
>
> /*
> * This structure encapsulates all the data needed during the
> process
> * of fetching, caching, and loading the firmware image into the
> GuC.
> */
> -struct intel_guc_fw {
> - struct drm_device * guc_dev;
> - const char * guc_fw_path;
> - size_t guc_fw_size;
> - struct drm_i915_gem_object * guc_fw_obj;
> - enum intel_guc_fw_status guc_fw_fetch_status;
> - enum intel_guc_fw_status guc_fw_load_status;
> -
> - uint16_t guc_fw_major_wanted;
> - uint16_t guc_fw_minor_wanted;
> - uint16_t guc_fw_major_found;
> - uint16_t guc_fw_minor_found;
> +struct intel_uc_fw {
> + struct drm_device *uc_dev;
> + const char *uc_fw_path;
> + size_t uc_fw_size;
> + struct drm_i915_gem_object *uc_fw_obj;
> + enum intel_uc_fw_status fetch_status;
> + enum intel_uc_fw_status load_status;
> +
> + uint16_t major_ver_wanted;
> + uint16_t minor_ver_wanted;
> + uint16_t major_ver_found;
> + uint16_t minor_ver_found;
>
> uint32_t header_size;
> uint32_t header_offset;
> @@ -124,7 +124,7 @@ struct intel_guc_fw {
> };
>
> struct intel_guc {
> - struct intel_guc_fw guc_fw;
> + struct intel_uc_fw guc_fw;
> uint32_t log_flags;
> struct i915_vma *log_vma;
>
> @@ -152,9 +152,10 @@ struct intel_guc {
> extern void intel_guc_init(struct drm_device *dev);
> extern int intel_guc_setup(struct drm_device *dev);
> extern void intel_guc_fini(struct drm_device *dev);
> -extern const char *intel_guc_fw_status_repr(enum intel_guc_fw_status
> status);
> +extern const char *intel_uc_fw_status_repr(enum intel_uc_fw_status
> status);
> extern int intel_guc_suspend(struct drm_device *dev);
> extern int intel_guc_resume(struct drm_device *dev);
> +void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw
> *uc_fw);
>
> /* i915_guc_submission.c */
> int i915_guc_submission_init(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
> b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 7ace96b..493295d 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -81,16 +81,16 @@ MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
> MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
>
> /* User-friendly representation of an enum */
> -const char *intel_guc_fw_status_repr(enum intel_guc_fw_status
> status)
> +const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status)
> {
> switch (status) {
> - case GUC_FIRMWARE_FAIL:
> + case UC_FIRMWARE_FAIL:
> return "FAIL";
> - case GUC_FIRMWARE_NONE:
> + case UC_FIRMWARE_NONE:
> return "NONE";
> - case GUC_FIRMWARE_PENDING:
> + case UC_FIRMWARE_PENDING:
> return "PENDING";
> - case GUC_FIRMWARE_SUCCESS:
> + case UC_FIRMWARE_SUCCESS:
> return "SUCCESS";
> default:
> return "UNKNOWN!";
> @@ -274,7 +274,7 @@ static inline bool guc_ucode_response(struct
> drm_i915_private *dev_priv,
> static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
> struct i915_vma *vma)
> {
> - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> unsigned long offset;
> struct sg_table *sg = vma->pages;
> u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT];
> @@ -346,18 +346,18 @@ static u32 guc_wopcm_size(struct
> drm_i915_private *dev_priv)
> */
> static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
> {
> - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> struct drm_device *dev = &dev_priv->drm;
> struct i915_vma *vma;
> int ret;
>
> - ret = i915_gem_object_set_to_gtt_domain(guc_fw->guc_fw_obj,
> false);
> + ret = i915_gem_object_set_to_gtt_domain(guc_fw->uc_fw_obj,
> false);
> if (ret) {
> DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
> return ret;
> }
>
> - vma = i915_gem_object_ggtt_pin(guc_fw->guc_fw_obj, NULL, 0,
> 0, 0);
> + vma = i915_gem_object_ggtt_pin(guc_fw->uc_fw_obj, NULL, 0,
> 0, 0);
> if (IS_ERR(vma)) {
> DRM_DEBUG_DRIVER("pin failed %d\n",
> (int)PTR_ERR(vma));
> return PTR_ERR(vma);
> @@ -448,14 +448,14 @@ static int guc_hw_reset(struct drm_i915_private
> *dev_priv)
> int intel_guc_setup(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
> - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> - const char *fw_path = guc_fw->guc_fw_path;
> + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> + const char *fw_path = guc_fw->uc_fw_path;
> int retries, ret, err;
>
> DRM_DEBUG_DRIVER("GuC fw status: path %s, fetch %s, load
> %s\n",
> fw_path,
> - intel_guc_fw_status_repr(guc_fw-
> >guc_fw_fetch_status),
> - intel_guc_fw_status_repr(guc_fw-
> >guc_fw_load_status));
> + intel_uc_fw_status_repr(guc_fw->fetch_status),
> + intel_uc_fw_status_repr(guc_fw->load_status));
>
> /* Loading forbidden, or no firmware to load? */
> if (!i915.enable_guc_loading) {
> @@ -473,21 +473,21 @@ int intel_guc_setup(struct drm_device *dev)
> }
>
> /* Fetch failed, or already fetched but failed to load? */
> - if (guc_fw->guc_fw_fetch_status != GUC_FIRMWARE_SUCCESS) {
> + if (guc_fw->fetch_status != UC_FIRMWARE_SUCCESS) {
> err = -EIO;
> goto fail;
> - } else if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_FAIL)
> {
> + } else if (guc_fw->load_status == UC_FIRMWARE_FAIL) {
> err = -ENOEXEC;
> goto fail;
> }
>
> guc_interrupts_release(dev_priv);
>
> - guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
> + guc_fw->load_status = UC_FIRMWARE_PENDING;
>
> DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
> - intel_guc_fw_status_repr(guc_fw-
> >guc_fw_fetch_status),
> - intel_guc_fw_status_repr(guc_fw-
> >guc_fw_load_status));
> + intel_uc_fw_status_repr(guc_fw->fetch_status),
> + intel_uc_fw_status_repr(guc_fw->load_status));
>
> err = i915_guc_submission_init(dev_priv);
> if (err)
> @@ -519,11 +519,11 @@ int intel_guc_setup(struct drm_device *dev)
> "retry %d more time(s)\n", err, retries);
> }
>
> - guc_fw->guc_fw_load_status = GUC_FIRMWARE_SUCCESS;
> + guc_fw->load_status = UC_FIRMWARE_SUCCESS;
>
> DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
> - intel_guc_fw_status_repr(guc_fw-
> >guc_fw_fetch_status),
> - intel_guc_fw_status_repr(guc_fw-
> >guc_fw_load_status));
> + intel_uc_fw_status_repr(guc_fw->fetch_status),
> + intel_uc_fw_status_repr(guc_fw->load_status));
>
> if (i915.enable_guc_submission) {
> err = i915_guc_submission_enable(dev_priv);
> @@ -535,8 +535,8 @@ int intel_guc_setup(struct drm_device *dev)
> return 0;
>
> fail:
> - if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_PENDING)
> - guc_fw->guc_fw_load_status = GUC_FIRMWARE_FAIL;
> + if (guc_fw->load_status == UC_FIRMWARE_PENDING)
> + guc_fw->load_status = UC_FIRMWARE_FAIL;
>
> guc_interrupts_release(dev_priv);
> i915_guc_submission_disable(dev_priv);
> @@ -581,7 +581,7 @@ fail:
> return ret;
> }
>
> -static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw
> *guc_fw)
> +void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw
> *uc_fw)
> {
> struct pci_dev *pdev = dev->pdev;
> struct drm_i915_gem_object *obj;
> @@ -590,17 +590,17 @@ static void guc_fw_fetch(struct drm_device
> *dev, struct intel_guc_fw *guc_fw)
> size_t size;
> int err;
>
> - DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch
> status %s\n",
> - intel_guc_fw_status_repr(guc_fw-
> >guc_fw_fetch_status));
> + DRM_DEBUG_DRIVER("before requesting firmware: uC fw fetch
> status %s\n",
> + intel_uc_fw_status_repr(uc_fw->fetch_status));
>
> - err = request_firmware(&fw, guc_fw->guc_fw_path, &pdev-
> >dev);
> + err = request_firmware(&fw, uc_fw->uc_fw_path, &pdev->dev);
> if (err)
> goto fail;
> if (!fw)
> goto fail;
>
> - DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n",
> - guc_fw->guc_fw_path, fw);
> + DRM_DEBUG_DRIVER("fetch uC fw from %s succeeded, fw %p\n",
> + uc_fw->uc_fw_path, fw);
>
> /* Check the size of the blob before examining buffer
> contents */
> if (fw->size < sizeof(struct guc_css_header)) {
> @@ -611,36 +611,36 @@ static void guc_fw_fetch(struct drm_device
> *dev, struct intel_guc_fw *guc_fw)
> css = (struct guc_css_header *)fw->data;
>
> /* Firmware bits always start from header */
> - guc_fw->header_offset = 0;
> - guc_fw->header_size = (css->header_size_dw - css-
> >modulus_size_dw -
> + uc_fw->header_offset = 0;
> + uc_fw->header_size = (css->header_size_dw - css-
> >modulus_size_dw -
> css->key_size_dw - css->exponent_size_dw) *
> sizeof(u32);
>
> - if (guc_fw->header_size != sizeof(struct guc_css_header)) {
> + if (uc_fw->header_size != sizeof(struct guc_css_header)) {
> DRM_NOTE("CSS header definition mismatch\n");
> goto fail;
> }
>
> /* then, uCode */
> - guc_fw->ucode_offset = guc_fw->header_offset + guc_fw-
> >header_size;
> - guc_fw->ucode_size = (css->size_dw - css->header_size_dw) *
> sizeof(u32);
> + uc_fw->ucode_offset = uc_fw->header_offset + uc_fw-
> >header_size;
> + uc_fw->ucode_size = (css->size_dw - css->header_size_dw) *
> sizeof(u32);
>
> /* now RSA */
> if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) {
> DRM_NOTE("RSA key size is bad\n");
> goto fail;
> }
> - guc_fw->rsa_offset = guc_fw->ucode_offset + guc_fw-
> >ucode_size;
> - guc_fw->rsa_size = css->key_size_dw * sizeof(u32);
> + uc_fw->rsa_offset = uc_fw->ucode_offset + uc_fw->ucode_size;
> + uc_fw->rsa_size = css->key_size_dw * sizeof(u32);
>
> /* At least, it should have header, uCode and RSA. Size of
> all three. */
> - size = guc_fw->header_size + guc_fw->ucode_size + guc_fw-
> >rsa_size;
> + size = uc_fw->header_size + uc_fw->ucode_size + uc_fw-
> >rsa_size;
> if (fw->size < size) {
> DRM_NOTE("Missing firmware components\n");
> goto fail;
> }
>
> /* Header and uCode will be loaded to WOPCM. Size of the
> two. */
> - size = guc_fw->header_size + guc_fw->ucode_size;
> + size = uc_fw->header_size + uc_fw->ucode_size;
> if (size > guc_wopcm_size(to_i915(dev))) {
> DRM_NOTE("Firmware is too large to fit in WOPCM\n");
> goto fail;
> @@ -652,21 +652,21 @@ static void guc_fw_fetch(struct drm_device
> *dev, struct intel_guc_fw *guc_fw)
> * TWO bytes each (i.e. u16), although all pointers and
> offsets are defined
> * in terms of bytes (u8).
> */
> - guc_fw->guc_fw_major_found = css->guc_sw_version >> 16;
> - guc_fw->guc_fw_minor_found = css->guc_sw_version & 0xFFFF;
> -
> - if (guc_fw->guc_fw_major_found != guc_fw-
> >guc_fw_major_wanted ||
> - guc_fw->guc_fw_minor_found < guc_fw-
> >guc_fw_minor_wanted) {
> - DRM_NOTE("GuC firmware version %d.%d, required
> %d.%d\n",
> - guc_fw->guc_fw_major_found, guc_fw-
> >guc_fw_minor_found,
> - guc_fw->guc_fw_major_wanted, guc_fw-
> >guc_fw_minor_wanted);
> + uc_fw->major_ver_found = css->guc_sw_version >> 16;
> + uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
> +
> + if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
> + uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) {
> + DRM_NOTE("uC firmware version %d.%d, required
> %d.%d\n",
> + uc_fw->major_ver_found, uc_fw-
> >minor_ver_found,
> + uc_fw->major_ver_wanted, uc_fw-
> >minor_ver_wanted);
> err = -ENOEXEC;
> goto fail;
> }
>
> DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum
> %d.%d)\n",
> - guc_fw->guc_fw_major_found, guc_fw-
> >guc_fw_minor_found,
> - guc_fw->guc_fw_major_wanted, guc_fw-
> >guc_fw_minor_wanted);
> + uc_fw->major_ver_found, uc_fw-
> >minor_ver_found,
> + uc_fw->major_ver_wanted, uc_fw-
> >minor_ver_wanted);
>
> mutex_lock(&dev->struct_mutex);
> obj = i915_gem_object_create_from_data(dev, fw->data, fw-
> >size);
> @@ -676,31 +676,31 @@ static void guc_fw_fetch(struct drm_device
> *dev, struct intel_guc_fw *guc_fw)
> goto fail;
> }
>
> - guc_fw->guc_fw_obj = obj;
> - guc_fw->guc_fw_size = fw->size;
> + uc_fw->uc_fw_obj = obj;
> + uc_fw->uc_fw_size = fw->size;
>
> - DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n",
> - guc_fw->guc_fw_obj);
> + DRM_DEBUG_DRIVER("uC fw fetch status SUCCESS, obj %p\n",
> + uc_fw->uc_fw_obj);
>
> release_firmware(fw);
> - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_SUCCESS;
> + uc_fw->fetch_status = UC_FIRMWARE_SUCCESS;
> return;
>
> fail:
> - DRM_WARN("Failed to fetch valid GuC firmware from %s (error
> %d)\n",
> - guc_fw->guc_fw_path, err);
> - DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p,
> obj %p\n",
> - err, fw, guc_fw->guc_fw_obj);
> + DRM_WARN("Failed to fetch valid uC firmware from %s (error
> %d)\n",
> + uc_fw->uc_fw_path, err);
> + DRM_DEBUG_DRIVER("uC fw fetch status FAIL; err %d, fw %p,
> obj %p\n",
> + err, fw, uc_fw->uc_fw_obj);
>
> mutex_lock(&dev->struct_mutex);
> - obj = guc_fw->guc_fw_obj;
> + obj = uc_fw->uc_fw_obj;
> if (obj)
> i915_gem_object_put(obj);
> - guc_fw->guc_fw_obj = NULL;
> + uc_fw->uc_fw_obj = NULL;
> mutex_unlock(&dev->struct_mutex);
>
> release_firmware(fw); /* OK even if fw is
> NULL */
> - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
> + uc_fw->fetch_status = UC_FIRMWARE_FAIL;
> }
>
> /**
> @@ -715,7 +715,7 @@ fail:
> void intel_guc_init(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
> - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> const char *fw_path;
>
> /* A negative value means "use platform default" */
> @@ -728,24 +728,24 @@ void intel_guc_init(struct drm_device *dev)
> fw_path = NULL;
> } else if (IS_SKYLAKE(dev)) {
> fw_path = I915_SKL_GUC_UCODE;
> - guc_fw->guc_fw_major_wanted = SKL_FW_MAJOR;
> - guc_fw->guc_fw_minor_wanted = SKL_FW_MINOR;
> + guc_fw->major_ver_wanted = SKL_FW_MAJOR;
> + guc_fw->minor_ver_wanted = SKL_FW_MINOR;
> } else if (IS_BROXTON(dev)) {
> fw_path = I915_BXT_GUC_UCODE;
> - guc_fw->guc_fw_major_wanted = BXT_FW_MAJOR;
> - guc_fw->guc_fw_minor_wanted = BXT_FW_MINOR;
> + guc_fw->major_ver_wanted = BXT_FW_MAJOR;
> + guc_fw->minor_ver_wanted = BXT_FW_MINOR;
> } else if (IS_KABYLAKE(dev)) {
> fw_path = I915_KBL_GUC_UCODE;
> - guc_fw->guc_fw_major_wanted = KBL_FW_MAJOR;
> - guc_fw->guc_fw_minor_wanted = KBL_FW_MINOR;
> + guc_fw->major_ver_wanted = KBL_FW_MAJOR;
> + guc_fw->minor_ver_wanted = KBL_FW_MINOR;
> } else {
> fw_path = ""; /* unknown device */
> }
>
> - guc_fw->guc_dev = dev;
> - guc_fw->guc_fw_path = fw_path;
> - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
> - guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE;
> + guc_fw->uc_dev = dev;
> + guc_fw->uc_fw_path = fw_path;
> + guc_fw->fetch_status = UC_FIRMWARE_NONE;
> + guc_fw->load_status = UC_FIRMWARE_NONE;
>
> /* Early (and silent) return if GuC loading is disabled */
> if (!i915.enable_guc_loading)
> @@ -755,9 +755,9 @@ void intel_guc_init(struct drm_device *dev)
> if (*fw_path == '\0')
> return;
>
> - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING;
> + guc_fw->fetch_status = UC_FIRMWARE_PENDING;
> DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n",
> fw_path);
> - guc_fw_fetch(dev, guc_fw);
> + intel_uc_fw_fetch(dev, guc_fw);
> /* status must now be FAIL or SUCCESS */
> }
>
> @@ -768,17 +768,17 @@ void intel_guc_init(struct drm_device *dev)
> void intel_guc_fini(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
> - struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
>
> mutex_lock(&dev->struct_mutex);
> guc_interrupts_release(dev_priv);
> i915_guc_submission_disable(dev_priv);
> i915_guc_submission_fini(dev_priv);
>
> - if (guc_fw->guc_fw_obj)
> - i915_gem_object_put(guc_fw->guc_fw_obj);
> - guc_fw->guc_fw_obj = NULL;
> + if (guc_fw->uc_fw_obj)
> + i915_gem_object_put(guc_fw->uc_fw_obj);
> + guc_fw->uc_fw_obj = NULL;
> mutex_unlock(&dev->struct_mutex);
>
> - guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
> + guc_fw->fetch_status = UC_FIRMWARE_NONE;
> }
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH 2/8] drm/i915/huc: Unified css_header struct for GuC and HuC
2016-10-03 18:42 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa
2016-10-03 18:42 ` [PATCH 1/8] drm/i915/guc: Make the GuC fw loading helper functions general Anusha Srivatsa
@ 2016-10-03 18:42 ` Anusha Srivatsa
2016-10-13 15:45 ` Jeff McGee
2016-10-24 21:42 ` Carlos Santa
2016-10-03 18:42 ` [PATCH 3/8] drm/i915/huc: Add HuC fw loading support Anusha Srivatsa
` (7 subsequent siblings)
9 siblings, 2 replies; 35+ messages in thread
From: Anusha Srivatsa @ 2016-10-03 18:42 UTC (permalink / raw)
To: intel-gfx
From: Peter Antoine <peter.antoine@intel.com>
HuC firmware css header has almost exactly same definition as GuC
firmware except for the sw_version. Also, add a new member fw_type
into intel_uc_fw to indicate what kind of fw it is. So, the loader
will pull right sw_version from header.
v2: rebased on-top of drm-intel-nightly
v3: rebased on-top of drm-intel-nightly (again).
v4: rebased + spaces.
v7: rebased.
v8: rebased.
Tested-by: Xiang Haihao <haihao.xiang@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
---
drivers/gpu/drm/i915/intel_guc.h | 4 ++++
drivers/gpu/drm/i915/intel_guc_fwif.h | 16 ++++++++++---
drivers/gpu/drm/i915/intel_guc_loader.c | 41 ++++++++++++++++++++++-----------
3 files changed, 45 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index b134a41..812e4ca 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -98,6 +98,9 @@ enum intel_uc_fw_status {
UC_FIRMWARE_SUCCESS
};
+#define UC_FW_TYPE_GUC 0
+#define UC_FW_TYPE_HUC 1
+
/*
* This structure encapsulates all the data needed during the process
* of fetching, caching, and loading the firmware image into the GuC.
@@ -115,6 +118,7 @@ struct intel_uc_fw {
uint16_t major_ver_found;
uint16_t minor_ver_found;
+ uint32_t fw_type;
uint32_t header_size;
uint32_t header_offset;
uint32_t rsa_size;
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index e40db2d..b38b6b4 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -154,7 +154,7 @@
* The GuC firmware layout looks like this:
*
* +-------------------------------+
- * | guc_css_header |
+ * | uc_css_header |
* | |
* | contains major/minor version |
* +-------------------------------+
@@ -181,9 +181,16 @@
* 3. Length info of each component can be found in header, in dwords.
* 4. Modulus and exponent key are not required by driver. They may not appear
* in fw. So driver will load a truncated firmware in this case.
+ *
+ * HuC firmware layout is same as GuC firmware.
+ *
+ * HuC firmware css header is different. However, the only difference is where
+ * the version information is saved. The uc_css_header is unified to support
+ * both. Driver should get HuC version from uc_css_header.huc_sw_version, while
+ * uc_css_header.guc_sw_version for GuC.
*/
-struct guc_css_header {
+struct uc_css_header {
uint32_t module_type;
/* header_size includes all non-uCode bits, including css_header, rsa
* key, modulus key and exponent data. */
@@ -214,7 +221,10 @@ struct guc_css_header {
char username[8];
char buildnumber[12];
- uint32_t device_id;
+ union {
+ uint32_t device_id;
+ uint32_t huc_sw_version;
+ };
uint32_t guc_sw_version;
uint32_t prod_preprod_fw;
uint32_t reserved[12];
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 493295d..0b863a1 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -586,7 +586,7 @@ void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw)
struct pci_dev *pdev = dev->pdev;
struct drm_i915_gem_object *obj;
const struct firmware *fw;
- struct guc_css_header *css;
+ struct uc_css_header *css;
size_t size;
int err;
@@ -603,19 +603,19 @@ void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw)
uc_fw->uc_fw_path, fw);
/* Check the size of the blob before examining buffer contents */
- if (fw->size < sizeof(struct guc_css_header)) {
+ if (fw->size < sizeof(struct uc_css_header)) {
DRM_NOTE("Firmware header is missing\n");
goto fail;
}
- css = (struct guc_css_header *)fw->data;
+ css = (struct uc_css_header *)fw->data;
/* Firmware bits always start from header */
uc_fw->header_offset = 0;
uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
- if (uc_fw->header_size != sizeof(struct guc_css_header)) {
+ if (uc_fw->header_size != sizeof(struct uc_css_header)) {
DRM_NOTE("CSS header definition mismatch\n");
goto fail;
}
@@ -639,21 +639,36 @@ void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw)
goto fail;
}
- /* Header and uCode will be loaded to WOPCM. Size of the two. */
- size = uc_fw->header_size + uc_fw->ucode_size;
- if (size > guc_wopcm_size(to_i915(dev))) {
- DRM_NOTE("Firmware is too large to fit in WOPCM\n");
- goto fail;
- }
-
/*
* The GuC firmware image has the version number embedded at a well-known
* offset within the firmware blob; note that major / minor version are
* TWO bytes each (i.e. u16), although all pointers and offsets are defined
* in terms of bytes (u8).
*/
- uc_fw->major_ver_found = css->guc_sw_version >> 16;
- uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
+ switch (uc_fw->fw_type) {
+ case UC_FW_TYPE_GUC:
+ /* Header and uCode will be loaded to WOPCM. Size of the two. */
+ size = uc_fw->header_size + uc_fw->ucode_size;
+
+ /* Top 32k of WOPCM is reserved (8K stack + 24k RC6 context). */
+ if (size > guc_wopcm_size(to_i915(dev))) {
+ DRM_ERROR("Firmware is too large to fit in WOPCM\n");
+ goto fail;
+ }
+ uc_fw->major_ver_found = css->guc_sw_version >> 16;
+ uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
+ break;
+
+ case UC_FW_TYPE_HUC:
+ uc_fw->major_ver_found = css->huc_sw_version >> 16;
+ uc_fw->minor_ver_found = css->huc_sw_version & 0xFFFF;
+ break;
+
+ default:
+ DRM_ERROR("Unknown firmware type %d\n", uc_fw->fw_type);
+ err = -ENOEXEC;
+ goto fail;
+ }
if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) {
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 35+ messages in thread* Re: [PATCH 2/8] drm/i915/huc: Unified css_header struct for GuC and HuC
2016-10-03 18:42 ` [PATCH 2/8] drm/i915/huc: Unified css_header struct for GuC and HuC Anusha Srivatsa
@ 2016-10-13 15:45 ` Jeff McGee
2016-10-14 4:24 ` Jeff McGee
2016-10-24 21:42 ` Carlos Santa
1 sibling, 1 reply; 35+ messages in thread
From: Jeff McGee @ 2016-10-13 15:45 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
On Mon, Oct 03, 2016 at 11:42:56AM -0700, Anusha Srivatsa wrote:
> From: Peter Antoine <peter.antoine@intel.com>
>
> HuC firmware css header has almost exactly same definition as GuC
> firmware except for the sw_version. Also, add a new member fw_type
> into intel_uc_fw to indicate what kind of fw it is. So, the loader
> will pull right sw_version from header.
>
> v2: rebased on-top of drm-intel-nightly
> v3: rebased on-top of drm-intel-nightly (again).
> v4: rebased + spaces.
> v7: rebased.
> v8: rebased.
>
> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
> ---
> drivers/gpu/drm/i915/intel_guc.h | 4 ++++
> drivers/gpu/drm/i915/intel_guc_fwif.h | 16 ++++++++++---
> drivers/gpu/drm/i915/intel_guc_loader.c | 41 ++++++++++++++++++++++-----------
> 3 files changed, 45 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
> index b134a41..812e4ca 100644
> --- a/drivers/gpu/drm/i915/intel_guc.h
> +++ b/drivers/gpu/drm/i915/intel_guc.h
> @@ -98,6 +98,9 @@ enum intel_uc_fw_status {
> UC_FIRMWARE_SUCCESS
> };
>
> +#define UC_FW_TYPE_GUC 0
> +#define UC_FW_TYPE_HUC 1
> +
> /*
> * This structure encapsulates all the data needed during the process
> * of fetching, caching, and loading the firmware image into the GuC.
> @@ -115,6 +118,7 @@ struct intel_uc_fw {
> uint16_t major_ver_found;
> uint16_t minor_ver_found;
>
> + uint32_t fw_type;
> uint32_t header_size;
> uint32_t header_offset;
> uint32_t rsa_size;
> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
> index e40db2d..b38b6b4 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> @@ -154,7 +154,7 @@
> * The GuC firmware layout looks like this:
> *
> * +-------------------------------+
> - * | guc_css_header |
> + * | uc_css_header |
> * | |
> * | contains major/minor version |
> * +-------------------------------+
> @@ -181,9 +181,16 @@
> * 3. Length info of each component can be found in header, in dwords.
> * 4. Modulus and exponent key are not required by driver. They may not appear
> * in fw. So driver will load a truncated firmware in this case.
> + *
> + * HuC firmware layout is same as GuC firmware.
> + *
> + * HuC firmware css header is different. However, the only difference is where
> + * the version information is saved. The uc_css_header is unified to support
> + * both. Driver should get HuC version from uc_css_header.huc_sw_version, while
> + * uc_css_header.guc_sw_version for GuC.
> */
>
> -struct guc_css_header {
> +struct uc_css_header {
> uint32_t module_type;
> /* header_size includes all non-uCode bits, including css_header, rsa
> * key, modulus key and exponent data. */
> @@ -214,7 +221,10 @@ struct guc_css_header {
>
> char username[8];
> char buildnumber[12];
> - uint32_t device_id;
> + union {
> + uint32_t device_id;
> + uint32_t huc_sw_version;
> + };
> uint32_t guc_sw_version;
> uint32_t prod_preprod_fw;
> uint32_t reserved[12];
I propose renaming the device_id field in this union to
'guc_client_branch_version'. GuC uses this position to store a client
version and branch version. I'm not sure where the 'device_id' term came
from. We don't reference this currently but may need to in the future
so might as well name it properly. At the very least we should probably
make it guc_device_id, to help indicate that it applies to guc fw only.
In that same vein, can we make guc_sw_version into a union as below to
reinforce the difference to huc?
union {
uint32_t guc_sw_version;
uint32_t huc_reserved;
};
Jeff
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 493295d..0b863a1 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -586,7 +586,7 @@ void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw)
> struct pci_dev *pdev = dev->pdev;
> struct drm_i915_gem_object *obj;
> const struct firmware *fw;
> - struct guc_css_header *css;
> + struct uc_css_header *css;
> size_t size;
> int err;
>
> @@ -603,19 +603,19 @@ void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw)
> uc_fw->uc_fw_path, fw);
>
> /* Check the size of the blob before examining buffer contents */
> - if (fw->size < sizeof(struct guc_css_header)) {
> + if (fw->size < sizeof(struct uc_css_header)) {
> DRM_NOTE("Firmware header is missing\n");
> goto fail;
> }
>
> - css = (struct guc_css_header *)fw->data;
> + css = (struct uc_css_header *)fw->data;
>
> /* Firmware bits always start from header */
> uc_fw->header_offset = 0;
> uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
> css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
>
> - if (uc_fw->header_size != sizeof(struct guc_css_header)) {
> + if (uc_fw->header_size != sizeof(struct uc_css_header)) {
> DRM_NOTE("CSS header definition mismatch\n");
> goto fail;
> }
> @@ -639,21 +639,36 @@ void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw)
> goto fail;
> }
>
> - /* Header and uCode will be loaded to WOPCM. Size of the two. */
> - size = uc_fw->header_size + uc_fw->ucode_size;
> - if (size > guc_wopcm_size(to_i915(dev))) {
> - DRM_NOTE("Firmware is too large to fit in WOPCM\n");
> - goto fail;
> - }
> -
> /*
> * The GuC firmware image has the version number embedded at a well-known
> * offset within the firmware blob; note that major / minor version are
> * TWO bytes each (i.e. u16), although all pointers and offsets are defined
> * in terms of bytes (u8).
> */
> - uc_fw->major_ver_found = css->guc_sw_version >> 16;
> - uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
> + switch (uc_fw->fw_type) {
> + case UC_FW_TYPE_GUC:
> + /* Header and uCode will be loaded to WOPCM. Size of the two. */
> + size = uc_fw->header_size + uc_fw->ucode_size;
> +
> + /* Top 32k of WOPCM is reserved (8K stack + 24k RC6 context). */
> + if (size > guc_wopcm_size(to_i915(dev))) {
> + DRM_ERROR("Firmware is too large to fit in WOPCM\n");
> + goto fail;
> + }
> + uc_fw->major_ver_found = css->guc_sw_version >> 16;
> + uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
> + break;
> +
> + case UC_FW_TYPE_HUC:
> + uc_fw->major_ver_found = css->huc_sw_version >> 16;
> + uc_fw->minor_ver_found = css->huc_sw_version & 0xFFFF;
> + break;
> +
> + default:
> + DRM_ERROR("Unknown firmware type %d\n", uc_fw->fw_type);
> + err = -ENOEXEC;
> + goto fail;
> + }
>
> if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
> uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) {
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [PATCH 2/8] drm/i915/huc: Unified css_header struct for GuC and HuC
2016-10-13 15:45 ` Jeff McGee
@ 2016-10-14 4:24 ` Jeff McGee
0 siblings, 0 replies; 35+ messages in thread
From: Jeff McGee @ 2016-10-14 4:24 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
On Thu, Oct 13, 2016 at 08:45:45AM -0700, Jeff McGee wrote:
> On Mon, Oct 03, 2016 at 11:42:56AM -0700, Anusha Srivatsa wrote:
> > From: Peter Antoine <peter.antoine@intel.com>
> >
> > HuC firmware css header has almost exactly same definition as GuC
> > firmware except for the sw_version. Also, add a new member fw_type
> > into intel_uc_fw to indicate what kind of fw it is. So, the loader
> > will pull right sw_version from header.
> >
> > v2: rebased on-top of drm-intel-nightly
> > v3: rebased on-top of drm-intel-nightly (again).
> > v4: rebased + spaces.
> > v7: rebased.
> > v8: rebased.
> >
> > Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > Signed-off-by: Alex Dai <yu.dai@intel.com>
> > Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> > Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_guc.h | 4 ++++
> > drivers/gpu/drm/i915/intel_guc_fwif.h | 16 ++++++++++---
> > drivers/gpu/drm/i915/intel_guc_loader.c | 41 ++++++++++++++++++++++-----------
> > 3 files changed, 45 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
> > index b134a41..812e4ca 100644
> > --- a/drivers/gpu/drm/i915/intel_guc.h
> > +++ b/drivers/gpu/drm/i915/intel_guc.h
> > @@ -98,6 +98,9 @@ enum intel_uc_fw_status {
> > UC_FIRMWARE_SUCCESS
> > };
> >
> > +#define UC_FW_TYPE_GUC 0
> > +#define UC_FW_TYPE_HUC 1
> > +
> > /*
> > * This structure encapsulates all the data needed during the process
> > * of fetching, caching, and loading the firmware image into the GuC.
> > @@ -115,6 +118,7 @@ struct intel_uc_fw {
> > uint16_t major_ver_found;
> > uint16_t minor_ver_found;
> >
> > + uint32_t fw_type;
> > uint32_t header_size;
> > uint32_t header_offset;
> > uint32_t rsa_size;
> > diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
> > index e40db2d..b38b6b4 100644
> > --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> > +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> > @@ -154,7 +154,7 @@
> > * The GuC firmware layout looks like this:
> > *
> > * +-------------------------------+
> > - * | guc_css_header |
> > + * | uc_css_header |
> > * | |
> > * | contains major/minor version |
> > * +-------------------------------+
> > @@ -181,9 +181,16 @@
> > * 3. Length info of each component can be found in header, in dwords.
> > * 4. Modulus and exponent key are not required by driver. They may not appear
> > * in fw. So driver will load a truncated firmware in this case.
> > + *
> > + * HuC firmware layout is same as GuC firmware.
> > + *
> > + * HuC firmware css header is different. However, the only difference is where
> > + * the version information is saved. The uc_css_header is unified to support
> > + * both. Driver should get HuC version from uc_css_header.huc_sw_version, while
> > + * uc_css_header.guc_sw_version for GuC.
> > */
> >
> > -struct guc_css_header {
> > +struct uc_css_header {
> > uint32_t module_type;
> > /* header_size includes all non-uCode bits, including css_header, rsa
> > * key, modulus key and exponent data. */
> > @@ -214,7 +221,10 @@ struct guc_css_header {
> >
> > char username[8];
> > char buildnumber[12];
> > - uint32_t device_id;
> > + union {
> > + uint32_t device_id;
> > + uint32_t huc_sw_version;
> > + };
> > uint32_t guc_sw_version;
> > uint32_t prod_preprod_fw;
> > uint32_t reserved[12];
>
> I propose renaming the device_id field in this union to
> 'guc_client_branch_version'. GuC uses this position to store a client
> version and branch version. I'm not sure where the 'device_id' term came
> from. We don't reference this currently but may need to in the future
> so might as well name it properly. At the very least we should probably
> make it guc_device_id, to help indicate that it applies to guc fw only.
>
> In that same vein, can we make guc_sw_version into a union as below to
> reinforce the difference to huc?
>
> union {
> uint32_t guc_sw_version;
> uint32_t huc_reserved;
> };
>
> Jeff
>
One correction. The branch version is considered the "major" and the
client version the "minor", so the better name for this field is
'guc_branch_client_version'.
> > diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> > index 493295d..0b863a1 100644
> > --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> > +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> > @@ -586,7 +586,7 @@ void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw)
> > struct pci_dev *pdev = dev->pdev;
> > struct drm_i915_gem_object *obj;
> > const struct firmware *fw;
> > - struct guc_css_header *css;
> > + struct uc_css_header *css;
> > size_t size;
> > int err;
> >
> > @@ -603,19 +603,19 @@ void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw)
> > uc_fw->uc_fw_path, fw);
> >
> > /* Check the size of the blob before examining buffer contents */
> > - if (fw->size < sizeof(struct guc_css_header)) {
> > + if (fw->size < sizeof(struct uc_css_header)) {
> > DRM_NOTE("Firmware header is missing\n");
> > goto fail;
> > }
> >
> > - css = (struct guc_css_header *)fw->data;
> > + css = (struct uc_css_header *)fw->data;
> >
> > /* Firmware bits always start from header */
> > uc_fw->header_offset = 0;
> > uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
> > css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
> >
> > - if (uc_fw->header_size != sizeof(struct guc_css_header)) {
> > + if (uc_fw->header_size != sizeof(struct uc_css_header)) {
> > DRM_NOTE("CSS header definition mismatch\n");
> > goto fail;
> > }
> > @@ -639,21 +639,36 @@ void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw)
> > goto fail;
> > }
> >
> > - /* Header and uCode will be loaded to WOPCM. Size of the two. */
> > - size = uc_fw->header_size + uc_fw->ucode_size;
> > - if (size > guc_wopcm_size(to_i915(dev))) {
> > - DRM_NOTE("Firmware is too large to fit in WOPCM\n");
> > - goto fail;
> > - }
> > -
> > /*
> > * The GuC firmware image has the version number embedded at a well-known
> > * offset within the firmware blob; note that major / minor version are
> > * TWO bytes each (i.e. u16), although all pointers and offsets are defined
> > * in terms of bytes (u8).
> > */
> > - uc_fw->major_ver_found = css->guc_sw_version >> 16;
> > - uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
> > + switch (uc_fw->fw_type) {
> > + case UC_FW_TYPE_GUC:
> > + /* Header and uCode will be loaded to WOPCM. Size of the two. */
> > + size = uc_fw->header_size + uc_fw->ucode_size;
> > +
> > + /* Top 32k of WOPCM is reserved (8K stack + 24k RC6 context). */
> > + if (size > guc_wopcm_size(to_i915(dev))) {
> > + DRM_ERROR("Firmware is too large to fit in WOPCM\n");
> > + goto fail;
> > + }
> > + uc_fw->major_ver_found = css->guc_sw_version >> 16;
> > + uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
> > + break;
> > +
> > + case UC_FW_TYPE_HUC:
> > + uc_fw->major_ver_found = css->huc_sw_version >> 16;
> > + uc_fw->minor_ver_found = css->huc_sw_version & 0xFFFF;
> > + break;
> > +
> > + default:
> > + DRM_ERROR("Unknown firmware type %d\n", uc_fw->fw_type);
> > + err = -ENOEXEC;
> > + goto fail;
> > + }
> >
> > if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
> > uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) {
> > --
> > 2.7.4
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 2/8] drm/i915/huc: Unified css_header struct for GuC and HuC
2016-10-03 18:42 ` [PATCH 2/8] drm/i915/huc: Unified css_header struct for GuC and HuC Anusha Srivatsa
2016-10-13 15:45 ` Jeff McGee
@ 2016-10-24 21:42 ` Carlos Santa
1 sibling, 0 replies; 35+ messages in thread
From: Carlos Santa @ 2016-10-24 21:42 UTC (permalink / raw)
To: Anusha Srivatsa, intel-gfx
On Mon, 2016-10-03 at 11:42 -0700, Anusha Srivatsa wrote:
> From: Peter Antoine <peter.antoine@intel.com>
>
> HuC firmware css header has almost exactly same definition as GuC
> firmware except for the sw_version. Also, add a new member fw_type
> into intel_uc_fw to indicate what kind of fw it is. So, the loader
> will pull right sw_version from header.
>
> v2: rebased on-top of drm-intel-nightly
> v3: rebased on-top of drm-intel-nightly (again).
> v4: rebased + spaces.
> v7: rebased.
> v8: rebased.
>
> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
> ---
> drivers/gpu/drm/i915/intel_guc.h | 4 ++++
> drivers/gpu/drm/i915/intel_guc_fwif.h | 16 ++++++++++---
> drivers/gpu/drm/i915/intel_guc_loader.c | 41 ++++++++++++++++++++++-
> ----------
> 3 files changed, 45 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_guc.h
> b/drivers/gpu/drm/i915/intel_guc.h
> index b134a41..812e4ca 100644
> --- a/drivers/gpu/drm/i915/intel_guc.h
> +++ b/drivers/gpu/drm/i915/intel_guc.h
> @@ -98,6 +98,9 @@ enum intel_uc_fw_status {
> UC_FIRMWARE_SUCCESS
> };
>
> +#define UC_FW_TYPE_GUC 0
> +#define UC_FW_TYPE_HUC 1
> +
This can be changed to an enum as suggested earlier by Rodrigo.
> /*
> * This structure encapsulates all the data needed during the
> process
> * of fetching, caching, and loading the firmware image into the
> GuC.
> @@ -115,6 +118,7 @@ struct intel_uc_fw {
> uint16_t major_ver_found;
> uint16_t minor_ver_found;
>
> + uint32_t fw_type;
Maybe a comment can be added to this variable to explicitly describe
what it is ("GuC/HuC FW")?
Carlos
> uint32_t header_size;
> uint32_t header_offset;
> uint32_t rsa_size;
> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
> b/drivers/gpu/drm/i915/intel_guc_fwif.h
> index e40db2d..b38b6b4 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> @@ -154,7 +154,7 @@
> * The GuC firmware layout looks like this:
> *
> * +-------------------------------+
> - * | guc_css_header |
> + * | uc_css_header |
> * | |
> * | contains major/minor version |
> * +-------------------------------+
> @@ -181,9 +181,16 @@
> * 3. Length info of each component can be found in header, in
> dwords.
> * 4. Modulus and exponent key are not required by driver. They may
> not appear
> * in fw. So driver will load a truncated firmware in this case.
> + *
> + * HuC firmware layout is same as GuC firmware.
> + *
> + * HuC firmware css header is different. However, the only
> difference is where
> + * the version information is saved. The uc_css_header is unified to
> support
> + * both. Driver should get HuC version from
> uc_css_header.huc_sw_version, while
> + * uc_css_header.guc_sw_version for GuC.
> */
>
> -struct guc_css_header {
> +struct uc_css_header {
> uint32_t module_type;
> /* header_size includes all non-uCode bits, including
> css_header, rsa
> * key, modulus key and exponent data. */
> @@ -214,7 +221,10 @@ struct guc_css_header {
>
> char username[8];
> char buildnumber[12];
> - uint32_t device_id;
> + union {
> + uint32_t device_id;
> + uint32_t huc_sw_version;
> + };
> uint32_t guc_sw_version;
> uint32_t prod_preprod_fw;
> uint32_t reserved[12];
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
> b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 493295d..0b863a1 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -586,7 +586,7 @@ void intel_uc_fw_fetch(struct drm_device *dev,
> struct intel_uc_fw *uc_fw)
> struct pci_dev *pdev = dev->pdev;
> struct drm_i915_gem_object *obj;
> const struct firmware *fw;
> - struct guc_css_header *css;
> + struct uc_css_header *css;
> size_t size;
> int err;
>
> @@ -603,19 +603,19 @@ void intel_uc_fw_fetch(struct drm_device *dev,
> struct intel_uc_fw *uc_fw)
> uc_fw->uc_fw_path, fw);
>
> /* Check the size of the blob before examining buffer
> contents */
> - if (fw->size < sizeof(struct guc_css_header)) {
> + if (fw->size < sizeof(struct uc_css_header)) {
> DRM_NOTE("Firmware header is missing\n");
> goto fail;
> }
>
> - css = (struct guc_css_header *)fw->data;
> + css = (struct uc_css_header *)fw->data;
>
> /* Firmware bits always start from header */
> uc_fw->header_offset = 0;
> uc_fw->header_size = (css->header_size_dw - css-
> >modulus_size_dw -
> css->key_size_dw - css->exponent_size_dw) *
> sizeof(u32);
>
> - if (uc_fw->header_size != sizeof(struct guc_css_header)) {
> + if (uc_fw->header_size != sizeof(struct uc_css_header)) {
> DRM_NOTE("CSS header definition mismatch\n");
> goto fail;
> }
> @@ -639,21 +639,36 @@ void intel_uc_fw_fetch(struct drm_device *dev,
> struct intel_uc_fw *uc_fw)
> goto fail;
> }
>
> - /* Header and uCode will be loaded to WOPCM. Size of the
> two. */
> - size = uc_fw->header_size + uc_fw->ucode_size;
> - if (size > guc_wopcm_size(to_i915(dev))) {
> - DRM_NOTE("Firmware is too large to fit in WOPCM\n");
> - goto fail;
> - }
> -
> /*
> * The GuC firmware image has the version number embedded at
> a well-known
> * offset within the firmware blob; note that major / minor
> version are
> * TWO bytes each (i.e. u16), although all pointers and
> offsets are defined
> * in terms of bytes (u8).
> */
> - uc_fw->major_ver_found = css->guc_sw_version >> 16;
> - uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
> + switch (uc_fw->fw_type) {
> + case UC_FW_TYPE_GUC:
> + /* Header and uCode will be loaded to WOPCM. Size of
> the two. */
> + size = uc_fw->header_size + uc_fw->ucode_size;
> +
> + /* Top 32k of WOPCM is reserved (8K stack + 24k RC6
> context). */
> + if (size > guc_wopcm_size(to_i915(dev))) {
> + DRM_ERROR("Firmware is too large to fit in
> WOPCM\n");
> + goto fail;
> + }
> + uc_fw->major_ver_found = css->guc_sw_version >> 16;
> + uc_fw->minor_ver_found = css->guc_sw_version &
> 0xFFFF;
> + break;
> +
> + case UC_FW_TYPE_HUC:
> + uc_fw->major_ver_found = css->huc_sw_version >> 16;
> + uc_fw->minor_ver_found = css->huc_sw_version &
> 0xFFFF;
> + break;
> +
> + default:
> + DRM_ERROR("Unknown firmware type %d\n", uc_fw-
> >fw_type);
> + err = -ENOEXEC;
> + goto fail;
> + }
>
> if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
> uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) {
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH 3/8] drm/i915/huc: Add HuC fw loading support
2016-10-03 18:42 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa
2016-10-03 18:42 ` [PATCH 1/8] drm/i915/guc: Make the GuC fw loading helper functions general Anusha Srivatsa
2016-10-03 18:42 ` [PATCH 2/8] drm/i915/huc: Unified css_header struct for GuC and HuC Anusha Srivatsa
@ 2016-10-03 18:42 ` Anusha Srivatsa
2016-10-13 17:42 ` Jeff McGee
2016-10-03 18:42 ` [PATCH 4/8] drm/i915/huc: Add debugfs for HuC loading status check Anusha Srivatsa
` (6 subsequent siblings)
9 siblings, 1 reply; 35+ messages in thread
From: Anusha Srivatsa @ 2016-10-03 18:42 UTC (permalink / raw)
To: intel-gfx
From: Peter Antoine <peter.antoine@intel.com>
The HuC loading process is similar to GuC. The intel_uc_fw_fetch()
is used for both cases.
HuC loading needs to be before GuC loading. The WOPCM setting must
be done early before loading any of them.
v2: rebased on-top of drm-intel-nightly.
removed if(HAS_GUC()) before the guc call. (D.Gordon)
update huc_version number of format.
v3: rebased to drm-intel-nightly, changed the file name format to
match the one in the huc package.
Changed dev->dev_private to to_i915()
v4: moved function back to where it was.
change wait_for_atomic to wait_for.
v5: rebased + comment changes.
v7: rebased.
v8: rebased.
Tested-by: Xiang Haihao <haihao.xiang@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_drv.c | 3 +
drivers/gpu/drm/i915/i915_drv.h | 3 +
drivers/gpu/drm/i915/i915_guc_reg.h | 3 +
drivers/gpu/drm/i915/intel_guc.h | 1 +
drivers/gpu/drm/i915/intel_guc_loader.c | 6 +-
drivers/gpu/drm/i915/intel_huc.h | 44 ++++++
drivers/gpu/drm/i915/intel_huc_loader.c | 268 ++++++++++++++++++++++++++++++++
8 files changed, 327 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_huc.h
create mode 100644 drivers/gpu/drm/i915/intel_huc_loader.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index e6fe004..6e99c51 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -53,6 +53,7 @@ i915-y += i915_cmd_parser.o \
# general-purpose microcontroller (GuC) support
i915-y += intel_guc_loader.o \
+ intel_huc_loader.o \
i915_guc_submission.o
# autogenerated null render state
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 31b2b63..7af7bd6 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -613,6 +613,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
* working irqs for e.g. gmbus and dp aux transfers. */
intel_modeset_init(dev);
+ intel_huc_init(dev);
intel_guc_init(dev);
ret = i915_gem_init(dev);
@@ -638,6 +639,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
cleanup_gem:
i915_gem_fini(dev);
cleanup_irq:
+ intel_huc_fini(dev);
intel_guc_fini(dev);
drm_irq_uninstall(dev);
intel_teardown_gmbus(dev);
@@ -1315,6 +1317,7 @@ void i915_driver_unload(struct drm_device *dev)
/* Flush any outstanding unpin_work. */
drain_workqueue(dev_priv->wq);
+ intel_huc_fini(dev);
intel_guc_fini(dev);
i915_gem_fini(dev);
intel_fbc_cleanup_cfb(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e0cb71c..625aa92 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -55,6 +55,7 @@
#include "intel_bios.h"
#include "intel_dpll_mgr.h"
#include "intel_guc.h"
+#include "intel_huc.h"
#include "intel_lrc.h"
#include "intel_ringbuffer.h"
@@ -1766,6 +1767,7 @@ struct drm_i915_private {
struct intel_gvt gvt;
+ struct intel_huc huc;
struct intel_guc guc;
struct intel_csr csr;
@@ -2822,6 +2824,7 @@ struct drm_i915_cmd_table {
#define HAS_GUC(dev) (INTEL_INFO(dev)->has_guc)
#define HAS_GUC_UCODE(dev) (HAS_GUC(dev))
#define HAS_GUC_SCHED(dev) (HAS_GUC(dev))
+#define HAS_HUC_UCODE(dev) (HAS_GUC(dev))
#define HAS_RESOURCE_STREAMER(dev) (INTEL_INFO(dev)->has_resource_streamer)
diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h
index a47e1e4..64e942a 100644
--- a/drivers/gpu/drm/i915/i915_guc_reg.h
+++ b/drivers/gpu/drm/i915/i915_guc_reg.h
@@ -61,9 +61,12 @@
#define DMA_ADDRESS_SPACE_GTT (8 << 16)
#define DMA_COPY_SIZE _MMIO(0xc310)
#define DMA_CTRL _MMIO(0xc314)
+#define HUC_UKERNEL (1<<9)
#define UOS_MOVE (1<<4)
#define START_DMA (1<<0)
#define DMA_GUC_WOPCM_OFFSET _MMIO(0xc340)
+#define HUC_LOADING_AGENT_VCR (0<<1)
+#define HUC_LOADING_AGENT_GUC (1<<1)
#define GUC_WOPCM_OFFSET_VALUE 0x80000 /* 512KB */
#define GUC_MAX_IDLE_COUNT _MMIO(0xC3E4)
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 812e4ca..af76ffe 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -160,6 +160,7 @@ extern const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status);
extern int intel_guc_suspend(struct drm_device *dev);
extern int intel_guc_resume(struct drm_device *dev);
void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw);
+u32 guc_wopcm_size(struct drm_i915_private *dev_priv);
/* i915_guc_submission.c */
int i915_guc_submission_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 0b863a1..0d214b4 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -305,7 +305,8 @@ static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
/* Finally start the DMA */
- I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
+ I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA) |
+ _MASKED_BIT_DISABLE(HUC_UKERNEL));
/*
* Wait for the DMA to complete & the GuC to start up.
@@ -330,7 +331,7 @@ static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
return ret;
}
-static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
+u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
{
u32 wopcm_size = GUC_WOPCM_TOP;
@@ -508,6 +509,7 @@ int intel_guc_setup(struct drm_device *dev)
if (err)
goto fail;
+ intel_huc_load(dev);
err = guc_ucode_xfer(dev_priv);
if (!err)
break;
diff --git a/drivers/gpu/drm/i915/intel_huc.h b/drivers/gpu/drm/i915/intel_huc.h
new file mode 100644
index 0000000..946caa7
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_huc.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright © 2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+#ifndef _INTEL_HUC_H_
+#define _INTEL_HUC_H_
+
+#include "intel_guc.h"
+
+#define HUC_STATUS2 _MMIO(0xD3B0)
+#define HUC_FW_VERIFIED (1<<7)
+
+struct intel_huc {
+ /* Generic uC firmware management */
+ struct intel_uc_fw huc_fw;
+
+ /* HuC-specific additions */
+};
+
+extern void intel_huc_init(struct drm_device *dev);
+extern int intel_huc_load(struct drm_device *dev);
+extern void intel_huc_auth(struct drm_device *dev);
+extern void intel_huc_fini(struct drm_device *dev);
+
+#endif
diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
new file mode 100644
index 0000000..1aaff67
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_huc_loader.c
@@ -0,0 +1,268 @@
+/*
+ * Copyright © 2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+#include <linux/firmware.h>
+#include "i915_drv.h"
+#include "intel_huc.h"
+
+/**
+ * DOC: HuC Firmware
+ *
+ * Motivation:
+ * GEN9 introduces a new dedicated firmware for usage in media HEVC (High
+ * Efficiency Video Coding) operations. Userspace can use the firmware
+ * capabilities by adding HuC specific commands to batch buffers.
+ *
+ * Implementation:
+ * On supported platforms, i915's job is to load the firmware stored on the
+ * file system and assist with authentication. It is up to userspace to
+ * detect the presence of HuC support on a platform, on their own.
+ * For debugging, i915 provides a debugfs file, i915_huc_load_status_info
+ * which displays the firmware load status.
+ *
+ * The same firmware loader is used as the GuC. Firmware * binary is fetched by
+ * the loader asynchronously from the driver init process. However, the actual
+ * loading to HW is deferred until GEM initialization is done.
+ *
+ * Note that HuC firmware loading must be done before GuC loading.
+ */
+
+#define I915_SKL_HUC_UCODE "i915/skl_huc_ver01_07_1398.bin"
+MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
+
+/**
+ * intel_huc_load_ucode() - DMA's the firmware
+ * @dev: the drm device
+ *
+ * This function takes the gem object containing the firmware, sets up the DMA
+ * engine MMIO, triggers the DMA operation and waits for it to finish.
+ *
+ * Transfer the firmware image to RAM for execution by the microcontroller.
+ *
+ * Return: 0 on success, non-zero on failure
+ */
+
+static int huc_ucode_xfer(struct drm_i915_private *dev_priv)
+{
+ struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
+ struct i915_vma *vma;
+ unsigned long offset = 0;
+ u32 size;
+ int ret;
+
+ ret = i915_gem_object_set_to_gtt_domain(huc_fw->uc_fw_obj, false);
+ if (ret) {
+ DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
+ return ret;
+ }
+
+ vma = i915_gem_object_ggtt_pin(huc_fw->uc_fw_obj, NULL, 0, 0, 0);
+ if (IS_ERR(vma)) {
+ DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
+ return PTR_ERR(vma);
+ }
+
+ /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
+ I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
+
+ WARN_ON(!mutex_is_locked(&dev_priv->drm.struct_mutex));
+ intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+
+ /* init WOPCM */
+ I915_WRITE(GUC_WOPCM_SIZE, guc_wopcm_size(dev_priv));
+ I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE |
+ HUC_LOADING_AGENT_GUC);
+
+ /* Set the source address for the uCode */
+ offset = i915_ggtt_offset(vma) + huc_fw->header_offset;
+ I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
+ I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
+
+ /* Hardware doesn't look at destination address for HuC. Set it to 0,
+ * but still program the correct address space.
+ */
+ I915_WRITE(DMA_ADDR_1_LOW, 0);
+ I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
+
+ size = huc_fw->header_size + huc_fw->ucode_size;
+ I915_WRITE(DMA_COPY_SIZE, size);
+
+ /* Start the DMA */
+ I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA));
+
+ /* Wait for DMA to finish */
+ ret = wait_for((I915_READ(DMA_CTRL) & START_DMA) == 0, 100);
+
+ DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret);
+
+ intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+ /*
+ * We keep the object pages for reuse during resume. But we can unpin it
+ * now that DMA has completed, so it doesn't continue to take up space.
+ */
+ i915_vma_unpin(vma);
+
+ return ret;
+}
+
+/**
+ * intel_huc_init() - initiate HuC firmware loading request
+ * @dev: the drm device
+ *
+ * Called early during driver load, but after GEM is initialised. The loading
+ * will continue only when driver explicitly specify firmware name and version.
+ * All other cases are considered as UC_FIRMWARE_NONE either because HW is not
+ * capable or driver yet support it. And there will be no error message for
+ * UC_FIRMWARE_NONE cases.
+ *
+ * The DMA-copying to HW is done later when intel_huc_ucode_load() is called.
+ */
+void intel_huc_init(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_huc *huc = &dev_priv->huc;
+ struct intel_uc_fw *huc_fw = &huc->huc_fw;
+ const char *fw_path = NULL;
+
+ huc_fw->uc_dev = dev;
+ huc_fw->uc_fw_path = NULL;
+ huc_fw->fetch_status = UC_FIRMWARE_NONE;
+ huc_fw->load_status = UC_FIRMWARE_NONE;
+ huc_fw->fw_type = UC_FW_TYPE_HUC;
+
+ if (!HAS_HUC_UCODE(dev_priv))
+ return;
+
+ if (IS_SKYLAKE(dev_priv)) {
+ fw_path = I915_SKL_HUC_UCODE;
+ huc_fw->major_ver_wanted = 1;
+ huc_fw->minor_ver_wanted = 7;
+ }
+
+ if (fw_path == NULL)
+ return;
+
+ huc_fw->uc_fw_path = fw_path;
+ huc_fw->fetch_status = UC_FIRMWARE_PENDING;
+
+ DRM_DEBUG_DRIVER("HuC firmware pending, path %s\n", fw_path);
+
+ intel_uc_fw_fetch(dev, huc_fw);
+}
+
+/**
+ * intel_huc_load() - load HuC uCode to device
+ * @dev: the drm device
+ *
+ * Called from gem_init_hw() during driver loading and also after a GPU reset.
+ * Be note that HuC loading must be done before GuC loading.
+ *
+ * The firmware image should have already been fetched into memory by the
+ * earlier call to intel_huc_ucode_init(), so here we need only check that
+ * is succeeded, and then transfer the image to the h/w.
+ *
+ * Return: non-zero code on error
+ */
+int intel_huc_load(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
+ int err;
+
+ if (huc_fw->fetch_status == UC_FIRMWARE_NONE)
+ return 0;
+
+ DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n",
+ huc_fw->uc_fw_path,
+ intel_uc_fw_status_repr(huc_fw->fetch_status),
+ intel_uc_fw_status_repr(huc_fw->load_status));
+
+ if (huc_fw->fetch_status == UC_FIRMWARE_SUCCESS &&
+ huc_fw->load_status == UC_FIRMWARE_FAIL)
+ return -ENOEXEC;
+
+ huc_fw->load_status = UC_FIRMWARE_PENDING;
+
+ switch (huc_fw->fetch_status) {
+ case UC_FIRMWARE_FAIL:
+ /* something went wrong :( */
+ err = -EIO;
+ goto fail;
+
+ case UC_FIRMWARE_NONE:
+ case UC_FIRMWARE_PENDING:
+ default:
+ /* "can't happen" */
+ WARN_ONCE(1, "HuC fw %s invalid fetch_status %s [%d]\n",
+ huc_fw->uc_fw_path,
+ intel_uc_fw_status_repr(huc_fw->fetch_status),
+ huc_fw->fetch_status);
+ err = -ENXIO;
+ goto fail;
+
+ case UC_FIRMWARE_SUCCESS:
+ break;
+ }
+
+ err = huc_ucode_xfer(dev_priv);
+ if (err)
+ goto fail;
+
+ huc_fw->load_status = UC_FIRMWARE_SUCCESS;
+
+ DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n",
+ huc_fw->uc_fw_path,
+ intel_uc_fw_status_repr(huc_fw->fetch_status),
+ intel_uc_fw_status_repr(huc_fw->load_status));
+
+ return 0;
+
+fail:
+ if (huc_fw->load_status == UC_FIRMWARE_PENDING)
+ huc_fw->load_status = UC_FIRMWARE_FAIL;
+
+ DRM_ERROR("Failed to complete HuC uCode load with ret %d\n", err);
+
+ return err;
+}
+
+/**
+ * intel_huc_fini() - clean up resources allocated for HuC
+ * @dev: the drm device
+ *
+ * Cleans up by releasing the huc firmware GEM obj.
+ */
+void intel_huc_fini(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
+
+ mutex_lock(&dev->struct_mutex);
+ if (huc_fw->uc_fw_obj)
+ drm_gem_object_unreference(&huc_fw->uc_fw_obj->base);
+ huc_fw->uc_fw_obj = NULL;
+ mutex_unlock(&dev->struct_mutex);
+
+ huc_fw->fetch_status = UC_FIRMWARE_NONE;
+}
--
2.7.4
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^ permalink raw reply related [flat|nested] 35+ messages in thread* Re: [PATCH 3/8] drm/i915/huc: Add HuC fw loading support
2016-10-03 18:42 ` [PATCH 3/8] drm/i915/huc: Add HuC fw loading support Anusha Srivatsa
@ 2016-10-13 17:42 ` Jeff McGee
2016-10-13 20:54 ` Jeff McGee
0 siblings, 1 reply; 35+ messages in thread
From: Jeff McGee @ 2016-10-13 17:42 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
On Mon, Oct 03, 2016 at 11:42:57AM -0700, Anusha Srivatsa wrote:
> From: Peter Antoine <peter.antoine@intel.com>
>
> The HuC loading process is similar to GuC. The intel_uc_fw_fetch()
> is used for both cases.
>
> HuC loading needs to be before GuC loading. The WOPCM setting must
> be done early before loading any of them.
>
> v2: rebased on-top of drm-intel-nightly.
> removed if(HAS_GUC()) before the guc call. (D.Gordon)
> update huc_version number of format.
> v3: rebased to drm-intel-nightly, changed the file name format to
> match the one in the huc package.
> Changed dev->dev_private to to_i915()
> v4: moved function back to where it was.
> change wait_for_atomic to wait_for.
> v5: rebased + comment changes.
> v7: rebased.
> v8: rebased.
>
> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/i915_drv.c | 3 +
> drivers/gpu/drm/i915/i915_drv.h | 3 +
> drivers/gpu/drm/i915/i915_guc_reg.h | 3 +
> drivers/gpu/drm/i915/intel_guc.h | 1 +
> drivers/gpu/drm/i915/intel_guc_loader.c | 6 +-
> drivers/gpu/drm/i915/intel_huc.h | 44 ++++++
> drivers/gpu/drm/i915/intel_huc_loader.c | 268 ++++++++++++++++++++++++++++++++
> 8 files changed, 327 insertions(+), 2 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/intel_huc.h
> create mode 100644 drivers/gpu/drm/i915/intel_huc_loader.c
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index e6fe004..6e99c51 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -53,6 +53,7 @@ i915-y += i915_cmd_parser.o \
>
> # general-purpose microcontroller (GuC) support
> i915-y += intel_guc_loader.o \
> + intel_huc_loader.o \
> i915_guc_submission.o
>
> # autogenerated null render state
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 31b2b63..7af7bd6 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -613,6 +613,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
> * working irqs for e.g. gmbus and dp aux transfers. */
> intel_modeset_init(dev);
>
> + intel_huc_init(dev);
> intel_guc_init(dev);
>
> ret = i915_gem_init(dev);
> @@ -638,6 +639,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
> cleanup_gem:
> i915_gem_fini(dev);
> cleanup_irq:
> + intel_huc_fini(dev);
> intel_guc_fini(dev);
> drm_irq_uninstall(dev);
> intel_teardown_gmbus(dev);
> @@ -1315,6 +1317,7 @@ void i915_driver_unload(struct drm_device *dev)
> /* Flush any outstanding unpin_work. */
> drain_workqueue(dev_priv->wq);
>
> + intel_huc_fini(dev);
> intel_guc_fini(dev);
> i915_gem_fini(dev);
> intel_fbc_cleanup_cfb(dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index e0cb71c..625aa92 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -55,6 +55,7 @@
> #include "intel_bios.h"
> #include "intel_dpll_mgr.h"
> #include "intel_guc.h"
> +#include "intel_huc.h"
> #include "intel_lrc.h"
> #include "intel_ringbuffer.h"
>
> @@ -1766,6 +1767,7 @@ struct drm_i915_private {
>
> struct intel_gvt gvt;
>
> + struct intel_huc huc;
> struct intel_guc guc;
>
> struct intel_csr csr;
> @@ -2822,6 +2824,7 @@ struct drm_i915_cmd_table {
> #define HAS_GUC(dev) (INTEL_INFO(dev)->has_guc)
> #define HAS_GUC_UCODE(dev) (HAS_GUC(dev))
> #define HAS_GUC_SCHED(dev) (HAS_GUC(dev))
> +#define HAS_HUC_UCODE(dev) (HAS_GUC(dev))
>
> #define HAS_RESOURCE_STREAMER(dev) (INTEL_INFO(dev)->has_resource_streamer)
>
> diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h
> index a47e1e4..64e942a 100644
> --- a/drivers/gpu/drm/i915/i915_guc_reg.h
> +++ b/drivers/gpu/drm/i915/i915_guc_reg.h
> @@ -61,9 +61,12 @@
> #define DMA_ADDRESS_SPACE_GTT (8 << 16)
> #define DMA_COPY_SIZE _MMIO(0xc310)
> #define DMA_CTRL _MMIO(0xc314)
> +#define HUC_UKERNEL (1<<9)
> #define UOS_MOVE (1<<4)
> #define START_DMA (1<<0)
> #define DMA_GUC_WOPCM_OFFSET _MMIO(0xc340)
> +#define HUC_LOADING_AGENT_VCR (0<<1)
> +#define HUC_LOADING_AGENT_GUC (1<<1)
> #define GUC_WOPCM_OFFSET_VALUE 0x80000 /* 512KB */
> #define GUC_MAX_IDLE_COUNT _MMIO(0xC3E4)
>
> diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
> index 812e4ca..af76ffe 100644
> --- a/drivers/gpu/drm/i915/intel_guc.h
> +++ b/drivers/gpu/drm/i915/intel_guc.h
> @@ -160,6 +160,7 @@ extern const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status);
> extern int intel_guc_suspend(struct drm_device *dev);
> extern int intel_guc_resume(struct drm_device *dev);
> void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw);
> +u32 guc_wopcm_size(struct drm_i915_private *dev_priv);
>
> /* i915_guc_submission.c */
> int i915_guc_submission_init(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 0b863a1..0d214b4 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -305,7 +305,8 @@ static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
> I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
>
> /* Finally start the DMA */
> - I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
> + I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA) |
> + _MASKED_BIT_DISABLE(HUC_UKERNEL));
>
> /*
> * Wait for the DMA to complete & the GuC to start up.
> @@ -330,7 +331,7 @@ static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
> return ret;
> }
>
> -static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
> +u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
> {
> u32 wopcm_size = GUC_WOPCM_TOP;
>
> @@ -508,6 +509,7 @@ int intel_guc_setup(struct drm_device *dev)
> if (err)
> goto fail;
>
> + intel_huc_load(dev);
> err = guc_ucode_xfer(dev_priv);
> if (!err)
> break;
> diff --git a/drivers/gpu/drm/i915/intel_huc.h b/drivers/gpu/drm/i915/intel_huc.h
> new file mode 100644
> index 0000000..946caa7
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_huc.h
> @@ -0,0 +1,44 @@
> +/*
> + * Copyright © 2014 Intel Corporation
Should this be 2016?
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + *
> + */
> +#ifndef _INTEL_HUC_H_
> +#define _INTEL_HUC_H_
> +
> +#include "intel_guc.h"
> +
> +#define HUC_STATUS2 _MMIO(0xD3B0)
> +#define HUC_FW_VERIFIED (1<<7)
> +
> +struct intel_huc {
> + /* Generic uC firmware management */
> + struct intel_uc_fw huc_fw;
> +
> + /* HuC-specific additions */
> +};
> +
> +extern void intel_huc_init(struct drm_device *dev);
> +extern int intel_huc_load(struct drm_device *dev);
> +extern void intel_huc_auth(struct drm_device *dev);
> +extern void intel_huc_fini(struct drm_device *dev);
> +
> +#endif
> diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
> new file mode 100644
> index 0000000..1aaff67
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_huc_loader.c
> @@ -0,0 +1,268 @@
> +/*
> + * Copyright © 2014 Intel Corporation
Should this be 2016?
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + *
> + */
> +#include <linux/firmware.h>
> +#include "i915_drv.h"
> +#include "intel_huc.h"
> +
> +/**
> + * DOC: HuC Firmware
> + *
> + * Motivation:
> + * GEN9 introduces a new dedicated firmware for usage in media HEVC (High
> + * Efficiency Video Coding) operations. Userspace can use the firmware
> + * capabilities by adding HuC specific commands to batch buffers.
> + *
> + * Implementation:
> + * On supported platforms, i915's job is to load the firmware stored on the
> + * file system and assist with authentication. It is up to userspace to
> + * detect the presence of HuC support on a platform, on their own.
> + * For debugging, i915 provides a debugfs file, i915_huc_load_status_info
> + * which displays the firmware load status.
Above comment refers to features added in subsequent patches and is not
entirely accurate at that. So I would just remove this whole block. Less
commenting is better than misleading commenting.
> + *
> + * The same firmware loader is used as the GuC. Firmware * binary is fetched by
> + * the loader asynchronously from the driver init process. However, the actual
Remove * from "Firmware * binary". Loading is not asynchronous so remove this
statement.
> + * loading to HW is deferred until GEM initialization is done.
> + *
> + * Note that HuC firmware loading must be done before GuC loading.
> + */
> +
> +#define I915_SKL_HUC_UCODE "i915/skl_huc_ver01_07_1398.bin"
> +MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
Please update to use the new approach used by GuC for specifying
required version and constructing the file path. See intel_guc_loader.c.
HuC firmware versioning includes the build number after the minor so
some modification will be needed.
> +
> +/**
> + * intel_huc_load_ucode() - DMA's the firmware
> + * @dev: the drm device
Fix name and parameter
> + *
> + * This function takes the gem object containing the firmware, sets up the DMA
> + * engine MMIO, triggers the DMA operation and waits for it to finish.
> + *
> + * Transfer the firmware image to RAM for execution by the microcontroller.
> + *
> + * Return: 0 on success, non-zero on failure
> + */
> +
> +static int huc_ucode_xfer(struct drm_i915_private *dev_priv)
> +{
> + struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
> + struct i915_vma *vma;
> + unsigned long offset = 0;
> + u32 size;
> + int ret;
> +
> + ret = i915_gem_object_set_to_gtt_domain(huc_fw->uc_fw_obj, false);
> + if (ret) {
> + DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
> + return ret;
> + }
> +
> + vma = i915_gem_object_ggtt_pin(huc_fw->uc_fw_obj, NULL, 0, 0, 0);
> + if (IS_ERR(vma)) {
> + DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
> + return PTR_ERR(vma);
> + }
> +
> + /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
> + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
> +
> + WARN_ON(!mutex_is_locked(&dev_priv->drm.struct_mutex));
I don't see reason for this WARN_ON check. This function is called
in well defined paths that require locking way up the chain.
I think we can remove it.
> + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> +
> + /* init WOPCM */
> + I915_WRITE(GUC_WOPCM_SIZE, guc_wopcm_size(dev_priv));
> + I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE |
> + HUC_LOADING_AGENT_GUC);
> +
> + /* Set the source address for the uCode */
> + offset = i915_ggtt_offset(vma) + huc_fw->header_offset;
> + I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
> + I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
> +
> + /* Hardware doesn't look at destination address for HuC. Set it to 0,
> + * but still program the correct address space.
> + */
> + I915_WRITE(DMA_ADDR_1_LOW, 0);
> + I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
> +
> + size = huc_fw->header_size + huc_fw->ucode_size;
> + I915_WRITE(DMA_COPY_SIZE, size);
> +
> + /* Start the DMA */
> + I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA));
> +
> + /* Wait for DMA to finish */
> + ret = wait_for((I915_READ(DMA_CTRL) & START_DMA) == 0, 100);
> +
> + DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret);
> +
> + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> +
> + /*
> + * We keep the object pages for reuse during resume. But we can unpin it
> + * now that DMA has completed, so it doesn't continue to take up space.
> + */
> + i915_vma_unpin(vma);
> +
> + return ret;
> +}
> +
> +/**
> + * intel_huc_init() - initiate HuC firmware loading request
> + * @dev: the drm device
> + *
> + * Called early during driver load, but after GEM is initialised. The loading
> + * will continue only when driver explicitly specify firmware name and version.
> + * All other cases are considered as UC_FIRMWARE_NONE either because HW is not
> + * capable or driver yet support it. And there will be no error message for
> + * UC_FIRMWARE_NONE cases.
> + *
> + * The DMA-copying to HW is done later when intel_huc_ucode_load() is called.
intel_huc_ucode_load() should be intel_huc_load().
> + */
> +void intel_huc_init(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_huc *huc = &dev_priv->huc;
> + struct intel_uc_fw *huc_fw = &huc->huc_fw;
> + const char *fw_path = NULL;
> +
> + huc_fw->uc_dev = dev;
> + huc_fw->uc_fw_path = NULL;
> + huc_fw->fetch_status = UC_FIRMWARE_NONE;
> + huc_fw->load_status = UC_FIRMWARE_NONE;
> + huc_fw->fw_type = UC_FW_TYPE_HUC;
> +
> + if (!HAS_HUC_UCODE(dev_priv))
> + return;
> +
> + if (IS_SKYLAKE(dev_priv)) {
> + fw_path = I915_SKL_HUC_UCODE;
> + huc_fw->major_ver_wanted = 1;
> + huc_fw->minor_ver_wanted = 7;
> + }
> +
> + if (fw_path == NULL)
> + return;
> +
> + huc_fw->uc_fw_path = fw_path;
> + huc_fw->fetch_status = UC_FIRMWARE_PENDING;
> +
> + DRM_DEBUG_DRIVER("HuC firmware pending, path %s\n", fw_path);
> +
> + intel_uc_fw_fetch(dev, huc_fw);
> +}
> +
> +/**
> + * intel_huc_load() - load HuC uCode to device
> + * @dev: the drm device
> + *
> + * Called from gem_init_hw() during driver loading and also after a GPU reset.
> + * Be note that HuC loading must be done before GuC loading.
> + *
> + * The firmware image should have already been fetched into memory by the
> + * earlier call to intel_huc_ucode_init(), so here we need only check that
> + * is succeeded, and then transfer the image to the h/w.
> + *
> + * Return: non-zero code on error
> + */
> +int intel_huc_load(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
> + int err;
> +
> + if (huc_fw->fetch_status == UC_FIRMWARE_NONE)
> + return 0;
> +
> + DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n",
> + huc_fw->uc_fw_path,
> + intel_uc_fw_status_repr(huc_fw->fetch_status),
> + intel_uc_fw_status_repr(huc_fw->load_status));
> +
> + if (huc_fw->fetch_status == UC_FIRMWARE_SUCCESS &&
> + huc_fw->load_status == UC_FIRMWARE_FAIL)
> + return -ENOEXEC;
> +
> + huc_fw->load_status = UC_FIRMWARE_PENDING;
> +
> + switch (huc_fw->fetch_status) {
> + case UC_FIRMWARE_FAIL:
> + /* something went wrong :( */
> + err = -EIO;
> + goto fail;
> +
> + case UC_FIRMWARE_NONE:
> + case UC_FIRMWARE_PENDING:
> + default:
> + /* "can't happen" */
> + WARN_ONCE(1, "HuC fw %s invalid fetch_status %s [%d]\n",
> + huc_fw->uc_fw_path,
> + intel_uc_fw_status_repr(huc_fw->fetch_status),
> + huc_fw->fetch_status);
> + err = -ENXIO;
> + goto fail;
> +
> + case UC_FIRMWARE_SUCCESS:
> + break;
> + }
> +
> + err = huc_ucode_xfer(dev_priv);
> + if (err)
> + goto fail;
> +
> + huc_fw->load_status = UC_FIRMWARE_SUCCESS;
> +
> + DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n",
> + huc_fw->uc_fw_path,
> + intel_uc_fw_status_repr(huc_fw->fetch_status),
> + intel_uc_fw_status_repr(huc_fw->load_status));
> +
> + return 0;
> +
> +fail:
> + if (huc_fw->load_status == UC_FIRMWARE_PENDING)
> + huc_fw->load_status = UC_FIRMWARE_FAIL;
> +
> + DRM_ERROR("Failed to complete HuC uCode load with ret %d\n", err);
> +
> + return err;
> +}
> +
> +/**
> + * intel_huc_fini() - clean up resources allocated for HuC
> + * @dev: the drm device
> + *
> + * Cleans up by releasing the huc firmware GEM obj.
> + */
> +void intel_huc_fini(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
> +
> + mutex_lock(&dev->struct_mutex);
> + if (huc_fw->uc_fw_obj)
> + drm_gem_object_unreference(&huc_fw->uc_fw_obj->base);
These are now replaced with i915_gem_object_put(huc_fw->uc_fw_obj)
> + huc_fw->uc_fw_obj = NULL;
> + mutex_unlock(&dev->struct_mutex);
> +
> + huc_fw->fetch_status = UC_FIRMWARE_NONE;
> +}
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [PATCH 3/8] drm/i915/huc: Add HuC fw loading support
2016-10-13 17:42 ` Jeff McGee
@ 2016-10-13 20:54 ` Jeff McGee
2016-10-24 21:24 ` Carlos Santa
0 siblings, 1 reply; 35+ messages in thread
From: Jeff McGee @ 2016-10-13 20:54 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
On Thu, Oct 13, 2016 at 10:42:42AM -0700, Jeff McGee wrote:
> On Mon, Oct 03, 2016 at 11:42:57AM -0700, Anusha Srivatsa wrote:
> > From: Peter Antoine <peter.antoine@intel.com>
> >
> > The HuC loading process is similar to GuC. The intel_uc_fw_fetch()
> > is used for both cases.
> >
> > HuC loading needs to be before GuC loading. The WOPCM setting must
> > be done early before loading any of them.
> >
> > v2: rebased on-top of drm-intel-nightly.
> > removed if(HAS_GUC()) before the guc call. (D.Gordon)
> > update huc_version number of format.
> > v3: rebased to drm-intel-nightly, changed the file name format to
> > match the one in the huc package.
> > Changed dev->dev_private to to_i915()
> > v4: moved function back to where it was.
> > change wait_for_atomic to wait_for.
> > v5: rebased + comment changes.
> > v7: rebased.
> > v8: rebased.
> >
> > Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > Signed-off-by: Alex Dai <yu.dai@intel.com>
> > Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> > Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
> > ---
> > drivers/gpu/drm/i915/Makefile | 1 +
> > drivers/gpu/drm/i915/i915_drv.c | 3 +
> > drivers/gpu/drm/i915/i915_drv.h | 3 +
> > drivers/gpu/drm/i915/i915_guc_reg.h | 3 +
> > drivers/gpu/drm/i915/intel_guc.h | 1 +
> > drivers/gpu/drm/i915/intel_guc_loader.c | 6 +-
> > drivers/gpu/drm/i915/intel_huc.h | 44 ++++++
> > drivers/gpu/drm/i915/intel_huc_loader.c | 268 ++++++++++++++++++++++++++++++++
> > 8 files changed, 327 insertions(+), 2 deletions(-)
> > create mode 100644 drivers/gpu/drm/i915/intel_huc.h
> > create mode 100644 drivers/gpu/drm/i915/intel_huc_loader.c
> >
> > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> > index e6fe004..6e99c51 100644
> > --- a/drivers/gpu/drm/i915/Makefile
> > +++ b/drivers/gpu/drm/i915/Makefile
> > @@ -53,6 +53,7 @@ i915-y += i915_cmd_parser.o \
> >
> > # general-purpose microcontroller (GuC) support
> > i915-y += intel_guc_loader.o \
> > + intel_huc_loader.o \
> > i915_guc_submission.o
> >
> > # autogenerated null render state
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > index 31b2b63..7af7bd6 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -613,6 +613,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
> > * working irqs for e.g. gmbus and dp aux transfers. */
> > intel_modeset_init(dev);
> >
> > + intel_huc_init(dev);
> > intel_guc_init(dev);
> >
> > ret = i915_gem_init(dev);
> > @@ -638,6 +639,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
> > cleanup_gem:
> > i915_gem_fini(dev);
> > cleanup_irq:
> > + intel_huc_fini(dev);
> > intel_guc_fini(dev);
> > drm_irq_uninstall(dev);
> > intel_teardown_gmbus(dev);
> > @@ -1315,6 +1317,7 @@ void i915_driver_unload(struct drm_device *dev)
> > /* Flush any outstanding unpin_work. */
> > drain_workqueue(dev_priv->wq);
> >
> > + intel_huc_fini(dev);
> > intel_guc_fini(dev);
> > i915_gem_fini(dev);
> > intel_fbc_cleanup_cfb(dev_priv);
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index e0cb71c..625aa92 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -55,6 +55,7 @@
> > #include "intel_bios.h"
> > #include "intel_dpll_mgr.h"
> > #include "intel_guc.h"
> > +#include "intel_huc.h"
> > #include "intel_lrc.h"
> > #include "intel_ringbuffer.h"
> >
> > @@ -1766,6 +1767,7 @@ struct drm_i915_private {
> >
> > struct intel_gvt gvt;
> >
> > + struct intel_huc huc;
> > struct intel_guc guc;
> >
> > struct intel_csr csr;
> > @@ -2822,6 +2824,7 @@ struct drm_i915_cmd_table {
> > #define HAS_GUC(dev) (INTEL_INFO(dev)->has_guc)
> > #define HAS_GUC_UCODE(dev) (HAS_GUC(dev))
> > #define HAS_GUC_SCHED(dev) (HAS_GUC(dev))
> > +#define HAS_HUC_UCODE(dev) (HAS_GUC(dev))
> >
> > #define HAS_RESOURCE_STREAMER(dev) (INTEL_INFO(dev)->has_resource_streamer)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h
> > index a47e1e4..64e942a 100644
> > --- a/drivers/gpu/drm/i915/i915_guc_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_guc_reg.h
> > @@ -61,9 +61,12 @@
> > #define DMA_ADDRESS_SPACE_GTT (8 << 16)
> > #define DMA_COPY_SIZE _MMIO(0xc310)
> > #define DMA_CTRL _MMIO(0xc314)
> > +#define HUC_UKERNEL (1<<9)
> > #define UOS_MOVE (1<<4)
> > #define START_DMA (1<<0)
> > #define DMA_GUC_WOPCM_OFFSET _MMIO(0xc340)
> > +#define HUC_LOADING_AGENT_VCR (0<<1)
> > +#define HUC_LOADING_AGENT_GUC (1<<1)
> > #define GUC_WOPCM_OFFSET_VALUE 0x80000 /* 512KB */
> > #define GUC_MAX_IDLE_COUNT _MMIO(0xC3E4)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
> > index 812e4ca..af76ffe 100644
> > --- a/drivers/gpu/drm/i915/intel_guc.h
> > +++ b/drivers/gpu/drm/i915/intel_guc.h
> > @@ -160,6 +160,7 @@ extern const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status);
> > extern int intel_guc_suspend(struct drm_device *dev);
> > extern int intel_guc_resume(struct drm_device *dev);
> > void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw);
> > +u32 guc_wopcm_size(struct drm_i915_private *dev_priv);
> >
> > /* i915_guc_submission.c */
> > int i915_guc_submission_init(struct drm_i915_private *dev_priv);
> > diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> > index 0b863a1..0d214b4 100644
> > --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> > +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> > @@ -305,7 +305,8 @@ static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
> > I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
> >
> > /* Finally start the DMA */
> > - I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
> > + I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA) |
> > + _MASKED_BIT_DISABLE(HUC_UKERNEL));
> >
> > /*
> > * Wait for the DMA to complete & the GuC to start up.
> > @@ -330,7 +331,7 @@ static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
> > return ret;
> > }
> >
> > -static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
> > +u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
> > {
> > u32 wopcm_size = GUC_WOPCM_TOP;
> >
> > @@ -508,6 +509,7 @@ int intel_guc_setup(struct drm_device *dev)
> > if (err)
> > goto fail;
> >
> > + intel_huc_load(dev);
> > err = guc_ucode_xfer(dev_priv);
> > if (!err)
> > break;
> > diff --git a/drivers/gpu/drm/i915/intel_huc.h b/drivers/gpu/drm/i915/intel_huc.h
> > new file mode 100644
> > index 0000000..946caa7
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/intel_huc.h
> > @@ -0,0 +1,44 @@
> > +/*
> > + * Copyright © 2014 Intel Corporation
>
> Should this be 2016?
>
> > + *
> > + * Permission is hereby granted, free of charge, to any person obtaining a
> > + * copy of this software and associated documentation files (the "Software"),
> > + * to deal in the Software without restriction, including without limitation
> > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice (including the next
> > + * paragraph) shall be included in all copies or substantial portions of the
> > + * Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> > + * IN THE SOFTWARE.
> > + *
> > + */
> > +#ifndef _INTEL_HUC_H_
> > +#define _INTEL_HUC_H_
> > +
> > +#include "intel_guc.h"
> > +
> > +#define HUC_STATUS2 _MMIO(0xD3B0)
> > +#define HUC_FW_VERIFIED (1<<7)
> > +
> > +struct intel_huc {
> > + /* Generic uC firmware management */
> > + struct intel_uc_fw huc_fw;
> > +
> > + /* HuC-specific additions */
> > +};
> > +
> > +extern void intel_huc_init(struct drm_device *dev);
> > +extern int intel_huc_load(struct drm_device *dev);
> > +extern void intel_huc_auth(struct drm_device *dev);
> > +extern void intel_huc_fini(struct drm_device *dev);
These don't need extern. Please remove. Also intel_huc_auth comes in with
later patch in the series so would be better to drop from here.
> > +
> > +#endif
> > diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
> > new file mode 100644
> > index 0000000..1aaff67
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/intel_huc_loader.c
> > @@ -0,0 +1,268 @@
> > +/*
> > + * Copyright © 2014 Intel Corporation
>
> Should this be 2016?
>
> > + *
> > + * Permission is hereby granted, free of charge, to any person obtaining a
> > + * copy of this software and associated documentation files (the "Software"),
> > + * to deal in the Software without restriction, including without limitation
> > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice (including the next
> > + * paragraph) shall be included in all copies or substantial portions of the
> > + * Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> > + * IN THE SOFTWARE.
> > + *
> > + */
> > +#include <linux/firmware.h>
> > +#include "i915_drv.h"
> > +#include "intel_huc.h"
> > +
> > +/**
> > + * DOC: HuC Firmware
> > + *
> > + * Motivation:
> > + * GEN9 introduces a new dedicated firmware for usage in media HEVC (High
> > + * Efficiency Video Coding) operations. Userspace can use the firmware
> > + * capabilities by adding HuC specific commands to batch buffers.
> > + *
> > + * Implementation:
> > + * On supported platforms, i915's job is to load the firmware stored on the
> > + * file system and assist with authentication. It is up to userspace to
> > + * detect the presence of HuC support on a platform, on their own.
> > + * For debugging, i915 provides a debugfs file, i915_huc_load_status_info
> > + * which displays the firmware load status.
> Above comment refers to features added in subsequent patches and is not
> entirely accurate at that. So I would just remove this whole block. Less
> commenting is better than misleading commenting.
>
> > + *
> > + * The same firmware loader is used as the GuC. Firmware * binary is fetched by
> > + * the loader asynchronously from the driver init process. However, the actual
> Remove * from "Firmware * binary". Loading is not asynchronous so remove this
> statement.
>
> > + * loading to HW is deferred until GEM initialization is done.
> > + *
> > + * Note that HuC firmware loading must be done before GuC loading.
> > + */
> > +
> > +#define I915_SKL_HUC_UCODE "i915/skl_huc_ver01_07_1398.bin"
> > +MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
> Please update to use the new approach used by GuC for specifying
> required version and constructing the file path. See intel_guc_loader.c.
> HuC firmware versioning includes the build number after the minor so
> some modification will be needed.
>
> > +
> > +/**
> > + * intel_huc_load_ucode() - DMA's the firmware
> > + * @dev: the drm device
> Fix name and parameter
>
> > + *
> > + * This function takes the gem object containing the firmware, sets up the DMA
> > + * engine MMIO, triggers the DMA operation and waits for it to finish.
> > + *
> > + * Transfer the firmware image to RAM for execution by the microcontroller.
> > + *
> > + * Return: 0 on success, non-zero on failure
> > + */
> > +
> > +static int huc_ucode_xfer(struct drm_i915_private *dev_priv)
> > +{
> > + struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
> > + struct i915_vma *vma;
> > + unsigned long offset = 0;
> > + u32 size;
> > + int ret;
> > +
> > + ret = i915_gem_object_set_to_gtt_domain(huc_fw->uc_fw_obj, false);
> > + if (ret) {
> > + DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
> > + return ret;
> > + }
> > +
> > + vma = i915_gem_object_ggtt_pin(huc_fw->uc_fw_obj, NULL, 0, 0, 0);
> > + if (IS_ERR(vma)) {
> > + DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
> > + return PTR_ERR(vma);
> > + }
> > +
> > + /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
> > + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
> > +
> > + WARN_ON(!mutex_is_locked(&dev_priv->drm.struct_mutex));
> I don't see reason for this WARN_ON check. This function is called
> in well defined paths that require locking way up the chain.
> I think we can remove it.
>
> > + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> > +
> > + /* init WOPCM */
> > + I915_WRITE(GUC_WOPCM_SIZE, guc_wopcm_size(dev_priv));
> > + I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE |
> > + HUC_LOADING_AGENT_GUC);
> > +
> > + /* Set the source address for the uCode */
> > + offset = i915_ggtt_offset(vma) + huc_fw->header_offset;
> > + I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
> > + I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
> > +
> > + /* Hardware doesn't look at destination address for HuC. Set it to 0,
> > + * but still program the correct address space.
> > + */
> > + I915_WRITE(DMA_ADDR_1_LOW, 0);
> > + I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
> > +
> > + size = huc_fw->header_size + huc_fw->ucode_size;
> > + I915_WRITE(DMA_COPY_SIZE, size);
> > +
> > + /* Start the DMA */
> > + I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA));
> > +
> > + /* Wait for DMA to finish */
> > + ret = wait_for((I915_READ(DMA_CTRL) & START_DMA) == 0, 100);
> > +
> > + DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret);
> > +
> > + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> > +
> > + /*
> > + * We keep the object pages for reuse during resume. But we can unpin it
> > + * now that DMA has completed, so it doesn't continue to take up space.
> > + */
> > + i915_vma_unpin(vma);
> > +
> > + return ret;
> > +}
> > +
> > +/**
> > + * intel_huc_init() - initiate HuC firmware loading request
> > + * @dev: the drm device
> > + *
> > + * Called early during driver load, but after GEM is initialised. The loading
> > + * will continue only when driver explicitly specify firmware name and version.
> > + * All other cases are considered as UC_FIRMWARE_NONE either because HW is not
> > + * capable or driver yet support it. And there will be no error message for
> > + * UC_FIRMWARE_NONE cases.
> > + *
> > + * The DMA-copying to HW is done later when intel_huc_ucode_load() is called.
> intel_huc_ucode_load() should be intel_huc_load().
>
> > + */
> > +void intel_huc_init(struct drm_device *dev)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(dev);
> > + struct intel_huc *huc = &dev_priv->huc;
> > + struct intel_uc_fw *huc_fw = &huc->huc_fw;
> > + const char *fw_path = NULL;
> > +
> > + huc_fw->uc_dev = dev;
> > + huc_fw->uc_fw_path = NULL;
> > + huc_fw->fetch_status = UC_FIRMWARE_NONE;
> > + huc_fw->load_status = UC_FIRMWARE_NONE;
> > + huc_fw->fw_type = UC_FW_TYPE_HUC;
> > +
> > + if (!HAS_HUC_UCODE(dev_priv))
> > + return;
> > +
> > + if (IS_SKYLAKE(dev_priv)) {
> > + fw_path = I915_SKL_HUC_UCODE;
> > + huc_fw->major_ver_wanted = 1;
> > + huc_fw->minor_ver_wanted = 7;
> > + }
> > +
> > + if (fw_path == NULL)
> > + return;
> > +
> > + huc_fw->uc_fw_path = fw_path;
> > + huc_fw->fetch_status = UC_FIRMWARE_PENDING;
> > +
> > + DRM_DEBUG_DRIVER("HuC firmware pending, path %s\n", fw_path);
> > +
> > + intel_uc_fw_fetch(dev, huc_fw);
> > +}
> > +
> > +/**
> > + * intel_huc_load() - load HuC uCode to device
> > + * @dev: the drm device
> > + *
> > + * Called from gem_init_hw() during driver loading and also after a GPU reset.
> > + * Be note that HuC loading must be done before GuC loading.
> > + *
> > + * The firmware image should have already been fetched into memory by the
> > + * earlier call to intel_huc_ucode_init(), so here we need only check that
> > + * is succeeded, and then transfer the image to the h/w.
> > + *
> > + * Return: non-zero code on error
> > + */
> > +int intel_huc_load(struct drm_device *dev)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(dev);
> > + struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
> > + int err;
> > +
> > + if (huc_fw->fetch_status == UC_FIRMWARE_NONE)
> > + return 0;
> > +
> > + DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n",
> > + huc_fw->uc_fw_path,
> > + intel_uc_fw_status_repr(huc_fw->fetch_status),
> > + intel_uc_fw_status_repr(huc_fw->load_status));
> > +
> > + if (huc_fw->fetch_status == UC_FIRMWARE_SUCCESS &&
> > + huc_fw->load_status == UC_FIRMWARE_FAIL)
> > + return -ENOEXEC;
> > +
> > + huc_fw->load_status = UC_FIRMWARE_PENDING;
> > +
> > + switch (huc_fw->fetch_status) {
> > + case UC_FIRMWARE_FAIL:
> > + /* something went wrong :( */
> > + err = -EIO;
> > + goto fail;
> > +
> > + case UC_FIRMWARE_NONE:
> > + case UC_FIRMWARE_PENDING:
> > + default:
> > + /* "can't happen" */
> > + WARN_ONCE(1, "HuC fw %s invalid fetch_status %s [%d]\n",
> > + huc_fw->uc_fw_path,
> > + intel_uc_fw_status_repr(huc_fw->fetch_status),
> > + huc_fw->fetch_status);
> > + err = -ENXIO;
> > + goto fail;
> > +
> > + case UC_FIRMWARE_SUCCESS:
> > + break;
> > + }
> > +
> > + err = huc_ucode_xfer(dev_priv);
> > + if (err)
> > + goto fail;
> > +
> > + huc_fw->load_status = UC_FIRMWARE_SUCCESS;
> > +
> > + DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n",
> > + huc_fw->uc_fw_path,
> > + intel_uc_fw_status_repr(huc_fw->fetch_status),
> > + intel_uc_fw_status_repr(huc_fw->load_status));
> > +
> > + return 0;
> > +
> > +fail:
> > + if (huc_fw->load_status == UC_FIRMWARE_PENDING)
> > + huc_fw->load_status = UC_FIRMWARE_FAIL;
> > +
> > + DRM_ERROR("Failed to complete HuC uCode load with ret %d\n", err);
> > +
> > + return err;
> > +}
> > +
> > +/**
> > + * intel_huc_fini() - clean up resources allocated for HuC
> > + * @dev: the drm device
> > + *
> > + * Cleans up by releasing the huc firmware GEM obj.
> > + */
> > +void intel_huc_fini(struct drm_device *dev)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(dev);
> > + struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
> > +
> > + mutex_lock(&dev->struct_mutex);
> > + if (huc_fw->uc_fw_obj)
> > + drm_gem_object_unreference(&huc_fw->uc_fw_obj->base);
> These are now replaced with i915_gem_object_put(huc_fw->uc_fw_obj)
>
> > + huc_fw->uc_fw_obj = NULL;
> > + mutex_unlock(&dev->struct_mutex);
> > +
> > + huc_fw->fetch_status = UC_FIRMWARE_NONE;
> > +}
> > --
> > 2.7.4
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [PATCH 3/8] drm/i915/huc: Add HuC fw loading support
2016-10-13 20:54 ` Jeff McGee
@ 2016-10-24 21:24 ` Carlos Santa
2016-10-24 22:25 ` Jeff McGee
0 siblings, 1 reply; 35+ messages in thread
From: Carlos Santa @ 2016-10-24 21:24 UTC (permalink / raw)
To: Jeff McGee, Anusha Srivatsa; +Cc: intel-gfx
On Thu, 2016-10-13 at 13:54 -0700, Jeff McGee wrote:
> On Thu, Oct 13, 2016 at 10:42:42AM -0700, Jeff McGee wrote:
> >
> > On Mon, Oct 03, 2016 at 11:42:57AM -0700, Anusha Srivatsa wrote:
> > >
> > > From: Peter Antoine <peter.antoine@intel.com>
> > >
> > > The HuC loading process is similar to GuC. The
> > > intel_uc_fw_fetch()
> > > is used for both cases.
> > >
> > > HuC loading needs to be before GuC loading. The WOPCM setting
> > > must
> > > be done early before loading any of them.
> > >
> > > v2: rebased on-top of drm-intel-nightly.
> > > removed if(HAS_GUC()) before the guc call. (D.Gordon)
> > > update huc_version number of format.
> > > v3: rebased to drm-intel-nightly, changed the file name format to
> > > match the one in the huc package.
> > > Changed dev->dev_private to to_i915()
> > > v4: moved function back to where it was.
> > > change wait_for_atomic to wait_for.
> > > v5: rebased + comment changes.
> > > v7: rebased.
> > > v8: rebased.
> > >
> > > Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> > > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > > Signed-off-by: Alex Dai <yu.dai@intel.com>
> > > Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> > > Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/Makefile | 1 +
> > > drivers/gpu/drm/i915/i915_drv.c | 3 +
> > > drivers/gpu/drm/i915/i915_drv.h | 3 +
> > > drivers/gpu/drm/i915/i915_guc_reg.h | 3 +
> > > drivers/gpu/drm/i915/intel_guc.h | 1 +
> > > drivers/gpu/drm/i915/intel_guc_loader.c | 6 +-
> > > drivers/gpu/drm/i915/intel_huc.h | 44 ++++++
> > > drivers/gpu/drm/i915/intel_huc_loader.c | 268
> > > ++++++++++++++++++++++++++++++++
> > > 8 files changed, 327 insertions(+), 2 deletions(-)
> > > create mode 100644 drivers/gpu/drm/i915/intel_huc.h
> > > create mode 100644 drivers/gpu/drm/i915/intel_huc_loader.c
> > >
> > > diff --git a/drivers/gpu/drm/i915/Makefile
> > > b/drivers/gpu/drm/i915/Makefile
> > > index e6fe004..6e99c51 100644
> > > --- a/drivers/gpu/drm/i915/Makefile
> > > +++ b/drivers/gpu/drm/i915/Makefile
> > > @@ -53,6 +53,7 @@ i915-y += i915_cmd_parser.o \
> > >
> > > # general-purpose microcontroller (GuC) support
> > > i915-y += intel_guc_loader.o \
> > > + intel_huc_loader.o \
> > > i915_guc_submission.o
> > >
> > > # autogenerated null render state
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.c
> > > b/drivers/gpu/drm/i915/i915_drv.c
> > > index 31b2b63..7af7bd6 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.c
> > > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > > @@ -613,6 +613,7 @@ static int i915_load_modeset_init(struct
> > > drm_device *dev)
> > > * working irqs for e.g. gmbus and dp aux transfers. */
> > > intel_modeset_init(dev);
> > >
> > > + intel_huc_init(dev);
> > > intel_guc_init(dev);
> > >
> > > ret = i915_gem_init(dev);
> > > @@ -638,6 +639,7 @@ static int i915_load_modeset_init(struct
> > > drm_device *dev)
> > > cleanup_gem:
> > > i915_gem_fini(dev);
> > > cleanup_irq:
> > > + intel_huc_fini(dev);
> > > intel_guc_fini(dev);
> > > drm_irq_uninstall(dev);
> > > intel_teardown_gmbus(dev);
> > > @@ -1315,6 +1317,7 @@ void i915_driver_unload(struct drm_device
> > > *dev)
> > > /* Flush any outstanding unpin_work. */
> > > drain_workqueue(dev_priv->wq);
> > >
> > > + intel_huc_fini(dev);
> > > intel_guc_fini(dev);
> > > i915_gem_fini(dev);
> > > intel_fbc_cleanup_cfb(dev_priv);
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > > b/drivers/gpu/drm/i915/i915_drv.h
> > > index e0cb71c..625aa92 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -55,6 +55,7 @@
> > > #include "intel_bios.h"
> > > #include "intel_dpll_mgr.h"
> > > #include "intel_guc.h"
> > > +#include "intel_huc.h"
> > > #include "intel_lrc.h"
> > > #include "intel_ringbuffer.h"
> > >
> > > @@ -1766,6 +1767,7 @@ struct drm_i915_private {
> > >
> > > struct intel_gvt gvt;
> > >
> > > + struct intel_huc huc;
> > > struct intel_guc guc;
> > >
> > > struct intel_csr csr;
> > > @@ -2822,6 +2824,7 @@ struct drm_i915_cmd_table {
> > > #define HAS_GUC(dev) (INTEL_INFO(dev)->has_guc)
> > > #define HAS_GUC_UCODE(dev) (HAS_GUC(dev))
> > > #define HAS_GUC_SCHED(dev) (HAS_GUC(dev))
> > > +#define HAS_HUC_UCODE(dev) (HAS_GUC(dev))
> > >
> > > #define HAS_RESOURCE_STREAMER(dev) (INTEL_INFO(dev)-
> > > >has_resource_streamer)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h
> > > b/drivers/gpu/drm/i915/i915_guc_reg.h
> > > index a47e1e4..64e942a 100644
> > > --- a/drivers/gpu/drm/i915/i915_guc_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_guc_reg.h
> > > @@ -61,9 +61,12 @@
> > > #define DMA_ADDRESS_SPACE_GTT (8 << 16)
> > > #define DMA_COPY_SIZE _MMIO(0xc310)
> > > #define DMA_CTRL _MMIO(0xc314)
> > > +#define HUC_UKERNEL (1<<9)
> > > #define UOS_MOVE (1<<4)
> > > #define START_DMA (1<<0)
> > > #define DMA_GUC_WOPCM_OFFSET _MMIO(0xc340)
> > > +#define HUC_LOADING_AGENT_VCR (0<<1)
> > > +#define HUC_LOADING_AGENT_GUC (1<<1)
> > > #define GUC_WOPCM_OFFSET_VALUE 0x80000 /*
> > > 512KB */
> > > #define GUC_MAX_IDLE_COUNT _MMIO(0xC3E4)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_guc.h
> > > b/drivers/gpu/drm/i915/intel_guc.h
> > > index 812e4ca..af76ffe 100644
> > > --- a/drivers/gpu/drm/i915/intel_guc.h
> > > +++ b/drivers/gpu/drm/i915/intel_guc.h
> > > @@ -160,6 +160,7 @@ extern const char
> > > *intel_uc_fw_status_repr(enum intel_uc_fw_status status);
> > > extern int intel_guc_suspend(struct drm_device *dev);
> > > extern int intel_guc_resume(struct drm_device *dev);
> > > void intel_uc_fw_fetch(struct drm_device *dev, struct
> > > intel_uc_fw *uc_fw);
> > > +u32 guc_wopcm_size(struct drm_i915_private *dev_priv);
> > >
> > > /* i915_guc_submission.c */
> > > int i915_guc_submission_init(struct drm_i915_private *dev_priv);
> > > diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
> > > b/drivers/gpu/drm/i915/intel_guc_loader.c
> > > index 0b863a1..0d214b4 100644
> > > --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> > > +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> > > @@ -305,7 +305,8 @@ static int guc_ucode_xfer_dma(struct
> > > drm_i915_private *dev_priv,
> > > I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
> > >
> > > /* Finally start the DMA */
> > > - I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE |
> > > START_DMA));
> > > + I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE |
> > > START_DMA) |
> > > + _MASKED_BIT_DISABLE(HUC_UKERNEL));
> > >
> > > /*
> > > * Wait for the DMA to complete & the GuC to start up.
> > > @@ -330,7 +331,7 @@ static int guc_ucode_xfer_dma(struct
> > > drm_i915_private *dev_priv,
> > > return ret;
> > > }
> > >
> > > -static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
> > > +u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
> > > {
> > > u32 wopcm_size = GUC_WOPCM_TOP;
> > >
> > > @@ -508,6 +509,7 @@ int intel_guc_setup(struct drm_device *dev)
> > > if (err)
> > > goto fail;
> > >
> > > + intel_huc_load(dev);
> > > err = guc_ucode_xfer(dev_priv);
> > > if (!err)
> > > break;
> > > diff --git a/drivers/gpu/drm/i915/intel_huc.h
> > > b/drivers/gpu/drm/i915/intel_huc.h
> > > new file mode 100644
> > > index 0000000..946caa7
> > > --- /dev/null
> > > +++ b/drivers/gpu/drm/i915/intel_huc.h
> > > @@ -0,0 +1,44 @@
> > > +/*
> > > + * Copyright © 2014 Intel Corporation
> > Should this be 2016?
> >
> > >
> > > + *
> > > + * Permission is hereby granted, free of charge, to any person
> > > obtaining a
> > > + * copy of this software and associated documentation files (the
> > > "Software"),
> > > + * to deal in the Software without restriction, including
> > > without limitation
> > > + * the rights to use, copy, modify, merge, publish, distribute,
> > > sublicense,
> > > + * and/or sell copies of the Software, and to permit persons to
> > > whom the
> > > + * Software is furnished to do so, subject to the following
> > > conditions:
> > > + *
> > > + * The above copyright notice and this permission notice
> > > (including the next
> > > + * paragraph) shall be included in all copies or substantial
> > > portions of the
> > > + * Software.
> > > + *
> > > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY
> > > KIND, EXPRESS OR
> > > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> > > MERCHANTABILITY,
> > > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
> > > EVENT SHALL
> > > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
> > > DAMAGES OR OTHER
> > > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
> > > OTHERWISE, ARISING
> > > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > > OTHER DEALINGS
> > > + * IN THE SOFTWARE.
> > > + *
> > > + */
> > > +#ifndef _INTEL_HUC_H_
> > > +#define _INTEL_HUC_H_
> > > +
> > > +#include "intel_guc.h"
> > > +
> > > +#define HUC_STATUS2 _MMIO(0xD3B0)
> > > +#define HUC_FW_VERIFIED (1<<7)
> > > +
> > > +struct intel_huc {
> > > + /* Generic uC firmware management */
> > > + struct intel_uc_fw huc_fw;
> > > +
> > > + /* HuC-specific additions */
> > > +};
> > > +
> > > +extern void intel_huc_init(struct drm_device *dev);
> > > +extern int intel_huc_load(struct drm_device *dev);
> > > +extern void intel_huc_auth(struct drm_device *dev);
> > > +extern void intel_huc_fini(struct drm_device *dev);
> These don't need extern. Please remove. Also intel_huc_auth comes in
> with
> later patch in the series so would be better to drop from here.
>
Removing intel_huc_auth actually brakes the compilation as it's being
called from intel_guc_loader.c
Carlos
> >
> > >
> > > +
> > > +#endif
> > > diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c
> > > b/drivers/gpu/drm/i915/intel_huc_loader.c
> > > new file mode 100644
> > > index 0000000..1aaff67
> > > --- /dev/null
> > > +++ b/drivers/gpu/drm/i915/intel_huc_loader.c
> > > @@ -0,0 +1,268 @@
> > > +/*
> > > + * Copyright © 2014 Intel Corporation
> > Should this be 2016?
> >
> > >
> > > + *
> > > + * Permission is hereby granted, free of charge, to any person
> > > obtaining a
> > > + * copy of this software and associated documentation files (the
> > > "Software"),
> > > + * to deal in the Software without restriction, including
> > > without limitation
> > > + * the rights to use, copy, modify, merge, publish, distribute,
> > > sublicense,
> > > + * and/or sell copies of the Software, and to permit persons to
> > > whom the
> > > + * Software is furnished to do so, subject to the following
> > > conditions:
> > > + *
> > > + * The above copyright notice and this permission notice
> > > (including the next
> > > + * paragraph) shall be included in all copies or substantial
> > > portions of the
> > > + * Software.
> > > + *
> > > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY
> > > KIND, EXPRESS OR
> > > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> > > MERCHANTABILITY,
> > > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
> > > EVENT SHALL
> > > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
> > > DAMAGES OR OTHER
> > > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
> > > OTHERWISE, ARISING
> > > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > > OTHER DEALINGS
> > > + * IN THE SOFTWARE.
> > > + *
> > > + */
> > > +#include <linux/firmware.h>
> > > +#include "i915_drv.h"
> > > +#include "intel_huc.h"
> > > +
> > > +/**
> > > + * DOC: HuC Firmware
> > > + *
> > > + * Motivation:
> > > + * GEN9 introduces a new dedicated firmware for usage in media
> > > HEVC (High
> > > + * Efficiency Video Coding) operations. Userspace can use the
> > > firmware
> > > + * capabilities by adding HuC specific commands to batch
> > > buffers.
> > > + *
> > > + * Implementation:
> > > + * On supported platforms, i915's job is to load the firmware
> > > stored on the
> > > + * file system and assist with authentication. It is up to
> > > userspace to
> > > + * detect the presence of HuC support on a platform, on their
> > > own.
> > > + * For debugging, i915 provides a debugfs file,
> > > i915_huc_load_status_info
> > > + * which displays the firmware load status.
> > Above comment refers to features added in subsequent patches and is
> > not
> > entirely accurate at that. So I would just remove this whole block.
> > Less
> > commenting is better than misleading commenting.
> >
> > >
> > > + *
> > > + * The same firmware loader is used as the GuC. Firmware *
> > > binary is fetched by
> > > + * the loader asynchronously from the driver init process.
> > > However, the actual
> > Remove * from "Firmware * binary". Loading is not asynchronous so
> > remove this
> > statement.
> >
> > >
> > > + * loading to HW is deferred until GEM initialization is done.
> > > + *
> > > + * Note that HuC firmware loading must be done before GuC
> > > loading.
> > > + */
> > > +
> > > +#define I915_SKL_HUC_UCODE "i915/skl_huc_ver01_07_1398.bin"
> > > +MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
> > Please update to use the new approach used by GuC for specifying
> > required version and constructing the file path. See
> > intel_guc_loader.c.
> > HuC firmware versioning includes the build number after the minor
> > so
> > some modification will be needed.
> >
> > >
> > > +
> > > +/**
> > > + * intel_huc_load_ucode() - DMA's the firmware
> > > + * @dev: the drm device
> > Fix name and parameter
> >
> > >
> > > + *
> > > + * This function takes the gem object containing the firmware,
> > > sets up the DMA
> > > + * engine MMIO, triggers the DMA operation and waits for it to
> > > finish.
> > > + *
> > > + * Transfer the firmware image to RAM for execution by the
> > > microcontroller.
> > > + *
> > > + * Return: 0 on success, non-zero on failure
> > > + */
> > > +
> > > +static int huc_ucode_xfer(struct drm_i915_private *dev_priv)
> > > +{
> > > + struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
> > > + struct i915_vma *vma;
> > > + unsigned long offset = 0;
> > > + u32 size;
> > > + int ret;
> > > +
> > > + ret = i915_gem_object_set_to_gtt_domain(huc_fw-
> > > >uc_fw_obj, false);
> > > + if (ret) {
> > > + DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
> > > + return ret;
> > > + }
> > > +
> > > + vma = i915_gem_object_ggtt_pin(huc_fw->uc_fw_obj, NULL,
> > > 0, 0, 0);
> > > + if (IS_ERR(vma)) {
> > > + DRM_DEBUG_DRIVER("pin failed %d\n",
> > > (int)PTR_ERR(vma));
> > > + return PTR_ERR(vma);
> > > + }
> > > +
> > > + /* Invalidate GuC TLB to let GuC take the latest updates
> > > to GTT. */
> > > + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
> > > +
> > > + WARN_ON(!mutex_is_locked(&dev_priv->drm.struct_mutex));
> > I don't see reason for this WARN_ON check. This function is called
> > in well defined paths that require locking way up the chain.
> > I think we can remove it.
> >
> > >
> > > + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> > > +
> > > + /* init WOPCM */
> > > + I915_WRITE(GUC_WOPCM_SIZE, guc_wopcm_size(dev_priv));
> > > + I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE
> > > |
> > > + HUC_LOADING_AGENT_GUC);
> > > +
> > > + /* Set the source address for the uCode */
> > > + offset = i915_ggtt_offset(vma) + huc_fw->header_offset;
> > > + I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
> > > + I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) &
> > > 0xFFFF);
> > > +
> > > + /* Hardware doesn't look at destination address for HuC.
> > > Set it to 0,
> > > + * but still program the correct address space.
> > > + */
> > > + I915_WRITE(DMA_ADDR_1_LOW, 0);
> > > + I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
> > > +
> > > + size = huc_fw->header_size + huc_fw->ucode_size;
> > > + I915_WRITE(DMA_COPY_SIZE, size);
> > > +
> > > + /* Start the DMA */
> > > + I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL |
> > > START_DMA));
> > > +
> > > + /* Wait for DMA to finish */
> > > + ret = wait_for((I915_READ(DMA_CTRL) & START_DMA) == 0,
> > > 100);
> > > +
> > > + DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret
> > > %d\n", ret);
> > > +
> > > + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> > > +
> > > + /*
> > > + * We keep the object pages for reuse during resume. But
> > > we can unpin it
> > > + * now that DMA has completed, so it doesn't continue to
> > > take up space.
> > > + */
> > > + i915_vma_unpin(vma);
> > > +
> > > + return ret;
> > > +}
> > > +
> > > +/**
> > > + * intel_huc_init() - initiate HuC firmware loading request
> > > + * @dev: the drm device
> > > + *
> > > + * Called early during driver load, but after GEM is
> > > initialised. The loading
> > > + * will continue only when driver explicitly specify firmware
> > > name and version.
> > > + * All other cases are considered as UC_FIRMWARE_NONE either
> > > because HW is not
> > > + * capable or driver yet support it. And there will be no error
> > > message for
> > > + * UC_FIRMWARE_NONE cases.
> > > + *
> > > + * The DMA-copying to HW is done later when
> > > intel_huc_ucode_load() is called.
> > intel_huc_ucode_load() should be intel_huc_load().
> >
> > >
> > > + */
> > > +void intel_huc_init(struct drm_device *dev)
> > > +{
> > > + struct drm_i915_private *dev_priv = to_i915(dev);
> > > + struct intel_huc *huc = &dev_priv->huc;
> > > + struct intel_uc_fw *huc_fw = &huc->huc_fw;
> > > + const char *fw_path = NULL;
> > > +
> > > + huc_fw->uc_dev = dev;
> > > + huc_fw->uc_fw_path = NULL;
> > > + huc_fw->fetch_status = UC_FIRMWARE_NONE;
> > > + huc_fw->load_status = UC_FIRMWARE_NONE;
> > > + huc_fw->fw_type = UC_FW_TYPE_HUC;
> > > +
> > > + if (!HAS_HUC_UCODE(dev_priv))
> > > + return;
> > > +
> > > + if (IS_SKYLAKE(dev_priv)) {
> > > + fw_path = I915_SKL_HUC_UCODE;
> > > + huc_fw->major_ver_wanted = 1;
> > > + huc_fw->minor_ver_wanted = 7;
> > > + }
> > > +
> > > + if (fw_path == NULL)
> > > + return;
> > > +
> > > + huc_fw->uc_fw_path = fw_path;
> > > + huc_fw->fetch_status = UC_FIRMWARE_PENDING;
> > > +
> > > + DRM_DEBUG_DRIVER("HuC firmware pending, path %s\n",
> > > fw_path);
> > > +
> > > + intel_uc_fw_fetch(dev, huc_fw);
> > > +}
> > > +
> > > +/**
> > > + * intel_huc_load() - load HuC uCode to device
> > > + * @dev: the drm device
> > > + *
> > > + * Called from gem_init_hw() during driver loading and also
> > > after a GPU reset.
> > > + * Be note that HuC loading must be done before GuC loading.
> > > + *
> > > + * The firmware image should have already been fetched into
> > > memory by the
> > > + * earlier call to intel_huc_ucode_init(), so here we need only
> > > check that
> > > + * is succeeded, and then transfer the image to the h/w.
> > > + *
> > > + * Return: non-zero code on error
> > > + */
> > > +int intel_huc_load(struct drm_device *dev)
> > > +{
> > > + struct drm_i915_private *dev_priv = to_i915(dev);
> > > + struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
> > > + int err;
> > > +
> > > + if (huc_fw->fetch_status == UC_FIRMWARE_NONE)
> > > + return 0;
> > > +
> > > + DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n",
> > > + huc_fw->uc_fw_path,
> > > + intel_uc_fw_status_repr(huc_fw->fetch_status),
> > > + intel_uc_fw_status_repr(huc_fw->load_status));
> > > +
> > > + if (huc_fw->fetch_status == UC_FIRMWARE_SUCCESS &&
> > > + huc_fw->load_status == UC_FIRMWARE_FAIL)
> > > + return -ENOEXEC;
> > > +
> > > + huc_fw->load_status = UC_FIRMWARE_PENDING;
> > > +
> > > + switch (huc_fw->fetch_status) {
> > > + case UC_FIRMWARE_FAIL:
> > > + /* something went wrong :( */
> > > + err = -EIO;
> > > + goto fail;
> > > +
> > > + case UC_FIRMWARE_NONE:
> > > + case UC_FIRMWARE_PENDING:
> > > + default:
> > > + /* "can't happen" */
> > > + WARN_ONCE(1, "HuC fw %s invalid fetch_status %s
> > > [%d]\n",
> > > + huc_fw->uc_fw_path,
> > > + intel_uc_fw_status_repr(huc_fw-
> > > >fetch_status),
> > > + huc_fw->fetch_status);
> > > + err = -ENXIO;
> > > + goto fail;
> > > +
> > > + case UC_FIRMWARE_SUCCESS:
> > > + break;
> > > + }
> > > +
> > > + err = huc_ucode_xfer(dev_priv);
> > > + if (err)
> > > + goto fail;
> > > +
> > > + huc_fw->load_status = UC_FIRMWARE_SUCCESS;
> > > +
> > > + DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n",
> > > + huc_fw->uc_fw_path,
> > > + intel_uc_fw_status_repr(huc_fw->fetch_status),
> > > + intel_uc_fw_status_repr(huc_fw->load_status));
> > > +
> > > + return 0;
> > > +
> > > +fail:
> > > + if (huc_fw->load_status == UC_FIRMWARE_PENDING)
> > > + huc_fw->load_status = UC_FIRMWARE_FAIL;
> > > +
> > > + DRM_ERROR("Failed to complete HuC uCode load with ret
> > > %d\n", err);
> > > +
> > > + return err;
> > > +}
> > > +
> > > +/**
> > > + * intel_huc_fini() - clean up resources allocated for HuC
> > > + * @dev: the drm device
> > > + *
> > > + * Cleans up by releasing the huc firmware GEM obj.
> > > + */
> > > +void intel_huc_fini(struct drm_device *dev)
> > > +{
> > > + struct drm_i915_private *dev_priv = to_i915(dev);
> > > + struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
> > > +
> > > + mutex_lock(&dev->struct_mutex);
> > > + if (huc_fw->uc_fw_obj)
> > > + drm_gem_object_unreference(&huc_fw->uc_fw_obj-
> > > >base);
> > These are now replaced with i915_gem_object_put(huc_fw->uc_fw_obj)
> >
> > >
> > > + huc_fw->uc_fw_obj = NULL;
> > > + mutex_unlock(&dev->struct_mutex);
> > > +
> > > + huc_fw->fetch_status = UC_FIRMWARE_NONE;
> > > +}
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^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [PATCH 3/8] drm/i915/huc: Add HuC fw loading support
2016-10-24 21:24 ` Carlos Santa
@ 2016-10-24 22:25 ` Jeff McGee
0 siblings, 0 replies; 35+ messages in thread
From: Jeff McGee @ 2016-10-24 22:25 UTC (permalink / raw)
To: Carlos Santa; +Cc: intel-gfx
On Mon, Oct 24, 2016 at 02:24:01PM -0700, Carlos Santa wrote:
> On Thu, 2016-10-13 at 13:54 -0700, Jeff McGee wrote:
> > On Thu, Oct 13, 2016 at 10:42:42AM -0700, Jeff McGee wrote:
> > >
> > > On Mon, Oct 03, 2016 at 11:42:57AM -0700, Anusha Srivatsa wrote:
> > > >
> > > > From: Peter Antoine <peter.antoine@intel.com>
> > > >
> > > > The HuC loading process is similar to GuC. The
> > > > intel_uc_fw_fetch()
> > > > is used for both cases.
> > > >
> > > > HuC loading needs to be before GuC loading. The WOPCM setting
> > > > must
> > > > be done early before loading any of them.
> > > >
> > > > v2: rebased on-top of drm-intel-nightly.
> > > > removed if(HAS_GUC()) before the guc call. (D.Gordon)
> > > > update huc_version number of format.
> > > > v3: rebased to drm-intel-nightly, changed the file name format to
> > > > match the one in the huc package.
> > > > Changed dev->dev_private to to_i915()
> > > > v4: moved function back to where it was.
> > > > change wait_for_atomic to wait_for.
> > > > v5: rebased + comment changes.
> > > > v7: rebased.
> > > > v8: rebased.
> > > >
> > > > Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> > > > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > > > Signed-off-by: Alex Dai <yu.dai@intel.com>
> > > > Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> > > > Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/Makefile | 1 +
> > > > drivers/gpu/drm/i915/i915_drv.c | 3 +
> > > > drivers/gpu/drm/i915/i915_drv.h | 3 +
> > > > drivers/gpu/drm/i915/i915_guc_reg.h | 3 +
> > > > drivers/gpu/drm/i915/intel_guc.h | 1 +
> > > > drivers/gpu/drm/i915/intel_guc_loader.c | 6 +-
> > > > drivers/gpu/drm/i915/intel_huc.h | 44 ++++++
> > > > drivers/gpu/drm/i915/intel_huc_loader.c | 268
> > > > ++++++++++++++++++++++++++++++++
> > > > 8 files changed, 327 insertions(+), 2 deletions(-)
> > > > create mode 100644 drivers/gpu/drm/i915/intel_huc.h
> > > > create mode 100644 drivers/gpu/drm/i915/intel_huc_loader.c
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/Makefile
> > > > b/drivers/gpu/drm/i915/Makefile
> > > > index e6fe004..6e99c51 100644
> > > > --- a/drivers/gpu/drm/i915/Makefile
> > > > +++ b/drivers/gpu/drm/i915/Makefile
> > > > @@ -53,6 +53,7 @@ i915-y += i915_cmd_parser.o \
> > > >
> > > > # general-purpose microcontroller (GuC) support
> > > > i915-y += intel_guc_loader.o \
> > > > + intel_huc_loader.o \
> > > > i915_guc_submission.o
> > > >
> > > > # autogenerated null render state
> > > > diff --git a/drivers/gpu/drm/i915/i915_drv.c
> > > > b/drivers/gpu/drm/i915/i915_drv.c
> > > > index 31b2b63..7af7bd6 100644
> > > > --- a/drivers/gpu/drm/i915/i915_drv.c
> > > > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > > > @@ -613,6 +613,7 @@ static int i915_load_modeset_init(struct
> > > > drm_device *dev)
> > > > * working irqs for e.g. gmbus and dp aux transfers. */
> > > > intel_modeset_init(dev);
> > > >
> > > > + intel_huc_init(dev);
> > > > intel_guc_init(dev);
> > > >
> > > > ret = i915_gem_init(dev);
> > > > @@ -638,6 +639,7 @@ static int i915_load_modeset_init(struct
> > > > drm_device *dev)
> > > > cleanup_gem:
> > > > i915_gem_fini(dev);
> > > > cleanup_irq:
> > > > + intel_huc_fini(dev);
> > > > intel_guc_fini(dev);
> > > > drm_irq_uninstall(dev);
> > > > intel_teardown_gmbus(dev);
> > > > @@ -1315,6 +1317,7 @@ void i915_driver_unload(struct drm_device
> > > > *dev)
> > > > /* Flush any outstanding unpin_work. */
> > > > drain_workqueue(dev_priv->wq);
> > > >
> > > > + intel_huc_fini(dev);
> > > > intel_guc_fini(dev);
> > > > i915_gem_fini(dev);
> > > > intel_fbc_cleanup_cfb(dev_priv);
> > > > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > > > b/drivers/gpu/drm/i915/i915_drv.h
> > > > index e0cb71c..625aa92 100644
> > > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > > @@ -55,6 +55,7 @@
> > > > #include "intel_bios.h"
> > > > #include "intel_dpll_mgr.h"
> > > > #include "intel_guc.h"
> > > > +#include "intel_huc.h"
> > > > #include "intel_lrc.h"
> > > > #include "intel_ringbuffer.h"
> > > >
> > > > @@ -1766,6 +1767,7 @@ struct drm_i915_private {
> > > >
> > > > struct intel_gvt gvt;
> > > >
> > > > + struct intel_huc huc;
> > > > struct intel_guc guc;
> > > >
> > > > struct intel_csr csr;
> > > > @@ -2822,6 +2824,7 @@ struct drm_i915_cmd_table {
> > > > #define HAS_GUC(dev) (INTEL_INFO(dev)->has_guc)
> > > > #define HAS_GUC_UCODE(dev) (HAS_GUC(dev))
> > > > #define HAS_GUC_SCHED(dev) (HAS_GUC(dev))
> > > > +#define HAS_HUC_UCODE(dev) (HAS_GUC(dev))
> > > >
> > > > #define HAS_RESOURCE_STREAMER(dev) (INTEL_INFO(dev)-
> > > > >has_resource_streamer)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h
> > > > b/drivers/gpu/drm/i915/i915_guc_reg.h
> > > > index a47e1e4..64e942a 100644
> > > > --- a/drivers/gpu/drm/i915/i915_guc_reg.h
> > > > +++ b/drivers/gpu/drm/i915/i915_guc_reg.h
> > > > @@ -61,9 +61,12 @@
> > > > #define DMA_ADDRESS_SPACE_GTT (8 << 16)
> > > > #define DMA_COPY_SIZE _MMIO(0xc310)
> > > > #define DMA_CTRL _MMIO(0xc314)
> > > > +#define HUC_UKERNEL (1<<9)
> > > > #define UOS_MOVE (1<<4)
> > > > #define START_DMA (1<<0)
> > > > #define DMA_GUC_WOPCM_OFFSET _MMIO(0xc340)
> > > > +#define HUC_LOADING_AGENT_VCR (0<<1)
> > > > +#define HUC_LOADING_AGENT_GUC (1<<1)
> > > > #define GUC_WOPCM_OFFSET_VALUE 0x80000 /*
> > > > 512KB */
> > > > #define GUC_MAX_IDLE_COUNT _MMIO(0xC3E4)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/intel_guc.h
> > > > b/drivers/gpu/drm/i915/intel_guc.h
> > > > index 812e4ca..af76ffe 100644
> > > > --- a/drivers/gpu/drm/i915/intel_guc.h
> > > > +++ b/drivers/gpu/drm/i915/intel_guc.h
> > > > @@ -160,6 +160,7 @@ extern const char
> > > > *intel_uc_fw_status_repr(enum intel_uc_fw_status status);
> > > > extern int intel_guc_suspend(struct drm_device *dev);
> > > > extern int intel_guc_resume(struct drm_device *dev);
> > > > void intel_uc_fw_fetch(struct drm_device *dev, struct
> > > > intel_uc_fw *uc_fw);
> > > > +u32 guc_wopcm_size(struct drm_i915_private *dev_priv);
> > > >
> > > > /* i915_guc_submission.c */
> > > > int i915_guc_submission_init(struct drm_i915_private *dev_priv);
> > > > diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
> > > > b/drivers/gpu/drm/i915/intel_guc_loader.c
> > > > index 0b863a1..0d214b4 100644
> > > > --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> > > > +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> > > > @@ -305,7 +305,8 @@ static int guc_ucode_xfer_dma(struct
> > > > drm_i915_private *dev_priv,
> > > > I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
> > > >
> > > > /* Finally start the DMA */
> > > > - I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE |
> > > > START_DMA));
> > > > + I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE |
> > > > START_DMA) |
> > > > + _MASKED_BIT_DISABLE(HUC_UKERNEL));
> > > >
> > > > /*
> > > > * Wait for the DMA to complete & the GuC to start up.
> > > > @@ -330,7 +331,7 @@ static int guc_ucode_xfer_dma(struct
> > > > drm_i915_private *dev_priv,
> > > > return ret;
> > > > }
> > > >
> > > > -static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
> > > > +u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
> > > > {
> > > > u32 wopcm_size = GUC_WOPCM_TOP;
> > > >
> > > > @@ -508,6 +509,7 @@ int intel_guc_setup(struct drm_device *dev)
> > > > if (err)
> > > > goto fail;
> > > >
> > > > + intel_huc_load(dev);
> > > > err = guc_ucode_xfer(dev_priv);
> > > > if (!err)
> > > > break;
> > > > diff --git a/drivers/gpu/drm/i915/intel_huc.h
> > > > b/drivers/gpu/drm/i915/intel_huc.h
> > > > new file mode 100644
> > > > index 0000000..946caa7
> > > > --- /dev/null
> > > > +++ b/drivers/gpu/drm/i915/intel_huc.h
> > > > @@ -0,0 +1,44 @@
> > > > +/*
> > > > + * Copyright © 2014 Intel Corporation
> > > Should this be 2016?
> > >
> > > >
> > > > + *
> > > > + * Permission is hereby granted, free of charge, to any person
> > > > obtaining a
> > > > + * copy of this software and associated documentation files (the
> > > > "Software"),
> > > > + * to deal in the Software without restriction, including
> > > > without limitation
> > > > + * the rights to use, copy, modify, merge, publish, distribute,
> > > > sublicense,
> > > > + * and/or sell copies of the Software, and to permit persons to
> > > > whom the
> > > > + * Software is furnished to do so, subject to the following
> > > > conditions:
> > > > + *
> > > > + * The above copyright notice and this permission notice
> > > > (including the next
> > > > + * paragraph) shall be included in all copies or substantial
> > > > portions of the
> > > > + * Software.
> > > > + *
> > > > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY
> > > > KIND, EXPRESS OR
> > > > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> > > > MERCHANTABILITY,
> > > > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
> > > > EVENT SHALL
> > > > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
> > > > DAMAGES OR OTHER
> > > > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
> > > > OTHERWISE, ARISING
> > > > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > > > OTHER DEALINGS
> > > > + * IN THE SOFTWARE.
> > > > + *
> > > > + */
> > > > +#ifndef _INTEL_HUC_H_
> > > > +#define _INTEL_HUC_H_
> > > > +
> > > > +#include "intel_guc.h"
> > > > +
> > > > +#define HUC_STATUS2 _MMIO(0xD3B0)
> > > > +#define HUC_FW_VERIFIED (1<<7)
> > > > +
> > > > +struct intel_huc {
> > > > + /* Generic uC firmware management */
> > > > + struct intel_uc_fw huc_fw;
> > > > +
> > > > + /* HuC-specific additions */
> > > > +};
> > > > +
> > > > +extern void intel_huc_init(struct drm_device *dev);
> > > > +extern int intel_huc_load(struct drm_device *dev);
> > > > +extern void intel_huc_auth(struct drm_device *dev);
> > > > +extern void intel_huc_fini(struct drm_device *dev);
> > These don't need extern. Please remove. Also intel_huc_auth comes in
> > with
> > later patch in the series so would be better to drop from here.
> >
>
> Removing intel_huc_auth actually brakes the compilation as it's being
> called from intel_guc_loader.c
>
> Carlos
>
Not until patch 5. That's why it would be cleaner to add intel_huc_auth
in patch 5 rather than here (patch 3) where it is not immediately used.
Not a huge deal.
Jeff
> > >
> > > >
> > > > +
> > > > +#endif
> > > > diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c
> > > > b/drivers/gpu/drm/i915/intel_huc_loader.c
> > > > new file mode 100644
> > > > index 0000000..1aaff67
> > > > --- /dev/null
> > > > +++ b/drivers/gpu/drm/i915/intel_huc_loader.c
> > > > @@ -0,0 +1,268 @@
> > > > +/*
> > > > + * Copyright © 2014 Intel Corporation
> > > Should this be 2016?
> > >
> > > >
> > > > + *
> > > > + * Permission is hereby granted, free of charge, to any person
> > > > obtaining a
> > > > + * copy of this software and associated documentation files (the
> > > > "Software"),
> > > > + * to deal in the Software without restriction, including
> > > > without limitation
> > > > + * the rights to use, copy, modify, merge, publish, distribute,
> > > > sublicense,
> > > > + * and/or sell copies of the Software, and to permit persons to
> > > > whom the
> > > > + * Software is furnished to do so, subject to the following
> > > > conditions:
> > > > + *
> > > > + * The above copyright notice and this permission notice
> > > > (including the next
> > > > + * paragraph) shall be included in all copies or substantial
> > > > portions of the
> > > > + * Software.
> > > > + *
> > > > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY
> > > > KIND, EXPRESS OR
> > > > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> > > > MERCHANTABILITY,
> > > > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
> > > > EVENT SHALL
> > > > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
> > > > DAMAGES OR OTHER
> > > > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
> > > > OTHERWISE, ARISING
> > > > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > > > OTHER DEALINGS
> > > > + * IN THE SOFTWARE.
> > > > + *
> > > > + */
> > > > +#include <linux/firmware.h>
> > > > +#include "i915_drv.h"
> > > > +#include "intel_huc.h"
> > > > +
> > > > +/**
> > > > + * DOC: HuC Firmware
> > > > + *
> > > > + * Motivation:
> > > > + * GEN9 introduces a new dedicated firmware for usage in media
> > > > HEVC (High
> > > > + * Efficiency Video Coding) operations. Userspace can use the
> > > > firmware
> > > > + * capabilities by adding HuC specific commands to batch
> > > > buffers.
> > > > + *
> > > > + * Implementation:
> > > > + * On supported platforms, i915's job is to load the firmware
> > > > stored on the
> > > > + * file system and assist with authentication. It is up to
> > > > userspace to
> > > > + * detect the presence of HuC support on a platform, on their
> > > > own.
> > > > + * For debugging, i915 provides a debugfs file,
> > > > i915_huc_load_status_info
> > > > + * which displays the firmware load status.
> > > Above comment refers to features added in subsequent patches and is
> > > not
> > > entirely accurate at that. So I would just remove this whole block.
> > > Less
> > > commenting is better than misleading commenting.
> > >
> > > >
> > > > + *
> > > > + * The same firmware loader is used as the GuC. Firmware *
> > > > binary is fetched by
> > > > + * the loader asynchronously from the driver init process.
> > > > However, the actual
> > > Remove * from "Firmware * binary". Loading is not asynchronous so
> > > remove this
> > > statement.
> > >
> > > >
> > > > + * loading to HW is deferred until GEM initialization is done.
> > > > + *
> > > > + * Note that HuC firmware loading must be done before GuC
> > > > loading.
> > > > + */
> > > > +
> > > > +#define I915_SKL_HUC_UCODE "i915/skl_huc_ver01_07_1398.bin"
> > > > +MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
> > > Please update to use the new approach used by GuC for specifying
> > > required version and constructing the file path. See
> > > intel_guc_loader.c.
> > > HuC firmware versioning includes the build number after the minor
> > > so
> > > some modification will be needed.
> > >
> > > >
> > > > +
> > > > +/**
> > > > + * intel_huc_load_ucode() - DMA's the firmware
> > > > + * @dev: the drm device
> > > Fix name and parameter
> > >
> > > >
> > > > + *
> > > > + * This function takes the gem object containing the firmware,
> > > > sets up the DMA
> > > > + * engine MMIO, triggers the DMA operation and waits for it to
> > > > finish.
> > > > + *
> > > > + * Transfer the firmware image to RAM for execution by the
> > > > microcontroller.
> > > > + *
> > > > + * Return: 0 on success, non-zero on failure
> > > > + */
> > > > +
> > > > +static int huc_ucode_xfer(struct drm_i915_private *dev_priv)
> > > > +{
> > > > + struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
> > > > + struct i915_vma *vma;
> > > > + unsigned long offset = 0;
> > > > + u32 size;
> > > > + int ret;
> > > > +
> > > > + ret = i915_gem_object_set_to_gtt_domain(huc_fw-
> > > > >uc_fw_obj, false);
> > > > + if (ret) {
> > > > + DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
> > > > + return ret;
> > > > + }
> > > > +
> > > > + vma = i915_gem_object_ggtt_pin(huc_fw->uc_fw_obj, NULL,
> > > > 0, 0, 0);
> > > > + if (IS_ERR(vma)) {
> > > > + DRM_DEBUG_DRIVER("pin failed %d\n",
> > > > (int)PTR_ERR(vma));
> > > > + return PTR_ERR(vma);
> > > > + }
> > > > +
> > > > + /* Invalidate GuC TLB to let GuC take the latest updates
> > > > to GTT. */
> > > > + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
> > > > +
> > > > + WARN_ON(!mutex_is_locked(&dev_priv->drm.struct_mutex));
> > > I don't see reason for this WARN_ON check. This function is called
> > > in well defined paths that require locking way up the chain.
> > > I think we can remove it.
> > >
> > > >
> > > > + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> > > > +
> > > > + /* init WOPCM */
> > > > + I915_WRITE(GUC_WOPCM_SIZE, guc_wopcm_size(dev_priv));
> > > > + I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE
> > > > |
> > > > + HUC_LOADING_AGENT_GUC);
> > > > +
> > > > + /* Set the source address for the uCode */
> > > > + offset = i915_ggtt_offset(vma) + huc_fw->header_offset;
> > > > + I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
> > > > + I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) &
> > > > 0xFFFF);
> > > > +
> > > > + /* Hardware doesn't look at destination address for HuC.
> > > > Set it to 0,
> > > > + * but still program the correct address space.
> > > > + */
> > > > + I915_WRITE(DMA_ADDR_1_LOW, 0);
> > > > + I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
> > > > +
> > > > + size = huc_fw->header_size + huc_fw->ucode_size;
> > > > + I915_WRITE(DMA_COPY_SIZE, size);
> > > > +
> > > > + /* Start the DMA */
> > > > + I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL |
> > > > START_DMA));
> > > > +
> > > > + /* Wait for DMA to finish */
> > > > + ret = wait_for((I915_READ(DMA_CTRL) & START_DMA) == 0,
> > > > 100);
> > > > +
> > > > + DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret
> > > > %d\n", ret);
> > > > +
> > > > + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> > > > +
> > > > + /*
> > > > + * We keep the object pages for reuse during resume. But
> > > > we can unpin it
> > > > + * now that DMA has completed, so it doesn't continue to
> > > > take up space.
> > > > + */
> > > > + i915_vma_unpin(vma);
> > > > +
> > > > + return ret;
> > > > +}
> > > > +
> > > > +/**
> > > > + * intel_huc_init() - initiate HuC firmware loading request
> > > > + * @dev: the drm device
> > > > + *
> > > > + * Called early during driver load, but after GEM is
> > > > initialised. The loading
> > > > + * will continue only when driver explicitly specify firmware
> > > > name and version.
> > > > + * All other cases are considered as UC_FIRMWARE_NONE either
> > > > because HW is not
> > > > + * capable or driver yet support it. And there will be no error
> > > > message for
> > > > + * UC_FIRMWARE_NONE cases.
> > > > + *
> > > > + * The DMA-copying to HW is done later when
> > > > intel_huc_ucode_load() is called.
> > > intel_huc_ucode_load() should be intel_huc_load().
> > >
> > > >
> > > > + */
> > > > +void intel_huc_init(struct drm_device *dev)
> > > > +{
> > > > + struct drm_i915_private *dev_priv = to_i915(dev);
> > > > + struct intel_huc *huc = &dev_priv->huc;
> > > > + struct intel_uc_fw *huc_fw = &huc->huc_fw;
> > > > + const char *fw_path = NULL;
> > > > +
> > > > + huc_fw->uc_dev = dev;
> > > > + huc_fw->uc_fw_path = NULL;
> > > > + huc_fw->fetch_status = UC_FIRMWARE_NONE;
> > > > + huc_fw->load_status = UC_FIRMWARE_NONE;
> > > > + huc_fw->fw_type = UC_FW_TYPE_HUC;
> > > > +
> > > > + if (!HAS_HUC_UCODE(dev_priv))
> > > > + return;
> > > > +
> > > > + if (IS_SKYLAKE(dev_priv)) {
> > > > + fw_path = I915_SKL_HUC_UCODE;
> > > > + huc_fw->major_ver_wanted = 1;
> > > > + huc_fw->minor_ver_wanted = 7;
> > > > + }
> > > > +
> > > > + if (fw_path == NULL)
> > > > + return;
> > > > +
> > > > + huc_fw->uc_fw_path = fw_path;
> > > > + huc_fw->fetch_status = UC_FIRMWARE_PENDING;
> > > > +
> > > > + DRM_DEBUG_DRIVER("HuC firmware pending, path %s\n",
> > > > fw_path);
> > > > +
> > > > + intel_uc_fw_fetch(dev, huc_fw);
> > > > +}
> > > > +
> > > > +/**
> > > > + * intel_huc_load() - load HuC uCode to device
> > > > + * @dev: the drm device
> > > > + *
> > > > + * Called from gem_init_hw() during driver loading and also
> > > > after a GPU reset.
> > > > + * Be note that HuC loading must be done before GuC loading.
> > > > + *
> > > > + * The firmware image should have already been fetched into
> > > > memory by the
> > > > + * earlier call to intel_huc_ucode_init(), so here we need only
> > > > check that
> > > > + * is succeeded, and then transfer the image to the h/w.
> > > > + *
> > > > + * Return: non-zero code on error
> > > > + */
> > > > +int intel_huc_load(struct drm_device *dev)
> > > > +{
> > > > + struct drm_i915_private *dev_priv = to_i915(dev);
> > > > + struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
> > > > + int err;
> > > > +
> > > > + if (huc_fw->fetch_status == UC_FIRMWARE_NONE)
> > > > + return 0;
> > > > +
> > > > + DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n",
> > > > + huc_fw->uc_fw_path,
> > > > + intel_uc_fw_status_repr(huc_fw->fetch_status),
> > > > + intel_uc_fw_status_repr(huc_fw->load_status));
> > > > +
> > > > + if (huc_fw->fetch_status == UC_FIRMWARE_SUCCESS &&
> > > > + huc_fw->load_status == UC_FIRMWARE_FAIL)
> > > > + return -ENOEXEC;
> > > > +
> > > > + huc_fw->load_status = UC_FIRMWARE_PENDING;
> > > > +
> > > > + switch (huc_fw->fetch_status) {
> > > > + case UC_FIRMWARE_FAIL:
> > > > + /* something went wrong :( */
> > > > + err = -EIO;
> > > > + goto fail;
> > > > +
> > > > + case UC_FIRMWARE_NONE:
> > > > + case UC_FIRMWARE_PENDING:
> > > > + default:
> > > > + /* "can't happen" */
> > > > + WARN_ONCE(1, "HuC fw %s invalid fetch_status %s
> > > > [%d]\n",
> > > > + huc_fw->uc_fw_path,
> > > > + intel_uc_fw_status_repr(huc_fw-
> > > > >fetch_status),
> > > > + huc_fw->fetch_status);
> > > > + err = -ENXIO;
> > > > + goto fail;
> > > > +
> > > > + case UC_FIRMWARE_SUCCESS:
> > > > + break;
> > > > + }
> > > > +
> > > > + err = huc_ucode_xfer(dev_priv);
> > > > + if (err)
> > > > + goto fail;
> > > > +
> > > > + huc_fw->load_status = UC_FIRMWARE_SUCCESS;
> > > > +
> > > > + DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n",
> > > > + huc_fw->uc_fw_path,
> > > > + intel_uc_fw_status_repr(huc_fw->fetch_status),
> > > > + intel_uc_fw_status_repr(huc_fw->load_status));
> > > > +
> > > > + return 0;
> > > > +
> > > > +fail:
> > > > + if (huc_fw->load_status == UC_FIRMWARE_PENDING)
> > > > + huc_fw->load_status = UC_FIRMWARE_FAIL;
> > > > +
> > > > + DRM_ERROR("Failed to complete HuC uCode load with ret
> > > > %d\n", err);
> > > > +
> > > > + return err;
> > > > +}
> > > > +
> > > > +/**
> > > > + * intel_huc_fini() - clean up resources allocated for HuC
> > > > + * @dev: the drm device
> > > > + *
> > > > + * Cleans up by releasing the huc firmware GEM obj.
> > > > + */
> > > > +void intel_huc_fini(struct drm_device *dev)
> > > > +{
> > > > + struct drm_i915_private *dev_priv = to_i915(dev);
> > > > + struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
> > > > +
> > > > + mutex_lock(&dev->struct_mutex);
> > > > + if (huc_fw->uc_fw_obj)
> > > > + drm_gem_object_unreference(&huc_fw->uc_fw_obj-
> > > > >base);
> > > These are now replaced with i915_gem_object_put(huc_fw->uc_fw_obj)
> > >
> > > >
> > > > + huc_fw->uc_fw_obj = NULL;
> > > > + mutex_unlock(&dev->struct_mutex);
> > > > +
> > > > + huc_fw->fetch_status = UC_FIRMWARE_NONE;
> > > > +}
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^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH 4/8] drm/i915/huc: Add debugfs for HuC loading status check
2016-10-03 18:42 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa
` (2 preceding siblings ...)
2016-10-03 18:42 ` [PATCH 3/8] drm/i915/huc: Add HuC fw loading support Anusha Srivatsa
@ 2016-10-03 18:42 ` Anusha Srivatsa
2016-10-13 17:49 ` Jeff McGee
` (2 more replies)
2016-10-03 18:42 ` [PATCH 5/8] drm/i915/huc: Support HuC authentication Anusha Srivatsa
` (5 subsequent siblings)
9 siblings, 3 replies; 35+ messages in thread
From: Anusha Srivatsa @ 2016-10-03 18:42 UTC (permalink / raw)
To: intel-gfx
From: Peter Antoine <peter.antoine@intel.com>
Add debugfs entry for HuC loading status check.
v2: rebase on-top of drm-intel-nightly.
v3: rebased again.
v7: rebased.
v8: rebased.
Tested-by: Xiang Haihao <haihao.xiang@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 44258a8..7bd0e23 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2413,6 +2413,36 @@ static int i915_llc(struct seq_file *m, void *data)
return 0;
}
+static int i915_huc_load_status_info(struct seq_file *m, void *data)
+{
+ struct drm_i915_private *dev_priv = node_to_i915(m->private);
+ struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
+
+ if (!HAS_HUC_UCODE(dev_priv))
+ return 0;
+
+ seq_puts(m, "HuC firmware status:\n");
+ seq_printf(m, "\tpath: %s\n", huc_fw->uc_fw_path);
+ seq_printf(m, "\tfetch: %s\n",
+ intel_uc_fw_status_repr(huc_fw->fetch_status));
+ seq_printf(m, "\tload: %s\n",
+ intel_uc_fw_status_repr(huc_fw->load_status));
+ seq_printf(m, "\tversion wanted: %d.%d\n",
+ huc_fw->major_ver_wanted, huc_fw->minor_ver_wanted);
+ seq_printf(m, "\tversion found: %d.%d\n",
+ huc_fw->major_ver_found, huc_fw->minor_ver_found);
+ seq_printf(m, "\theader: offset is %d; size = %d\n",
+ huc_fw->header_offset, huc_fw->header_size);
+ seq_printf(m, "\tuCode: offset is %d; size = %d\n",
+ huc_fw->ucode_offset, huc_fw->ucode_size);
+ seq_printf(m, "\tRSA: offset is %d; size = %d\n",
+ huc_fw->rsa_offset, huc_fw->rsa_size);
+
+ seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2));
+
+ return 0;
+}
+
static int i915_guc_load_status_info(struct seq_file *m, void *data)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -4427,6 +4457,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_guc_info", i915_guc_info, 0},
{"i915_guc_load_status", i915_guc_load_status_info, 0},
{"i915_guc_log_dump", i915_guc_log_dump, 0},
+ {"i915_huc_load_status", i915_huc_load_status_info, 0},
{"i915_frequency_info", i915_frequency_info, 0},
{"i915_hangcheck_info", i915_hangcheck_info, 0},
{"i915_drpc_info", i915_drpc_info, 0},
--
2.7.4
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^ permalink raw reply related [flat|nested] 35+ messages in thread* Re: [PATCH 4/8] drm/i915/huc: Add debugfs for HuC loading status check
2016-10-03 18:42 ` [PATCH 4/8] drm/i915/huc: Add debugfs for HuC loading status check Anusha Srivatsa
@ 2016-10-13 17:49 ` Jeff McGee
2016-10-24 23:48 ` Carlos Santa
2016-10-25 22:14 ` Carlos Santa
2 siblings, 0 replies; 35+ messages in thread
From: Jeff McGee @ 2016-10-13 17:49 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
Reviewed-by: Jeff McGee <jeff.mcgee@intel.com>
On Mon, Oct 03, 2016 at 11:42:58AM -0700, Anusha Srivatsa wrote:
> From: Peter Antoine <peter.antoine@intel.com>
>
> Add debugfs entry for HuC loading status check.
>
> v2: rebase on-top of drm-intel-nightly.
> v3: rebased again.
> v7: rebased.
> v8: rebased.
>
> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 31 +++++++++++++++++++++++++++++++
> 1 file changed, 31 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 44258a8..7bd0e23 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2413,6 +2413,36 @@ static int i915_llc(struct seq_file *m, void *data)
> return 0;
> }
>
> +static int i915_huc_load_status_info(struct seq_file *m, void *data)
> +{
> + struct drm_i915_private *dev_priv = node_to_i915(m->private);
> + struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
> +
> + if (!HAS_HUC_UCODE(dev_priv))
> + return 0;
> +
> + seq_puts(m, "HuC firmware status:\n");
> + seq_printf(m, "\tpath: %s\n", huc_fw->uc_fw_path);
> + seq_printf(m, "\tfetch: %s\n",
> + intel_uc_fw_status_repr(huc_fw->fetch_status));
> + seq_printf(m, "\tload: %s\n",
> + intel_uc_fw_status_repr(huc_fw->load_status));
> + seq_printf(m, "\tversion wanted: %d.%d\n",
> + huc_fw->major_ver_wanted, huc_fw->minor_ver_wanted);
> + seq_printf(m, "\tversion found: %d.%d\n",
> + huc_fw->major_ver_found, huc_fw->minor_ver_found);
> + seq_printf(m, "\theader: offset is %d; size = %d\n",
> + huc_fw->header_offset, huc_fw->header_size);
> + seq_printf(m, "\tuCode: offset is %d; size = %d\n",
> + huc_fw->ucode_offset, huc_fw->ucode_size);
> + seq_printf(m, "\tRSA: offset is %d; size = %d\n",
> + huc_fw->rsa_offset, huc_fw->rsa_size);
> +
> + seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2));
> +
> + return 0;
> +}
> +
> static int i915_guc_load_status_info(struct seq_file *m, void *data)
> {
> struct drm_i915_private *dev_priv = node_to_i915(m->private);
> @@ -4427,6 +4457,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
> {"i915_guc_info", i915_guc_info, 0},
> {"i915_guc_load_status", i915_guc_load_status_info, 0},
> {"i915_guc_log_dump", i915_guc_log_dump, 0},
> + {"i915_huc_load_status", i915_huc_load_status_info, 0},
> {"i915_frequency_info", i915_frequency_info, 0},
> {"i915_hangcheck_info", i915_hangcheck_info, 0},
> {"i915_drpc_info", i915_drpc_info, 0},
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [PATCH 4/8] drm/i915/huc: Add debugfs for HuC loading status check
2016-10-03 18:42 ` [PATCH 4/8] drm/i915/huc: Add debugfs for HuC loading status check Anusha Srivatsa
2016-10-13 17:49 ` Jeff McGee
@ 2016-10-24 23:48 ` Carlos Santa
2016-10-25 22:14 ` Carlos Santa
2 siblings, 0 replies; 35+ messages in thread
From: Carlos Santa @ 2016-10-24 23:48 UTC (permalink / raw)
To: Anusha Srivatsa, intel-gfx
Tested with HuC version 1.07.1398 on SKL.
Reviewed-by: Carlos Santa <carlos.santa@intel.com>
Tested-by: Carlos Santa <carlos.santa@intel.com>
On Mon, 2016-10-03 at 11:42 -0700, Anusha Srivatsa wrote:
> From: Peter Antoine <peter.antoine@intel.com>
>
> Add debugfs entry for HuC loading status check.
>
> v2: rebase on-top of drm-intel-nightly.
> v3: rebased again.
> v7: rebased.
> v8: rebased.
>
> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 31
> +++++++++++++++++++++++++++++++
> 1 file changed, 31 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 44258a8..7bd0e23 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2413,6 +2413,36 @@ static int i915_llc(struct seq_file *m, void
> *data)
> return 0;
> }
>
> +static int i915_huc_load_status_info(struct seq_file *m, void *data)
> +{
> + struct drm_i915_private *dev_priv = node_to_i915(m-
> >private);
> + struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
> +
> + if (!HAS_HUC_UCODE(dev_priv))
> + return 0;
> +
> + seq_puts(m, "HuC firmware status:\n");
> + seq_printf(m, "\tpath: %s\n", huc_fw->uc_fw_path);
> + seq_printf(m, "\tfetch: %s\n",
> + intel_uc_fw_status_repr(huc_fw->fetch_status));
> + seq_printf(m, "\tload: %s\n",
> + intel_uc_fw_status_repr(huc_fw->load_status));
> + seq_printf(m, "\tversion wanted: %d.%d\n",
> + huc_fw->major_ver_wanted, huc_fw->minor_ver_wanted);
> + seq_printf(m, "\tversion found: %d.%d\n",
> + huc_fw->major_ver_found, huc_fw->minor_ver_found);
> + seq_printf(m, "\theader: offset is %d; size = %d\n",
> + huc_fw->header_offset, huc_fw->header_size);
> + seq_printf(m, "\tuCode: offset is %d; size = %d\n",
> + huc_fw->ucode_offset, huc_fw->ucode_size);
> + seq_printf(m, "\tRSA: offset is %d; size = %d\n",
> + huc_fw->rsa_offset, huc_fw->rsa_size);
> +
> + seq_printf(m, "\nHuC status 0x%08x:\n",
> I915_READ(HUC_STATUS2));
> +
> + return 0;
> +}
> +
> static int i915_guc_load_status_info(struct seq_file *m, void *data)
> {
> struct drm_i915_private *dev_priv = node_to_i915(m-
> >private);
> @@ -4427,6 +4457,7 @@ static const struct drm_info_list
> i915_debugfs_list[] = {
> {"i915_guc_info", i915_guc_info, 0},
> {"i915_guc_load_status", i915_guc_load_status_info, 0},
> {"i915_guc_log_dump", i915_guc_log_dump, 0},
> + {"i915_huc_load_status", i915_huc_load_status_info, 0},
> {"i915_frequency_info", i915_frequency_info, 0},
> {"i915_hangcheck_info", i915_hangcheck_info, 0},
> {"i915_drpc_info", i915_drpc_info, 0},
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^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [PATCH 4/8] drm/i915/huc: Add debugfs for HuC loading status check
2016-10-03 18:42 ` [PATCH 4/8] drm/i915/huc: Add debugfs for HuC loading status check Anusha Srivatsa
2016-10-13 17:49 ` Jeff McGee
2016-10-24 23:48 ` Carlos Santa
@ 2016-10-25 22:14 ` Carlos Santa
2 siblings, 0 replies; 35+ messages in thread
From: Carlos Santa @ 2016-10-25 22:14 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
Tested with HuC version 1.07.1398 on SKL.
Reviewed-by: Carlos Santa <carlos.santa@intel.com>
Tested-by: Carlos Santa <carlos.santa@intel.com>
On Mon, 2016-10-03 at 11:42 -0700, Anusha Srivatsa wrote:
> From: Peter Antoine <peter.antoine@intel.com>
>
> Add debugfs entry for HuC loading status check.
>
> v2: rebase on-top of drm-intel-nightly.
> v3: rebased again.
> v7: rebased.
> v8: rebased.
>
> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 31
> +++++++++++++++++++++++++++++++
> 1 file changed, 31 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 44258a8..7bd0e23 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2413,6 +2413,36 @@ static int i915_llc(struct seq_file *m, void
> *data)
> return 0;
> }
>
> +static int i915_huc_load_status_info(struct seq_file *m, void *data)
> +{
> + struct drm_i915_private *dev_priv = node_to_i915(m-
> >private);
> + struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
> +
> + if (!HAS_HUC_UCODE(dev_priv))
> + return 0;
> +
> + seq_puts(m, "HuC firmware status:\n");
> + seq_printf(m, "\tpath: %s\n", huc_fw->uc_fw_path);
> + seq_printf(m, "\tfetch: %s\n",
> + intel_uc_fw_status_repr(huc_fw->fetch_status));
> + seq_printf(m, "\tload: %s\n",
> + intel_uc_fw_status_repr(huc_fw->load_status));
> + seq_printf(m, "\tversion wanted: %d.%d\n",
> + huc_fw->major_ver_wanted, huc_fw->minor_ver_wanted);
> + seq_printf(m, "\tversion found: %d.%d\n",
> + huc_fw->major_ver_found, huc_fw->minor_ver_found);
> + seq_printf(m, "\theader: offset is %d; size = %d\n",
> + huc_fw->header_offset, huc_fw->header_size);
> + seq_printf(m, "\tuCode: offset is %d; size = %d\n",
> + huc_fw->ucode_offset, huc_fw->ucode_size);
> + seq_printf(m, "\tRSA: offset is %d; size = %d\n",
> + huc_fw->rsa_offset, huc_fw->rsa_size);
> +
> + seq_printf(m, "\nHuC status 0x%08x:\n",
> I915_READ(HUC_STATUS2));
> +
> + return 0;
> +}
> +
> static int i915_guc_load_status_info(struct seq_file *m, void *data)
> {
> struct drm_i915_private *dev_priv = node_to_i915(m-
> >private);
> @@ -4427,6 +4457,7 @@ static const struct drm_info_list
> i915_debugfs_list[] = {
> {"i915_guc_info", i915_guc_info, 0},
> {"i915_guc_load_status", i915_guc_load_status_info, 0},
> {"i915_guc_log_dump", i915_guc_log_dump, 0},
> + {"i915_huc_load_status", i915_huc_load_status_info, 0},
> {"i915_frequency_info", i915_frequency_info, 0},
> {"i915_hangcheck_info", i915_hangcheck_info, 0},
> {"i915_drpc_info", i915_drpc_info, 0},
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^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH 5/8] drm/i915/huc: Support HuC authentication
2016-10-03 18:42 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa
` (3 preceding siblings ...)
2016-10-03 18:42 ` [PATCH 4/8] drm/i915/huc: Add debugfs for HuC loading status check Anusha Srivatsa
@ 2016-10-03 18:42 ` Anusha Srivatsa
2016-10-13 21:34 ` Jeff McGee
` (2 more replies)
2016-10-03 18:43 ` [PATCH 6/8] drm/i915/huc: Add BXT HuC Loading Support Anusha Srivatsa
` (4 subsequent siblings)
9 siblings, 3 replies; 35+ messages in thread
From: Anusha Srivatsa @ 2016-10-03 18:42 UTC (permalink / raw)
To: intel-gfx
From: Peter Antoine <peter.antoine@intel.com>
The HuC authentication is done by host2guc call. The HuC RSA keys
are sent to GuC for authentication.
v2: rebased on top of drm-intel-nightly.
changed name format and upped version 1.7.
v3: rebased on top of drm-intel-nightly.
v4: changed wait_for_automic to wait_for
v5: rebased.
v7: rebased.
v8: rebased.
Tested-by: Xiang Haihao <haihao.xiang@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
---
drivers/gpu/drm/i915/i915_guc_submission.c | 65 ++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_guc_fwif.h | 1 +
drivers/gpu/drm/i915/intel_guc_loader.c | 2 +
3 files changed, 68 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index 4b92943..984b529 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -25,6 +25,7 @@
#include <linux/circ_buf.h>
#include "i915_drv.h"
#include "intel_guc.h"
+#include "intel_huc.h"
/**
* DOC: GuC-based command submission
@@ -1110,3 +1111,67 @@ int intel_guc_resume(struct drm_device *dev)
return host2guc_action(guc, data, ARRAY_SIZE(data));
}
+
+/**
+ * intel_huc_auth() - authenticate ucode
+ * @dev: the drm device
+ *
+ * Triggers a HuC fw authentication request to the GuC via host-2-guc
+ * interface.
+ */
+void intel_huc_auth(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_guc *guc = &dev_priv->guc;
+ struct intel_huc *huc = &dev_priv->huc;
+ struct i915_vma *vma;
+ int ret;
+ u32 data[2];
+
+ /* Bypass the case where there is no HuC firmware */
+ if (huc->huc_fw.fetch_status == UC_FIRMWARE_NONE ||
+ huc->huc_fw.load_status == UC_FIRMWARE_NONE)
+ return;
+
+ if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS) {
+ DRM_ERROR("HuC: GuC fw wasn't loaded. Can't authenticate");
+ return;
+ }
+
+ if (huc->huc_fw.load_status != UC_FIRMWARE_SUCCESS) {
+ DRM_ERROR("HuC: fw wasn't loaded. Nothing to authenticate");
+ return;
+ }
+
+ vma = i915_gem_object_ggtt_pin(huc->huc_fw.uc_fw_obj, NULL, 0, 0, 0);
+ if (IS_ERR(vma)) {
+ DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
+ return;
+ }
+
+
+ /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
+ I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
+
+ /* Specify auth action and where public signature is. It's stored
+ * at the beginning of the gem object, before the fw bits
+ */
+ data[0] = HOST2GUC_ACTION_AUTHENTICATE_HUC;
+ data[1] = i915_ggtt_offset(vma) + huc->huc_fw.rsa_offset;
+
+ ret = host2guc_action(guc, data, ARRAY_SIZE(data));
+ if (ret) {
+ DRM_ERROR("HuC: GuC did not ack Auth request\n");
+ goto out;
+ }
+
+ /* Check authentication status, it should be done by now */
+ ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0, 50);
+ if (ret) {
+ DRM_ERROR("HuC: Authentication failed\n");
+ goto out;
+ }
+
+out:
+ i915_vma_unpin(vma);
+}
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index b38b6b4..57e6466 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -438,6 +438,7 @@ enum host2guc_action {
HOST2GUC_ACTION_ENTER_S_STATE = 0x501,
HOST2GUC_ACTION_EXIT_S_STATE = 0x502,
HOST2GUC_ACTION_SLPC_REQUEST = 0x3003,
+ HOST2GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
HOST2GUC_ACTION_LIMIT
};
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 0d214b4..31a2b0a 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -527,6 +527,8 @@ int intel_guc_setup(struct drm_device *dev)
intel_uc_fw_status_repr(guc_fw->fetch_status),
intel_uc_fw_status_repr(guc_fw->load_status));
+ intel_huc_auth(dev);
+
if (i915.enable_guc_submission) {
err = i915_guc_submission_enable(dev_priv);
if (err)
--
2.7.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 35+ messages in thread* Re: [PATCH 5/8] drm/i915/huc: Support HuC authentication
2016-10-03 18:42 ` [PATCH 5/8] drm/i915/huc: Support HuC authentication Anusha Srivatsa
@ 2016-10-13 21:34 ` Jeff McGee
2016-10-26 0:49 ` Carlos Santa
2016-10-26 1:00 ` Carlos Santa
2 siblings, 0 replies; 35+ messages in thread
From: Jeff McGee @ 2016-10-13 21:34 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
On Mon, Oct 03, 2016 at 11:42:59AM -0700, Anusha Srivatsa wrote:
> From: Peter Antoine <peter.antoine@intel.com>
>
> The HuC authentication is done by host2guc call. The HuC RSA keys
> are sent to GuC for authentication.
>
> v2: rebased on top of drm-intel-nightly.
> changed name format and upped version 1.7.
> v3: rebased on top of drm-intel-nightly.
> v4: changed wait_for_automic to wait_for
> v5: rebased.
> v7: rebased.
> v8: rebased.
>
> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
> ---
> drivers/gpu/drm/i915/i915_guc_submission.c | 65 ++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_guc_fwif.h | 1 +
> drivers/gpu/drm/i915/intel_guc_loader.c | 2 +
> 3 files changed, 68 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
> index 4b92943..984b529 100644
> --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> @@ -25,6 +25,7 @@
> #include <linux/circ_buf.h>
> #include "i915_drv.h"
> #include "intel_guc.h"
> +#include "intel_huc.h"
>
> /**
> * DOC: GuC-based command submission
> @@ -1110,3 +1111,67 @@ int intel_guc_resume(struct drm_device *dev)
>
> return host2guc_action(guc, data, ARRAY_SIZE(data));
> }
> +
> +/**
> + * intel_huc_auth() - authenticate ucode
> + * @dev: the drm device
> + *
> + * Triggers a HuC fw authentication request to the GuC via host-2-guc
> + * interface.
> + */
> +void intel_huc_auth(struct drm_device *dev)
This function is primarily a guc action and must be in i915_guc_submission.c
to use the static host2guc call. I think it would be clearer to name the
function intel_guc_auth_huc and place the prototype in intel_guc.h instead
of intel_huc.h where other wrappers of host2guc are prototyped.
> +{
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_guc *guc = &dev_priv->guc;
> + struct intel_huc *huc = &dev_priv->huc;
> + struct i915_vma *vma;
> + int ret;
> + u32 data[2];
> +
> + /* Bypass the case where there is no HuC firmware */
> + if (huc->huc_fw.fetch_status == UC_FIRMWARE_NONE ||
> + huc->huc_fw.load_status == UC_FIRMWARE_NONE)
> + return;
> +
> + if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS) {
> + DRM_ERROR("HuC: GuC fw wasn't loaded. Can't authenticate");
> + return;
> + }
> +
> + if (huc->huc_fw.load_status != UC_FIRMWARE_SUCCESS) {
> + DRM_ERROR("HuC: fw wasn't loaded. Nothing to authenticate");
> + return;
> + }
> +
> + vma = i915_gem_object_ggtt_pin(huc->huc_fw.uc_fw_obj, NULL, 0, 0, 0);
> + if (IS_ERR(vma)) {
> + DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
> + return;
> + }
> +
> +
> + /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
> + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
> +
> + /* Specify auth action and where public signature is. It's stored
> + * at the beginning of the gem object, before the fw bits
Second sentence is wrong. RSA offset is after header and ucode. Please
just remove this sentence.
> + */
> + data[0] = HOST2GUC_ACTION_AUTHENTICATE_HUC;
> + data[1] = i915_ggtt_offset(vma) + huc->huc_fw.rsa_offset;
> +
> + ret = host2guc_action(guc, data, ARRAY_SIZE(data));
> + if (ret) {
> + DRM_ERROR("HuC: GuC did not ack Auth request\n");
> + goto out;
> + }
> +
> + /* Check authentication status, it should be done by now */
> + ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0, 50);
> + if (ret) {
> + DRM_ERROR("HuC: Authentication failed\n");
> + goto out;
> + }
> +
> +out:
> + i915_vma_unpin(vma);
> +}
> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
> index b38b6b4..57e6466 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> @@ -438,6 +438,7 @@ enum host2guc_action {
> HOST2GUC_ACTION_ENTER_S_STATE = 0x501,
> HOST2GUC_ACTION_EXIT_S_STATE = 0x502,
> HOST2GUC_ACTION_SLPC_REQUEST = 0x3003,
> + HOST2GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
> HOST2GUC_ACTION_LIMIT
> };
>
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 0d214b4..31a2b0a 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -527,6 +527,8 @@ int intel_guc_setup(struct drm_device *dev)
> intel_uc_fw_status_repr(guc_fw->fetch_status),
> intel_uc_fw_status_repr(guc_fw->load_status));
>
> + intel_huc_auth(dev);
> +
> if (i915.enable_guc_submission) {
> err = i915_guc_submission_enable(dev_priv);
> if (err)
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [PATCH 5/8] drm/i915/huc: Support HuC authentication
2016-10-03 18:42 ` [PATCH 5/8] drm/i915/huc: Support HuC authentication Anusha Srivatsa
2016-10-13 21:34 ` Jeff McGee
@ 2016-10-26 0:49 ` Carlos Santa
2016-10-26 1:00 ` Carlos Santa
2 siblings, 0 replies; 35+ messages in thread
From: Carlos Santa @ 2016-10-26 0:49 UTC (permalink / raw)
To: Anusha Srivatsa, intel-gfx, jeff.mcgee
On Mon, 2016-10-03 at 11:42 -0700, Anusha Srivatsa wrote:
> From: Peter Antoine <peter.antoine@intel.com>
>
> The HuC authentication is done by host2guc call. The HuC RSA keys
> are sent to GuC for authentication.
>
> v2: rebased on top of drm-intel-nightly.
> changed name format and upped version 1.7.
> v3: rebased on top of drm-intel-nightly.
> v4: changed wait_for_automic to wait_for
> v5: rebased.
> v7: rebased.
> v8: rebased.
>
> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
> ---
> drivers/gpu/drm/i915/i915_guc_submission.c | 65
> ++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_guc_fwif.h | 1 +
> drivers/gpu/drm/i915/intel_guc_loader.c | 2 +
> 3 files changed, 68 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
> b/drivers/gpu/drm/i915/i915_guc_submission.c
> index 4b92943..984b529 100644
> --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> @@ -25,6 +25,7 @@
> #include <linux/circ_buf.h>
> #include "i915_drv.h"
> #include "intel_guc.h"
> +#include "intel_huc.h"
>
> /**
> * DOC: GuC-based command submission
> @@ -1110,3 +1111,67 @@ int intel_guc_resume(struct drm_device *dev)
>
> return host2guc_action(guc, data, ARRAY_SIZE(data));
> }
> +
> +/**
> + * intel_huc_auth() - authenticate ucode
> + * @dev: the drm device
> + *
> + * Triggers a HuC fw authentication request to the GuC via host-2-
> guc
> + * interface.
> + */
> +void intel_huc_auth(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_guc *guc = &dev_priv->guc;
> + struct intel_huc *huc = &dev_priv->huc;
> + struct i915_vma *vma;
> + int ret;
> + u32 data[2];
> +
> + /* Bypass the case where there is no HuC firmware */
> + if (huc->huc_fw.fetch_status == UC_FIRMWARE_NONE ||
> + huc->huc_fw.load_status == UC_FIRMWARE_NONE)
> + return;
> +
> + if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS) {
> + DRM_ERROR("HuC: GuC fw wasn't loaded. Can't
> authenticate");
> + return;
> + }
> +
> + if (huc->huc_fw.load_status != UC_FIRMWARE_SUCCESS) {
> + DRM_ERROR("HuC: fw wasn't loaded. Nothing to
> authenticate");
> + return;
> + }
> +
> + vma = i915_gem_object_ggtt_pin(huc->huc_fw.uc_fw_obj, NULL,
> 0, 0, 0);
> + if (IS_ERR(vma)) {
> + DRM_DEBUG_DRIVER("pin failed %d\n",
> (int)PTR_ERR(vma));
> + return;
> + }
> +
> +
> + /* Invalidate GuC TLB to let GuC take the latest updates to
> GTT. */
> + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
> +
> + /* Specify auth action and where public signature is. It's
> stored
> + * at the beginning of the gem object, before the fw bits
> + */
> + data[0] = HOST2GUC_ACTION_AUTHENTICATE_HUC;
> + data[1] = i915_ggtt_offset(vma) + huc->huc_fw.rsa_offset;
> +
> + ret = host2guc_action(guc, data, ARRAY_SIZE(data));
> + if (ret) {
> + DRM_ERROR("HuC: GuC did not ack Auth request\n");
> + goto out;
> + }
> +
> + /* Check authentication status, it should be done by now */
> + ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) >
> 0, 50);
> + if (ret) {
> + DRM_ERROR("HuC: Authentication failed\n");
> + goto out;
> + }
> +
> +out:
> + i915_vma_unpin(vma);
> +}
> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
> b/drivers/gpu/drm/i915/intel_guc_fwif.h
> index b38b6b4..57e6466 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> @@ -438,6 +438,7 @@ enum host2guc_action {
> HOST2GUC_ACTION_ENTER_S_STATE = 0x501,
> HOST2GUC_ACTION_EXIT_S_STATE = 0x502,
> HOST2GUC_ACTION_SLPC_REQUEST = 0x3003,
> + HOST2GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
> HOST2GUC_ACTION_LIMIT
> };
>
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
> b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 0d214b4..31a2b0a 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -527,6 +527,8 @@ int intel_guc_setup(struct drm_device *dev)
> intel_uc_fw_status_repr(guc_fw->fetch_status),
> intel_uc_fw_status_repr(guc_fw->load_status));
>
> + intel_huc_auth(dev);
> +
Shouldn't intel_huc_auth() be returning a meaningful error value
instead of void?
Carlos
> if (i915.enable_guc_submission) {
> err = i915_guc_submission_enable(dev_priv);
> if (err)
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [PATCH 5/8] drm/i915/huc: Support HuC authentication
2016-10-03 18:42 ` [PATCH 5/8] drm/i915/huc: Support HuC authentication Anusha Srivatsa
2016-10-13 21:34 ` Jeff McGee
2016-10-26 0:49 ` Carlos Santa
@ 2016-10-26 1:00 ` Carlos Santa
2 siblings, 0 replies; 35+ messages in thread
From: Carlos Santa @ 2016-10-26 1:00 UTC (permalink / raw)
To: Anusha Srivatsa, intel-gfx
On Mon, 2016-10-03 at 11:42 -0700, Anusha Srivatsa wrote:
> From: Peter Antoine <peter.antoine@intel.com>
>
> The HuC authentication is done by host2guc call. The HuC RSA keys
> are sent to GuC for authentication.
>
> v2: rebased on top of drm-intel-nightly.
> changed name format and upped version 1.7.
> v3: rebased on top of drm-intel-nightly.
> v4: changed wait_for_automic to wait_for
> v5: rebased.
> v7: rebased.
> v8: rebased.
>
> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
> ---
> drivers/gpu/drm/i915/i915_guc_submission.c | 65
> ++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_guc_fwif.h | 1 +
> drivers/gpu/drm/i915/intel_guc_loader.c | 2 +
> 3 files changed, 68 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
> b/drivers/gpu/drm/i915/i915_guc_submission.c
> index 4b92943..984b529 100644
> --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> @@ -25,6 +25,7 @@
> #include <linux/circ_buf.h>
> #include "i915_drv.h"
> #include "intel_guc.h"
> +#include "intel_huc.h"
>
> /**
> * DOC: GuC-based command submission
> @@ -1110,3 +1111,67 @@ int intel_guc_resume(struct drm_device *dev)
>
> return host2guc_action(guc, data, ARRAY_SIZE(data));
> }
> +
> +/**
> + * intel_huc_auth() - authenticate ucode
> + * @dev: the drm device
> + *
> + * Triggers a HuC fw authentication request to the GuC via host-2-
> guc
> + * interface.
> + */
> +void intel_huc_auth(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_guc *guc = &dev_priv->guc;
> + struct intel_huc *huc = &dev_priv->huc;
> + struct i915_vma *vma;
> + int ret;
> + u32 data[2];
> +
> + /* Bypass the case where there is no HuC firmware */
> + if (huc->huc_fw.fetch_status == UC_FIRMWARE_NONE ||
> + huc->huc_fw.load_status == UC_FIRMWARE_NONE)
> + return;
> +
> + if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS) {
> + DRM_ERROR("HuC: GuC fw wasn't loaded. Can't
> authenticate");
> + return;
> + }
> +
> + if (huc->huc_fw.load_status != UC_FIRMWARE_SUCCESS) {
> + DRM_ERROR("HuC: fw wasn't loaded. Nothing to
> authenticate");
> + return;
> + }
> +
> + vma = i915_gem_object_ggtt_pin(huc->huc_fw.uc_fw_obj, NULL,
> 0, 0, 0);
> + if (IS_ERR(vma)) {
> + DRM_DEBUG_DRIVER("pin failed %d\n",
> (int)PTR_ERR(vma));
> + return;
> + }
> +
> +
> + /* Invalidate GuC TLB to let GuC take the latest updates to
> GTT. */
> + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
> +
> + /* Specify auth action and where public signature is. It's
> stored
> + * at the beginning of the gem object, before the fw bits
> + */
> + data[0] = HOST2GUC_ACTION_AUTHENTICATE_HUC;
> + data[1] = i915_ggtt_offset(vma) + huc->huc_fw.rsa_offset;
> +
> + ret = host2guc_action(guc, data, ARRAY_SIZE(data));
> + if (ret) {
> + DRM_ERROR("HuC: GuC did not ack Auth request\n");
> + goto out;
> + }
> +
> + /* Check authentication status, it should be done by now */
> + ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) >
> 0, 50);
> + if (ret) {
> + DRM_ERROR("HuC: Authentication failed\n");
> + goto out;
> + }
> +
> +out:
> + i915_vma_unpin(vma);
> +}
> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
> b/drivers/gpu/drm/i915/intel_guc_fwif.h
> index b38b6b4..57e6466 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> @@ -438,6 +438,7 @@ enum host2guc_action {
> HOST2GUC_ACTION_ENTER_S_STATE = 0x501,
> HOST2GUC_ACTION_EXIT_S_STATE = 0x502,
> HOST2GUC_ACTION_SLPC_REQUEST = 0x3003,
> + HOST2GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
> HOST2GUC_ACTION_LIMIT
> };
>
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
> b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 0d214b4..31a2b0a 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -527,6 +527,8 @@ int intel_guc_setup(struct drm_device *dev)
> intel_uc_fw_status_repr(guc_fw->fetch_status),
> intel_uc_fw_status_repr(guc_fw->load_status));
>
> + intel_huc_auth(dev);
> +
Shouldn't intel_huc_auth() be returning a meaningful error value
instead of void?
Carlos
> if (i915.enable_guc_submission) {
> err = i915_guc_submission_enable(dev_priv);
> if (err)
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^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH 6/8] drm/i915/huc: Add BXT HuC Loading Support
2016-10-03 18:42 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa
` (4 preceding siblings ...)
2016-10-03 18:42 ` [PATCH 5/8] drm/i915/huc: Support HuC authentication Anusha Srivatsa
@ 2016-10-03 18:43 ` Anusha Srivatsa
2016-10-13 21:36 ` Jeff McGee
2016-10-03 18:43 ` [PATCH 7/8] drm/i915/get_params: Add GuC status to getparams Anusha Srivatsa
` (3 subsequent siblings)
9 siblings, 1 reply; 35+ messages in thread
From: Anusha Srivatsa @ 2016-10-03 18:43 UTC (permalink / raw)
To: intel-gfx
From: Peter Antoine <peter.antoine@intel.com>
This patch adds the HuC Loading for the BXT.
Version 1.7 of the HuC firmware.
v2: rebased.
v3: rebased.
changed file name to match the install package format.
v7: rebased.
v8: rebased.
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
Reviewed-by: David Gordon <david.s.gordon@intel.com>
---
drivers/gpu/drm/i915/intel_huc_loader.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
index 1aaff67..87a6948 100644
--- a/drivers/gpu/drm/i915/intel_huc_loader.c
+++ b/drivers/gpu/drm/i915/intel_huc_loader.c
@@ -50,6 +50,9 @@
#define I915_SKL_HUC_UCODE "i915/skl_huc_ver01_07_1398.bin"
MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
+#define I915_BXT_HUC_UCODE "i915/bxt_huc_ver01_07_1398.bin"
+MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
+
/**
* intel_huc_load_ucode() - DMA's the firmware
* @dev: the drm device
@@ -158,6 +161,10 @@ void intel_huc_init(struct drm_device *dev)
fw_path = I915_SKL_HUC_UCODE;
huc_fw->major_ver_wanted = 1;
huc_fw->minor_ver_wanted = 7;
+ } else if (IS_BROXTON(dev_priv)) {
+ fw_path = I915_BXT_HUC_UCODE;
+ huc_fw->major_ver_wanted = 1;
+ huc_fw->minor_ver_wanted = 7;
}
if (fw_path == NULL)
--
2.7.4
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^ permalink raw reply related [flat|nested] 35+ messages in thread* Re: [PATCH 6/8] drm/i915/huc: Add BXT HuC Loading Support
2016-10-03 18:43 ` [PATCH 6/8] drm/i915/huc: Add BXT HuC Loading Support Anusha Srivatsa
@ 2016-10-13 21:36 ` Jeff McGee
0 siblings, 0 replies; 35+ messages in thread
From: Jeff McGee @ 2016-10-13 21:36 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
On Mon, Oct 03, 2016 at 11:43:00AM -0700, Anusha Srivatsa wrote:
> From: Peter Antoine <peter.antoine@intel.com>
>
> This patch adds the HuC Loading for the BXT.
> Version 1.7 of the HuC firmware.
>
> v2: rebased.
> v3: rebased.
> changed file name to match the install package format.
> v7: rebased.
> v8: rebased.
>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> Reviewed-by: David Gordon <david.s.gordon@intel.com>
> ---
> drivers/gpu/drm/i915/intel_huc_loader.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
> index 1aaff67..87a6948 100644
> --- a/drivers/gpu/drm/i915/intel_huc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_huc_loader.c
> @@ -50,6 +50,9 @@
> #define I915_SKL_HUC_UCODE "i915/skl_huc_ver01_07_1398.bin"
> MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
>
> +#define I915_BXT_HUC_UCODE "i915/bxt_huc_ver01_07_1398.bin"
> +MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
> +
This will need updating if the newer firmware version/name macros in
intel_guc_loader.c are adopted.
> /**
> * intel_huc_load_ucode() - DMA's the firmware
> * @dev: the drm device
> @@ -158,6 +161,10 @@ void intel_huc_init(struct drm_device *dev)
> fw_path = I915_SKL_HUC_UCODE;
> huc_fw->major_ver_wanted = 1;
> huc_fw->minor_ver_wanted = 7;
> + } else if (IS_BROXTON(dev_priv)) {
> + fw_path = I915_BXT_HUC_UCODE;
> + huc_fw->major_ver_wanted = 1;
> + huc_fw->minor_ver_wanted = 7;
> }
>
> if (fw_path == NULL)
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH 7/8] drm/i915/get_params: Add GuC status to getparams
2016-10-03 18:42 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa
` (5 preceding siblings ...)
2016-10-03 18:43 ` [PATCH 6/8] drm/i915/huc: Add BXT HuC Loading Support Anusha Srivatsa
@ 2016-10-03 18:43 ` Anusha Srivatsa
2016-10-05 20:51 ` Rodrigo Vivi
2016-10-03 18:43 ` [PATCH 8/8] drm/i915/get_params: Add HuC " Anusha Srivatsa
` (2 subsequent siblings)
9 siblings, 1 reply; 35+ messages in thread
From: Anusha Srivatsa @ 2016-10-03 18:43 UTC (permalink / raw)
To: intel-gfx
From: Peter Antoine <peter.antoine@intel.com>
This patch returns the GuC status to the caller. It is used so
that the userspace knows if the GuC has been loaded.
v4: rebase.
v5: rebased.
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 4 ++++
drivers/gpu/drm/i915/intel_guc.h | 2 +-
drivers/gpu/drm/i915/intel_guc_loader.c | 18 ++++++++++++++++++
include/uapi/drm/i915_drm.h | 1 +
4 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 7af7bd6..ff1c18d 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -49,6 +49,7 @@
#include "i915_trace.h"
#include "i915_vgpu.h"
#include "intel_drv.h"
+#include "intel_guc.h"
static struct drm_driver driver;
@@ -339,6 +340,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
*/
value = 1;
break;
+ case I915_PARAM_HAS_GUC:
+ value = intel_is_guc_valid(dev_priv);
+ break;
default:
DRM_DEBUG("Unknown parameter %d\n", param->param);
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index af76ffe..3a7fa7e 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -168,5 +168,5 @@ int i915_guc_submission_enable(struct drm_i915_private *dev_priv);
int i915_guc_wq_reserve(struct drm_i915_gem_request *rq);
void i915_guc_submission_disable(struct drm_i915_private *dev_priv);
void i915_guc_submission_fini(struct drm_i915_private *dev_priv);
-
+int intel_is_guc_valid(struct drm_i915_private *dev_priv);
#endif
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 31a2b0a..5d2a703 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -801,3 +801,21 @@ void intel_guc_fini(struct drm_device *dev)
guc_fw->fetch_status = UC_FIRMWARE_NONE;
}
+
+/**
+ * intel_is_guc_valid() - Check to see if the GuC is fully loaded.
+ * @dev: drm dedvice to check.
+ *
+ * This function will return true if the guc has been loaded and
+ * has valid firmware.
+ */
+int intel_is_guc_valid(struct drm_i915_private *dev_priv)
+{
+ struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
+
+ if (guc_fw->load_status == UC_FIRMWARE_SUCCESS)
+ return 1;
+ else
+ return 0;
+}
+
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 03725fe..629fb5e 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -388,6 +388,7 @@ typedef struct drm_i915_irq_wait {
#define I915_PARAM_HAS_POOLED_EU 38
#define I915_PARAM_MIN_EU_IN_POOL 39
#define I915_PARAM_MMAP_GTT_VERSION 40
+#define I915_PARAM_HAS_GUC 41
typedef struct drm_i915_getparam {
__s32 param;
--
2.7.4
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 35+ messages in thread* Re: [PATCH 7/8] drm/i915/get_params: Add GuC status to getparams
2016-10-03 18:43 ` [PATCH 7/8] drm/i915/get_params: Add GuC status to getparams Anusha Srivatsa
@ 2016-10-05 20:51 ` Rodrigo Vivi
2016-10-07 7:11 ` Daniel Vetter
0 siblings, 1 reply; 35+ messages in thread
From: Rodrigo Vivi @ 2016-10-05 20:51 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
On Mon, Oct 03, 2016 at 11:43:01AM -0700, Anusha Srivatsa wrote:
> From: Peter Antoine <peter.antoine@intel.com>
>
> This patch returns the GuC status to the caller. It is used so
> that the userspace knows if the GuC has been loaded.
>
> v4: rebase.
> v5: rebased.
>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 4 ++++
> drivers/gpu/drm/i915/intel_guc.h | 2 +-
> drivers/gpu/drm/i915/intel_guc_loader.c | 18 ++++++++++++++++++
> include/uapi/drm/i915_drm.h | 1 +
> 4 files changed, 24 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 7af7bd6..ff1c18d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -49,6 +49,7 @@
> #include "i915_trace.h"
> #include "i915_vgpu.h"
> #include "intel_drv.h"
> +#include "intel_guc.h"
>
> static struct drm_driver driver;
>
> @@ -339,6 +340,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
> */
> value = 1;
> break;
> + case I915_PARAM_HAS_GUC:
> + value = intel_is_guc_valid(dev_priv);
> + break;
> default:
> DRM_DEBUG("Unknown parameter %d\n", param->param);
> return -EINVAL;
> diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
> index af76ffe..3a7fa7e 100644
> --- a/drivers/gpu/drm/i915/intel_guc.h
> +++ b/drivers/gpu/drm/i915/intel_guc.h
> @@ -168,5 +168,5 @@ int i915_guc_submission_enable(struct drm_i915_private *dev_priv);
> int i915_guc_wq_reserve(struct drm_i915_gem_request *rq);
> void i915_guc_submission_disable(struct drm_i915_private *dev_priv);
> void i915_guc_submission_fini(struct drm_i915_private *dev_priv);
> -
> +int intel_is_guc_valid(struct drm_i915_private *dev_priv);
> #endif
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 31a2b0a..5d2a703 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -801,3 +801,21 @@ void intel_guc_fini(struct drm_device *dev)
>
> guc_fw->fetch_status = UC_FIRMWARE_NONE;
> }
> +
> +/**
> + * intel_is_guc_valid() - Check to see if the GuC is fully loaded.
> + * @dev: drm dedvice to check.
> + *
> + * This function will return true if the guc has been loaded and
> + * has valid firmware.
> + */
> +int intel_is_guc_valid(struct drm_i915_private *dev_priv)
> +{
> + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> +
> + if (guc_fw->load_status == UC_FIRMWARE_SUCCESS)
> + return 1;
> + else
> + return 0;
> +}
> +
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 03725fe..629fb5e 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -388,6 +388,7 @@ typedef struct drm_i915_irq_wait {
> #define I915_PARAM_HAS_POOLED_EU 38
> #define I915_PARAM_MIN_EU_IN_POOL 39
> #define I915_PARAM_MMAP_GTT_VERSION 40
> +#define I915_PARAM_HAS_GUC 41
>
> typedef struct drm_i915_getparam {
> __s32 param;
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [PATCH 7/8] drm/i915/get_params: Add GuC status to getparams
2016-10-05 20:51 ` Rodrigo Vivi
@ 2016-10-07 7:11 ` Daniel Vetter
2016-10-13 21:42 ` Jeff McGee
0 siblings, 1 reply; 35+ messages in thread
From: Daniel Vetter @ 2016-10-07 7:11 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
On Wed, Oct 05, 2016 at 01:51:14PM -0700, Rodrigo Vivi wrote:
>
>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This is new uabi. Where's the userspace?
Checking this is part of the review.
-Daniel
>
> On Mon, Oct 03, 2016 at 11:43:01AM -0700, Anusha Srivatsa wrote:
> > From: Peter Antoine <peter.antoine@intel.com>
> >
> > This patch returns the GuC status to the caller. It is used so
> > that the userspace knows if the GuC has been loaded.
> >
> > v4: rebase.
> > v5: rebased.
> >
> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_drv.c | 4 ++++
> > drivers/gpu/drm/i915/intel_guc.h | 2 +-
> > drivers/gpu/drm/i915/intel_guc_loader.c | 18 ++++++++++++++++++
> > include/uapi/drm/i915_drm.h | 1 +
> > 4 files changed, 24 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > index 7af7bd6..ff1c18d 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -49,6 +49,7 @@
> > #include "i915_trace.h"
> > #include "i915_vgpu.h"
> > #include "intel_drv.h"
> > +#include "intel_guc.h"
> >
> > static struct drm_driver driver;
> >
> > @@ -339,6 +340,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
> > */
> > value = 1;
> > break;
> > + case I915_PARAM_HAS_GUC:
> > + value = intel_is_guc_valid(dev_priv);
> > + break;
> > default:
> > DRM_DEBUG("Unknown parameter %d\n", param->param);
> > return -EINVAL;
> > diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
> > index af76ffe..3a7fa7e 100644
> > --- a/drivers/gpu/drm/i915/intel_guc.h
> > +++ b/drivers/gpu/drm/i915/intel_guc.h
> > @@ -168,5 +168,5 @@ int i915_guc_submission_enable(struct drm_i915_private *dev_priv);
> > int i915_guc_wq_reserve(struct drm_i915_gem_request *rq);
> > void i915_guc_submission_disable(struct drm_i915_private *dev_priv);
> > void i915_guc_submission_fini(struct drm_i915_private *dev_priv);
> > -
> > +int intel_is_guc_valid(struct drm_i915_private *dev_priv);
> > #endif
> > diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> > index 31a2b0a..5d2a703 100644
> > --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> > +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> > @@ -801,3 +801,21 @@ void intel_guc_fini(struct drm_device *dev)
> >
> > guc_fw->fetch_status = UC_FIRMWARE_NONE;
> > }
> > +
> > +/**
> > + * intel_is_guc_valid() - Check to see if the GuC is fully loaded.
> > + * @dev: drm dedvice to check.
> > + *
> > + * This function will return true if the guc has been loaded and
> > + * has valid firmware.
> > + */
> > +int intel_is_guc_valid(struct drm_i915_private *dev_priv)
> > +{
> > + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> > +
> > + if (guc_fw->load_status == UC_FIRMWARE_SUCCESS)
> > + return 1;
> > + else
> > + return 0;
> > +}
> > +
> > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> > index 03725fe..629fb5e 100644
> > --- a/include/uapi/drm/i915_drm.h
> > +++ b/include/uapi/drm/i915_drm.h
> > @@ -388,6 +388,7 @@ typedef struct drm_i915_irq_wait {
> > #define I915_PARAM_HAS_POOLED_EU 38
> > #define I915_PARAM_MIN_EU_IN_POOL 39
> > #define I915_PARAM_MMAP_GTT_VERSION 40
> > +#define I915_PARAM_HAS_GUC 41
> >
> > typedef struct drm_i915_getparam {
> > __s32 param;
> > --
> > 2.7.4
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [PATCH 7/8] drm/i915/get_params: Add GuC status to getparams
2016-10-07 7:11 ` Daniel Vetter
@ 2016-10-13 21:42 ` Jeff McGee
2016-10-17 6:49 ` Daniel Vetter
0 siblings, 1 reply; 35+ messages in thread
From: Jeff McGee @ 2016-10-13 21:42 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Fri, Oct 07, 2016 at 09:11:03AM +0200, Daniel Vetter wrote:
> On Wed, Oct 05, 2016 at 01:51:14PM -0700, Rodrigo Vivi wrote:
> >
> >
> > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> This is new uabi. Where's the userspace?
>
> Checking this is part of the review.
> -Daniel
>
I'm not sure that GuC status is strictly needed by userspace. No
direct dependencies that I am aware of. HuC status is needed and that
is the subsequent patch.
-Jeff
> >
> > On Mon, Oct 03, 2016 at 11:43:01AM -0700, Anusha Srivatsa wrote:
> > > From: Peter Antoine <peter.antoine@intel.com>
> > >
> > > This patch returns the GuC status to the caller. It is used so
> > > that the userspace knows if the GuC has been loaded.
> > >
> > > v4: rebase.
> > > v5: rebased.
> > >
> > > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > > Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/i915_drv.c | 4 ++++
> > > drivers/gpu/drm/i915/intel_guc.h | 2 +-
> > > drivers/gpu/drm/i915/intel_guc_loader.c | 18 ++++++++++++++++++
> > > include/uapi/drm/i915_drm.h | 1 +
> > > 4 files changed, 24 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > > index 7af7bd6..ff1c18d 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.c
> > > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > > @@ -49,6 +49,7 @@
> > > #include "i915_trace.h"
> > > #include "i915_vgpu.h"
> > > #include "intel_drv.h"
> > > +#include "intel_guc.h"
> > >
> > > static struct drm_driver driver;
> > >
> > > @@ -339,6 +340,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
> > > */
> > > value = 1;
> > > break;
> > > + case I915_PARAM_HAS_GUC:
> > > + value = intel_is_guc_valid(dev_priv);
> > > + break;
> > > default:
> > > DRM_DEBUG("Unknown parameter %d\n", param->param);
> > > return -EINVAL;
> > > diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
> > > index af76ffe..3a7fa7e 100644
> > > --- a/drivers/gpu/drm/i915/intel_guc.h
> > > +++ b/drivers/gpu/drm/i915/intel_guc.h
> > > @@ -168,5 +168,5 @@ int i915_guc_submission_enable(struct drm_i915_private *dev_priv);
> > > int i915_guc_wq_reserve(struct drm_i915_gem_request *rq);
> > > void i915_guc_submission_disable(struct drm_i915_private *dev_priv);
> > > void i915_guc_submission_fini(struct drm_i915_private *dev_priv);
> > > -
> > > +int intel_is_guc_valid(struct drm_i915_private *dev_priv);
> > > #endif
> > > diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> > > index 31a2b0a..5d2a703 100644
> > > --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> > > +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> > > @@ -801,3 +801,21 @@ void intel_guc_fini(struct drm_device *dev)
> > >
> > > guc_fw->fetch_status = UC_FIRMWARE_NONE;
> > > }
> > > +
> > > +/**
> > > + * intel_is_guc_valid() - Check to see if the GuC is fully loaded.
> > > + * @dev: drm dedvice to check.
> > > + *
> > > + * This function will return true if the guc has been loaded and
> > > + * has valid firmware.
> > > + */
> > > +int intel_is_guc_valid(struct drm_i915_private *dev_priv)
> > > +{
> > > + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> > > +
> > > + if (guc_fw->load_status == UC_FIRMWARE_SUCCESS)
> > > + return 1;
> > > + else
> > > + return 0;
> > > +}
> > > +
> > > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> > > index 03725fe..629fb5e 100644
> > > --- a/include/uapi/drm/i915_drm.h
> > > +++ b/include/uapi/drm/i915_drm.h
> > > @@ -388,6 +388,7 @@ typedef struct drm_i915_irq_wait {
> > > #define I915_PARAM_HAS_POOLED_EU 38
> > > #define I915_PARAM_MIN_EU_IN_POOL 39
> > > #define I915_PARAM_MMAP_GTT_VERSION 40
> > > +#define I915_PARAM_HAS_GUC 41
> > >
> > > typedef struct drm_i915_getparam {
> > > __s32 param;
> > > --
> > > 2.7.4
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [PATCH 7/8] drm/i915/get_params: Add GuC status to getparams
2016-10-13 21:42 ` Jeff McGee
@ 2016-10-17 6:49 ` Daniel Vetter
0 siblings, 0 replies; 35+ messages in thread
From: Daniel Vetter @ 2016-10-17 6:49 UTC (permalink / raw)
To: Jeff McGee; +Cc: intel-gfx
On Thu, Oct 13, 2016 at 02:42:46PM -0700, Jeff McGee wrote:
> On Fri, Oct 07, 2016 at 09:11:03AM +0200, Daniel Vetter wrote:
> > On Wed, Oct 05, 2016 at 01:51:14PM -0700, Rodrigo Vivi wrote:
> > >
> > >
> > > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> >
> > This is new uabi. Where's the userspace?
> >
> > Checking this is part of the review.
> > -Daniel
> >
> I'm not sure that GuC status is strictly needed by userspace. No
> direct dependencies that I am aware of. HuC status is needed and that
> is the subsequent patch.
I'd say we drop this one then.
-Daniel
> -Jeff
>
> > >
> > > On Mon, Oct 03, 2016 at 11:43:01AM -0700, Anusha Srivatsa wrote:
> > > > From: Peter Antoine <peter.antoine@intel.com>
> > > >
> > > > This patch returns the GuC status to the caller. It is used so
> > > > that the userspace knows if the GuC has been loaded.
> > > >
> > > > v4: rebase.
> > > > v5: rebased.
> > > >
> > > > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > > > Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/i915_drv.c | 4 ++++
> > > > drivers/gpu/drm/i915/intel_guc.h | 2 +-
> > > > drivers/gpu/drm/i915/intel_guc_loader.c | 18 ++++++++++++++++++
> > > > include/uapi/drm/i915_drm.h | 1 +
> > > > 4 files changed, 24 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > > > index 7af7bd6..ff1c18d 100644
> > > > --- a/drivers/gpu/drm/i915/i915_drv.c
> > > > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > > > @@ -49,6 +49,7 @@
> > > > #include "i915_trace.h"
> > > > #include "i915_vgpu.h"
> > > > #include "intel_drv.h"
> > > > +#include "intel_guc.h"
> > > >
> > > > static struct drm_driver driver;
> > > >
> > > > @@ -339,6 +340,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
> > > > */
> > > > value = 1;
> > > > break;
> > > > + case I915_PARAM_HAS_GUC:
> > > > + value = intel_is_guc_valid(dev_priv);
> > > > + break;
> > > > default:
> > > > DRM_DEBUG("Unknown parameter %d\n", param->param);
> > > > return -EINVAL;
> > > > diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
> > > > index af76ffe..3a7fa7e 100644
> > > > --- a/drivers/gpu/drm/i915/intel_guc.h
> > > > +++ b/drivers/gpu/drm/i915/intel_guc.h
> > > > @@ -168,5 +168,5 @@ int i915_guc_submission_enable(struct drm_i915_private *dev_priv);
> > > > int i915_guc_wq_reserve(struct drm_i915_gem_request *rq);
> > > > void i915_guc_submission_disable(struct drm_i915_private *dev_priv);
> > > > void i915_guc_submission_fini(struct drm_i915_private *dev_priv);
> > > > -
> > > > +int intel_is_guc_valid(struct drm_i915_private *dev_priv);
> > > > #endif
> > > > diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> > > > index 31a2b0a..5d2a703 100644
> > > > --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> > > > +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> > > > @@ -801,3 +801,21 @@ void intel_guc_fini(struct drm_device *dev)
> > > >
> > > > guc_fw->fetch_status = UC_FIRMWARE_NONE;
> > > > }
> > > > +
> > > > +/**
> > > > + * intel_is_guc_valid() - Check to see if the GuC is fully loaded.
> > > > + * @dev: drm dedvice to check.
> > > > + *
> > > > + * This function will return true if the guc has been loaded and
> > > > + * has valid firmware.
> > > > + */
> > > > +int intel_is_guc_valid(struct drm_i915_private *dev_priv)
> > > > +{
> > > > + struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
> > > > +
> > > > + if (guc_fw->load_status == UC_FIRMWARE_SUCCESS)
> > > > + return 1;
> > > > + else
> > > > + return 0;
> > > > +}
> > > > +
> > > > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> > > > index 03725fe..629fb5e 100644
> > > > --- a/include/uapi/drm/i915_drm.h
> > > > +++ b/include/uapi/drm/i915_drm.h
> > > > @@ -388,6 +388,7 @@ typedef struct drm_i915_irq_wait {
> > > > #define I915_PARAM_HAS_POOLED_EU 38
> > > > #define I915_PARAM_MIN_EU_IN_POOL 39
> > > > #define I915_PARAM_MMAP_GTT_VERSION 40
> > > > +#define I915_PARAM_HAS_GUC 41
> > > >
> > > > typedef struct drm_i915_getparam {
> > > > __s32 param;
> > > > --
> > > > 2.7.4
> > > >
> > > > _______________________________________________
> > > > Intel-gfx mailing list
> > > > Intel-gfx@lists.freedesktop.org
> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> > --
> > Daniel Vetter
> > Software Engineer, Intel Corporation
> > http://blog.ffwll.ch
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams
2016-10-03 18:42 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa
` (6 preceding siblings ...)
2016-10-03 18:43 ` [PATCH 7/8] drm/i915/get_params: Add GuC status to getparams Anusha Srivatsa
@ 2016-10-03 18:43 ` Anusha Srivatsa
2016-10-05 20:51 ` Rodrigo Vivi
2016-10-13 21:47 ` Jeff McGee
2016-10-03 19:19 ` ✗ Fi.CI.BAT: warning for HuC Loading Patches Patchwork
2016-10-07 7:09 ` [PATCH 0/8] " Daniel Vetter
9 siblings, 2 replies; 35+ messages in thread
From: Anusha Srivatsa @ 2016-10-03 18:43 UTC (permalink / raw)
To: intel-gfx
From: Peter Antoine <peter.antoine@intel.com>
This patch will allow for getparams to return the status of the HuC.
As the HuC has to be validated by the GuC this patch uses the validated
status to show when the HuC is loaded and ready for use. You cannot use
the loaded status as with the GuC as the HuC is verified after it is
loaded and is not usable until it is verified.
v2: removed the forewakes as the registers are already force-woken.
(T.Ursulin)
v4: rebased.
v5: rebased.
Tested-by: Xiang Haihao <haihao.xiang@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 4 ++++
drivers/gpu/drm/i915/intel_huc.h | 2 +-
drivers/gpu/drm/i915/intel_huc_loader.c | 14 ++++++++++++++
include/uapi/drm/i915_drm.h | 1 +
4 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index ff1c18d..0d7b290 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -49,6 +49,7 @@
#include "i915_trace.h"
#include "i915_vgpu.h"
#include "intel_drv.h"
+#include "intel_huc.h"
#include "intel_guc.h"
static struct drm_driver driver;
@@ -343,6 +344,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
case I915_PARAM_HAS_GUC:
value = intel_is_guc_valid(dev_priv);
break;
+ case I915_PARAM_HAS_HUC:
+ value = intel_is_huc_valid(dev_priv);
+ break;
default:
DRM_DEBUG("Unknown parameter %d\n", param->param);
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/intel_huc.h b/drivers/gpu/drm/i915/intel_huc.h
index 946caa7..5eac625 100644
--- a/drivers/gpu/drm/i915/intel_huc.h
+++ b/drivers/gpu/drm/i915/intel_huc.h
@@ -40,5 +40,5 @@ extern void intel_huc_init(struct drm_device *dev);
extern int intel_huc_load(struct drm_device *dev);
extern void intel_huc_auth(struct drm_device *dev);
extern void intel_huc_fini(struct drm_device *dev);
-
+extern int intel_is_huc_valid(struct drm_i915_private *dev_priv);
#endif
diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
index 87a6948..d574183 100644
--- a/drivers/gpu/drm/i915/intel_huc_loader.c
+++ b/drivers/gpu/drm/i915/intel_huc_loader.c
@@ -273,3 +273,17 @@ void intel_huc_fini(struct drm_device *dev)
huc_fw->fetch_status = UC_FIRMWARE_NONE;
}
+
+/**
+ * intel_is_huc_valid() - Check to see if the HuC is fully loaded.
+ * @dev_priv: drm device to check.
+ *
+ * This function will return true if the guc has been loaded and
+ * has valid firmware. The simplest way of doing this is to check
+ * if the HuC has been validated, if so it must have been loaded.
+ */
+int intel_is_huc_valid(struct drm_i915_private *dev_priv)
+{
+ return ((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) != 0);
+}
+
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 629fb5e..d236520 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -389,6 +389,7 @@ typedef struct drm_i915_irq_wait {
#define I915_PARAM_MIN_EU_IN_POOL 39
#define I915_PARAM_MMAP_GTT_VERSION 40
#define I915_PARAM_HAS_GUC 41
+#define I915_PARAM_HAS_HUC 42
typedef struct drm_i915_getparam {
__s32 param;
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 35+ messages in thread* Re: [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams
2016-10-03 18:43 ` [PATCH 8/8] drm/i915/get_params: Add HuC " Anusha Srivatsa
@ 2016-10-05 20:51 ` Rodrigo Vivi
2016-10-13 21:47 ` Jeff McGee
1 sibling, 0 replies; 35+ messages in thread
From: Rodrigo Vivi @ 2016-10-05 20:51 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
On Mon, Oct 03, 2016 at 11:43:02AM -0700, Anusha Srivatsa wrote:
> From: Peter Antoine <peter.antoine@intel.com>
>
> This patch will allow for getparams to return the status of the HuC.
> As the HuC has to be validated by the GuC this patch uses the validated
> status to show when the HuC is loaded and ready for use. You cannot use
> the loaded status as with the GuC as the HuC is verified after it is
> loaded and is not usable until it is verified.
>
> v2: removed the forewakes as the registers are already force-woken.
> (T.Ursulin)
> v4: rebased.
> v5: rebased.
>
> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 4 ++++
> drivers/gpu/drm/i915/intel_huc.h | 2 +-
> drivers/gpu/drm/i915/intel_huc_loader.c | 14 ++++++++++++++
> include/uapi/drm/i915_drm.h | 1 +
> 4 files changed, 20 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index ff1c18d..0d7b290 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -49,6 +49,7 @@
> #include "i915_trace.h"
> #include "i915_vgpu.h"
> #include "intel_drv.h"
> +#include "intel_huc.h"
> #include "intel_guc.h"
>
> static struct drm_driver driver;
> @@ -343,6 +344,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
> case I915_PARAM_HAS_GUC:
> value = intel_is_guc_valid(dev_priv);
> break;
> + case I915_PARAM_HAS_HUC:
> + value = intel_is_huc_valid(dev_priv);
> + break;
> default:
> DRM_DEBUG("Unknown parameter %d\n", param->param);
> return -EINVAL;
> diff --git a/drivers/gpu/drm/i915/intel_huc.h b/drivers/gpu/drm/i915/intel_huc.h
> index 946caa7..5eac625 100644
> --- a/drivers/gpu/drm/i915/intel_huc.h
> +++ b/drivers/gpu/drm/i915/intel_huc.h
> @@ -40,5 +40,5 @@ extern void intel_huc_init(struct drm_device *dev);
> extern int intel_huc_load(struct drm_device *dev);
> extern void intel_huc_auth(struct drm_device *dev);
> extern void intel_huc_fini(struct drm_device *dev);
> -
> +extern int intel_is_huc_valid(struct drm_i915_private *dev_priv);
> #endif
> diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
> index 87a6948..d574183 100644
> --- a/drivers/gpu/drm/i915/intel_huc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_huc_loader.c
> @@ -273,3 +273,17 @@ void intel_huc_fini(struct drm_device *dev)
>
> huc_fw->fetch_status = UC_FIRMWARE_NONE;
> }
> +
> +/**
> + * intel_is_huc_valid() - Check to see if the HuC is fully loaded.
> + * @dev_priv: drm device to check.
> + *
> + * This function will return true if the guc has been loaded and
> + * has valid firmware. The simplest way of doing this is to check
> + * if the HuC has been validated, if so it must have been loaded.
> + */
> +int intel_is_huc_valid(struct drm_i915_private *dev_priv)
> +{
> + return ((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) != 0);
> +}
> +
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 629fb5e..d236520 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -389,6 +389,7 @@ typedef struct drm_i915_irq_wait {
> #define I915_PARAM_MIN_EU_IN_POOL 39
> #define I915_PARAM_MMAP_GTT_VERSION 40
> #define I915_PARAM_HAS_GUC 41
> +#define I915_PARAM_HAS_HUC 42
>
> typedef struct drm_i915_getparam {
> __s32 param;
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams
2016-10-03 18:43 ` [PATCH 8/8] drm/i915/get_params: Add HuC " Anusha Srivatsa
2016-10-05 20:51 ` Rodrigo Vivi
@ 2016-10-13 21:47 ` Jeff McGee
2016-10-17 6:48 ` Daniel Vetter
1 sibling, 1 reply; 35+ messages in thread
From: Jeff McGee @ 2016-10-13 21:47 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
On Mon, Oct 03, 2016 at 11:43:02AM -0700, Anusha Srivatsa wrote:
> From: Peter Antoine <peter.antoine@intel.com>
>
> This patch will allow for getparams to return the status of the HuC.
> As the HuC has to be validated by the GuC this patch uses the validated
> status to show when the HuC is loaded and ready for use. You cannot use
> the loaded status as with the GuC as the HuC is verified after it is
> loaded and is not usable until it is verified.
>
> v2: removed the forewakes as the registers are already force-woken.
> (T.Ursulin)
> v4: rebased.
> v5: rebased.
>
> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 4 ++++
> drivers/gpu/drm/i915/intel_huc.h | 2 +-
> drivers/gpu/drm/i915/intel_huc_loader.c | 14 ++++++++++++++
> include/uapi/drm/i915_drm.h | 1 +
> 4 files changed, 20 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index ff1c18d..0d7b290 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -49,6 +49,7 @@
> #include "i915_trace.h"
> #include "i915_vgpu.h"
> #include "intel_drv.h"
> +#include "intel_huc.h"
> #include "intel_guc.h"
>
> static struct drm_driver driver;
> @@ -343,6 +344,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
> case I915_PARAM_HAS_GUC:
> value = intel_is_guc_valid(dev_priv);
> break;
> + case I915_PARAM_HAS_HUC:
> + value = intel_is_huc_valid(dev_priv);
> + break;
> default:
> DRM_DEBUG("Unknown parameter %d\n", param->param);
> return -EINVAL;
> diff --git a/drivers/gpu/drm/i915/intel_huc.h b/drivers/gpu/drm/i915/intel_huc.h
> index 946caa7..5eac625 100644
> --- a/drivers/gpu/drm/i915/intel_huc.h
> +++ b/drivers/gpu/drm/i915/intel_huc.h
> @@ -40,5 +40,5 @@ extern void intel_huc_init(struct drm_device *dev);
> extern int intel_huc_load(struct drm_device *dev);
> extern void intel_huc_auth(struct drm_device *dev);
> extern void intel_huc_fini(struct drm_device *dev);
> -
> +extern int intel_is_huc_valid(struct drm_i915_private *dev_priv);
> #endif
> diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
> index 87a6948..d574183 100644
> --- a/drivers/gpu/drm/i915/intel_huc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_huc_loader.c
> @@ -273,3 +273,17 @@ void intel_huc_fini(struct drm_device *dev)
>
> huc_fw->fetch_status = UC_FIRMWARE_NONE;
> }
> +
> +/**
> + * intel_is_huc_valid() - Check to see if the HuC is fully loaded.
> + * @dev_priv: drm device to check.
> + *
> + * This function will return true if the guc has been loaded and
> + * has valid firmware. The simplest way of doing this is to check
> + * if the HuC has been validated, if so it must have been loaded.
> + */
> +int intel_is_huc_valid(struct drm_i915_private *dev_priv)
I'm still unclear on the 'intel' vs. 'i915' prefix usage. But it seems
that intel prefixed functions accept drm_device instead of drm_i915_private.
Also, need to see the userspace usage of this new GETPARAM.
> +{
> + return ((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) != 0);
> +}
> +
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 629fb5e..d236520 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -389,6 +389,7 @@ typedef struct drm_i915_irq_wait {
> #define I915_PARAM_MIN_EU_IN_POOL 39
> #define I915_PARAM_MMAP_GTT_VERSION 40
> #define I915_PARAM_HAS_GUC 41
> +#define I915_PARAM_HAS_HUC 42
>
> typedef struct drm_i915_getparam {
> __s32 param;
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [PATCH 8/8] drm/i915/get_params: Add HuC status to getparams
2016-10-13 21:47 ` Jeff McGee
@ 2016-10-17 6:48 ` Daniel Vetter
0 siblings, 0 replies; 35+ messages in thread
From: Daniel Vetter @ 2016-10-17 6:48 UTC (permalink / raw)
To: Jeff McGee; +Cc: intel-gfx
On Thu, Oct 13, 2016 at 02:47:32PM -0700, Jeff McGee wrote:
> On Mon, Oct 03, 2016 at 11:43:02AM -0700, Anusha Srivatsa wrote:
> > From: Peter Antoine <peter.antoine@intel.com>
> >
> > This patch will allow for getparams to return the status of the HuC.
> > As the HuC has to be validated by the GuC this patch uses the validated
> > status to show when the HuC is loaded and ready for use. You cannot use
> > the loaded status as with the GuC as the HuC is verified after it is
> > loaded and is not usable until it is verified.
> >
> > v2: removed the forewakes as the registers are already force-woken.
> > (T.Ursulin)
> > v4: rebased.
> > v5: rebased.
> >
> > Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_drv.c | 4 ++++
> > drivers/gpu/drm/i915/intel_huc.h | 2 +-
> > drivers/gpu/drm/i915/intel_huc_loader.c | 14 ++++++++++++++
> > include/uapi/drm/i915_drm.h | 1 +
> > 4 files changed, 20 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > index ff1c18d..0d7b290 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -49,6 +49,7 @@
> > #include "i915_trace.h"
> > #include "i915_vgpu.h"
> > #include "intel_drv.h"
> > +#include "intel_huc.h"
> > #include "intel_guc.h"
> >
> > static struct drm_driver driver;
> > @@ -343,6 +344,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
> > case I915_PARAM_HAS_GUC:
> > value = intel_is_guc_valid(dev_priv);
> > break;
> > + case I915_PARAM_HAS_HUC:
> > + value = intel_is_huc_valid(dev_priv);
> > + break;
> > default:
> > DRM_DEBUG("Unknown parameter %d\n", param->param);
> > return -EINVAL;
> > diff --git a/drivers/gpu/drm/i915/intel_huc.h b/drivers/gpu/drm/i915/intel_huc.h
> > index 946caa7..5eac625 100644
> > --- a/drivers/gpu/drm/i915/intel_huc.h
> > +++ b/drivers/gpu/drm/i915/intel_huc.h
> > @@ -40,5 +40,5 @@ extern void intel_huc_init(struct drm_device *dev);
> > extern int intel_huc_load(struct drm_device *dev);
> > extern void intel_huc_auth(struct drm_device *dev);
> > extern void intel_huc_fini(struct drm_device *dev);
> > -
> > +extern int intel_is_huc_valid(struct drm_i915_private *dev_priv);
> > #endif
> > diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
> > index 87a6948..d574183 100644
> > --- a/drivers/gpu/drm/i915/intel_huc_loader.c
> > +++ b/drivers/gpu/drm/i915/intel_huc_loader.c
> > @@ -273,3 +273,17 @@ void intel_huc_fini(struct drm_device *dev)
> >
> > huc_fw->fetch_status = UC_FIRMWARE_NONE;
> > }
> > +
> > +/**
> > + * intel_is_huc_valid() - Check to see if the HuC is fully loaded.
> > + * @dev_priv: drm device to check.
> > + *
> > + * This function will return true if the guc has been loaded and
> > + * has valid firmware. The simplest way of doing this is to check
> > + * if the HuC has been validated, if so it must have been loaded.
> > + */
> > +int intel_is_huc_valid(struct drm_i915_private *dev_priv)
> I'm still unclear on the 'intel' vs. 'i915' prefix usage. But it seems
> that intel prefixed functions accept drm_device instead of drm_i915_private.
intel_ is core and modeset, i915_ is gem stuff. mostly. Absolutely nothing
to do with drm_device vs. drm_i915_private, that should only be a question
of whether it's a drm vfunc or an internal one (we're transitioning to
that pattern, so atm it's a bit a mess).
> Also, need to see the userspace usage of this new GETPARAM.
+1 ;-)
Cheers, Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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^ permalink raw reply [flat|nested] 35+ messages in thread
* ✗ Fi.CI.BAT: warning for HuC Loading Patches
2016-10-03 18:42 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa
` (7 preceding siblings ...)
2016-10-03 18:43 ` [PATCH 8/8] drm/i915/get_params: Add HuC " Anusha Srivatsa
@ 2016-10-03 19:19 ` Patchwork
2016-10-07 7:09 ` [PATCH 0/8] " Daniel Vetter
9 siblings, 0 replies; 35+ messages in thread
From: Patchwork @ 2016-10-03 19:19 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
== Series Details ==
Series: HuC Loading Patches
URL : https://patchwork.freedesktop.org/series/13244/
State : warning
== Summary ==
Series 13244v1 HuC Loading Patches
https://patchwork.freedesktop.org/api/1.0/series/13244/revisions/1/mbox/
Test drv_module_reload_basic:
skip -> PASS (fi-skl-6770hq)
Test kms_cursor_legacy:
Subgroup basic-flip-after-cursor-varying-size:
pass -> DMESG-WARN (fi-skl-6700k)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass -> DMESG-WARN (fi-byt-j1900)
Subgroup suspend-read-crc-pipe-b:
pass -> DMESG-WARN (fi-byt-j1900)
fi-bdw-5557u total:244 pass:229 dwarn:0 dfail:0 fail:0 skip:15
fi-bsw-n3050 total:244 pass:202 dwarn:0 dfail:0 fail:0 skip:42
fi-bxt-t5700 total:244 pass:214 dwarn:0 dfail:0 fail:0 skip:30
fi-byt-j1900 total:244 pass:210 dwarn:2 dfail:0 fail:1 skip:31
fi-hsw-4770 total:244 pass:222 dwarn:0 dfail:0 fail:0 skip:22
fi-hsw-4770r total:244 pass:222 dwarn:0 dfail:0 fail:0 skip:22
fi-ilk-650 total:244 pass:182 dwarn:0 dfail:0 fail:2 skip:60
fi-ivb-3520m total:244 pass:219 dwarn:0 dfail:0 fail:0 skip:25
fi-ivb-3770 total:244 pass:207 dwarn:0 dfail:0 fail:0 skip:37
fi-skl-6260u total:244 pass:230 dwarn:0 dfail:0 fail:0 skip:14
fi-skl-6700hq total:244 pass:222 dwarn:0 dfail:0 fail:0 skip:22
fi-skl-6700k total:244 pass:218 dwarn:2 dfail:0 fail:0 skip:24
fi-skl-6770hq total:244 pass:228 dwarn:1 dfail:0 fail:1 skip:14
fi-snb-2520m total:244 pass:208 dwarn:0 dfail:0 fail:0 skip:36
fi-snb-2600 total:244 pass:207 dwarn:0 dfail:0 fail:0 skip:37
fi-byt-n2820 failed to collect. IGT log at Patchwork_2615/fi-byt-n2820/igt.log
Results at /archive/results/CI_IGT_test/Patchwork_2615/
71d126590e2fa6d65d93fe3586d55ddf9f6c39a6 drm-intel-nightly: 2016y-10m-03d-13h-22m-56s UTC integration manifest
7372b66 drm/i915/get_params: Add HuC status to getparams
9b67dd6 drm/i915/get_params: Add GuC status to getparams
1ae3938 drm/i915/huc: Add BXT HuC Loading Support
5fa24fe drm/i915/huc: Support HuC authentication
9a038e2 drm/i915/huc: Add debugfs for HuC loading status check
52144f2 drm/i915/huc: Add HuC fw loading support
e5c48b1 drm/i915/huc: Unified css_header struct for GuC and HuC
e69b469 drm/i915/guc: Make the GuC fw loading helper functions general
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^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [PATCH 0/8] HuC Loading Patches
2016-10-03 18:42 [PATCH 0/8] HuC Loading Patches Anusha Srivatsa
` (8 preceding siblings ...)
2016-10-03 19:19 ` ✗ Fi.CI.BAT: warning for HuC Loading Patches Patchwork
@ 2016-10-07 7:09 ` Daniel Vetter
9 siblings, 0 replies; 35+ messages in thread
From: Daniel Vetter @ 2016-10-07 7:09 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
On Mon, Oct 03, 2016 at 11:42:54AM -0700, Anusha Srivatsa wrote:
> These patches add HuC loading support. The userspace
> patches that check for a fully loaded HuC firmware and use
> it can be found at:
> https://lists.freedesktop.org/archives/libva/2016-September/004554.html
> https://lists.freedesktop.org/archives/libva/2016-September/004555.html
>
> v2: rebased.
When submitting patches you always have to add your signed-off-by, even
when they're not yours. The chain of people who've touched a patch must be
completely tracked with these signed-off-by.
No ideas on the patches themselves since I'm not a huc/guc expert.
-Daniel
>
>
> Peter Antoine (8):
> drm/i915/guc: Make the GuC fw loading helper functions general
> drm/i915/huc: Unified css_header struct for GuC and HuC
> drm/i915/huc: Add HuC fw loading support
> drm/i915/huc: Add debugfs for HuC loading status check
> drm/i915/huc: Support HuC authentication
> drm/i915/huc: Add BXT HuC Loading Support
> drm/i915/get_params: Add GuC status to getparams
> drm/i915/get_params: Add HuC status to getparams
>
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/i915_debugfs.c | 43 ++++-
> drivers/gpu/drm/i915/i915_drv.c | 11 ++
> drivers/gpu/drm/i915/i915_drv.h | 3 +
> drivers/gpu/drm/i915/i915_guc_reg.h | 3 +
> drivers/gpu/drm/i915/i915_guc_submission.c | 69 ++++++-
> drivers/gpu/drm/i915/intel_guc.h | 48 ++---
> drivers/gpu/drm/i915/intel_guc_fwif.h | 17 +-
> drivers/gpu/drm/i915/intel_guc_loader.c | 215 ++++++++++++---------
> drivers/gpu/drm/i915/intel_huc.h | 44 +++++
> drivers/gpu/drm/i915/intel_huc_loader.c | 289 +++++++++++++++++++++++++++++
> include/uapi/drm/i915_drm.h | 2 +
> 12 files changed, 624 insertions(+), 121 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/intel_huc.h
> create mode 100644 drivers/gpu/drm/i915/intel_huc_loader.c
>
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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^ permalink raw reply [flat|nested] 35+ messages in thread