Re: [PATCH] drm/i915/gvt: Implement WaForceWakeRenderDuringMmioTLBInvalidate

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Thu, Oct 20, 2016 at 12:57:31PM +0200, Arkadiusz Hiler wrote:
> When invalidating RCS TLB the device can enter RC6 state interrupting
> the process, therefore the need for render forcewake for the whole
> procedure.
> 
> This WA is needed for all production SKL SKUs.
> 
> References: HSD#2136899, HSD#1404391274
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
> Signed-off-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
> ---
>  drivers/gpu/drm/i915/gvt/render.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/render.c b/drivers/gpu/drm/i915/gvt/render.c
> index f54ab85..f5000ea 100644
> --- a/drivers/gpu/drm/i915/gvt/render.c
> +++ b/drivers/gpu/drm/i915/gvt/render.c
> @@ -134,11 +134,22 @@ static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id)
>  
>  	reg = _MMIO(regs[ring_id]);

Random drive by comment:
You should add the registers to i915_reg.h properly so that we don't get
this ugly _MMIO() stuff sprinkled all over the place.

>  
> +	/* WaForceWakeRenderDuringMmioTLBInvalidate:skl
> +	 * we need to put a forcewake when invalidating RCS TLB caches,
> +	 * otherwise device can go to RC6 state and interrupt invalidation
> +	 * process */
> +	if (IS_SKYLAKE(dev_priv) && ring_id == RCS)
> +		intel_uncore_forcewake_get(dev_priv, FORCEWAKE_RENDER);
> +
>  	I915_WRITE(reg, 0x1);
>  
>  	if (wait_for_atomic((I915_READ(reg) == 0), 50))
>  		gvt_err("timeout in invalidate ring (%d) tlb\n", ring_id);
>  
> +	if (IS_SKYLAKE(dev_priv) && ring_id == RCS)
> +		intel_uncore_forcewake_put(dev_priv, FORCEWAKE_RENDER);
> +
> +
>  	gvt_dbg_core("invalidate TLB for ring %d\n", ring_id);
>  }
>  
> -- 
> 2.7.4
> 
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-- 
Ville Syrjälä
Intel OTC
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