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From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: Arkadiusz Hiler <arkadiusz.hiler@intel.com>,
	intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2] drm/i915/gvt: Implement WaForceWakeRenderDuringMmioTLBInvalidate
Date: Fri, 21 Oct 2016 13:55:59 +0300	[thread overview]
Message-ID: <874m46q8cg.fsf@gaia.fi.intel.com> (raw)
In-Reply-To: <1477045947-30768-1-git-send-email-arkadiusz.hiler@intel.com>

Arkadiusz Hiler <arkadiusz.hiler@intel.com> writes:

> When invalidating RCS TLB the device can enter RC6 state interrupting
> the process, therefore the need for render forcewake for the whole
> procedure.
>
> This WA is needed for all production SKL SKUs.
>
> v2: reworked putting and getting forcewake with help of Mika Kuoppala
>
> References: HSD#2136899, HSD#1404391274
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
> Signed-off-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
> ---
>  drivers/gpu/drm/i915/gvt/render.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gvt/render.c b/drivers/gpu/drm/i915/gvt/render.c
> index feebb65..8e7a80e 100644
> --- a/drivers/gpu/drm/i915/gvt/render.c
> +++ b/drivers/gpu/drm/i915/gvt/render.c
> @@ -118,6 +118,7 @@ static u32 gen9_render_mocs_L3[32];
>  static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id)
>  {
>  	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
> +	enum forcewake_domains fw;
>  	i915_reg_t reg;
>  	u32 regs[] = {
>  		[RCS] = 0x4260,
> @@ -135,11 +136,25 @@ static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id)
>  
>  	reg = _MMIO(regs[ring_id]);
>  
> +	/* WaForceWakeRenderDuringMmioTLBInvalidate:skl
> +	 * we need to put a forcewake when invalidating RCS TLB caches,
> +	 * otherwise device can go to RC6 state and interrupt invalidation
> +	 * process
> +	 */
> +	fw = intel_uncore_forcewake_for_reg(dev_priv, reg,
> +					    FW_REG_READ | FW_REG_WRITE);
> +	if (ring_id == RCS && IS_SKYLAKE(dev_priv))
> +		fw |= FORCEWAKE_RENDER;
> +
> +	intel_uncore_forcewake_get(dev_priv, fw);
> +
>  	I915_WRITE(reg, 0x1);
>

To take full advantage of the explicit forcewake dance, please
look at I915_WRITE_FW and I915_READ_FW.

-Mika


>  	if (wait_for_atomic((I915_READ(reg) == 0), 50))
>  		gvt_err("timeout in invalidate ring (%d) tlb\n", ring_id);
>  
> +	intel_uncore_forcewake_put(dev_priv, fw);
> +
>  	gvt_dbg_core("invalidate TLB for ring %d\n", ring_id);
>  }
>  
> -- 
> 2.7.4
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  reply	other threads:[~2016-10-21 10:57 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-10-20 10:57 [PATCH] drm/i915/gvt: Implement WaForceWakeRenderDuringMmioTLBInvalidate Arkadiusz Hiler
2016-10-20 11:17 ` ✗ Fi.CI.BAT: warning for " Patchwork
2016-10-20 11:52   ` Arkadiusz Hiler
2016-10-20 12:04     ` Ville Syrjälä
2016-10-20 12:55       ` Arkadiusz Hiler
2016-10-20 14:29 ` [PATCH] " Mika Kuoppala
2016-10-20 15:20   ` Arkadiusz Hiler
2016-10-21  4:15     ` Zhenyu Wang
2016-10-20 14:47 ` Ville Syrjälä
2016-10-21 10:32 ` [PATCH v2] " Arkadiusz Hiler
2016-10-21 10:55   ` Mika Kuoppala [this message]
2016-10-21 11:11 ` [PATCH v3] " Arkadiusz Hiler
2016-10-21 11:16 ` ✗ Fi.CI.BAT: warning for drm/i915/gvt: Implement WaForceWakeRenderDuringMmioTLBInvalidate (rev3) Patchwork
2016-10-21 11:46 ` ✓ Fi.CI.BAT: success for drm/i915/gvt: Implement WaForceWakeRenderDuringMmioTLBInvalidate (rev4) Patchwork

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