From: Marc Zyngier <marc.zyngier@arm.com>
To: Vladimir Murzin <vladimir.murzin@arm.com>
Cc: christoffer.dall@linaro.org, andre.przywara@arm.com,
kvmarm@lists.cs.columbia.edu,
linux-arm-kernel@lists.infradead.org, kbuild-all@01.org
Subject: Re: [RFC PATCH 4/8] irqchip/gicv3-its: specialise readq and writeq accesses
Date: Sat, 22 Oct 2016 16:43:49 +0100 [thread overview]
Message-ID: <20161022164349.18fe5d5a@arm.com> (raw)
In-Reply-To: <1477042601-15227-5-git-send-email-vladimir.murzin@arm.com>
On Fri, 21 Oct 2016 10:36:37 +0100
Vladimir Murzin <vladimir.murzin@arm.com> wrote:
Hi Vladimir,
> readq and writeq type of assessors are not supported in AArch32, so we
> need to specialise them and glue later with series of 32-bit accesses
> on AArch32 side.
>
> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
> ---
> arch/arm64/include/asm/arch_gicv3.h | 16 ++++++++++++++++
> drivers/irqchip/irq-gic-v3-its.c | 30 +++++++++++++++---------------
> 2 files changed, 31 insertions(+), 15 deletions(-)
>
> diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h
> index 4f0402a..e0ada98 100644
> --- a/arch/arm64/include/asm/arch_gicv3.h
> +++ b/arch/arm64/include/asm/arch_gicv3.h
> @@ -190,5 +190,21 @@ static inline void gic_write_bpr1(u32 val)
>
> #define gic_flush_dcache_to_poc(a,l) __flush_dcache_area((a), (l))
>
> +#define gits_read_typer(c) readq_relaxed(c)
> +
> +#define gits_read_baser(c) readq_relaxed(c)
> +#define gits_write_baser(v, c) writeq_relaxed(v, c)
> +
> +#define gits_read_cbaser(c) readq_relaxed(c)
> +#define gits_write_cbaser(v, c) writeq_relaxed(v, c)
> +
> +#define gits_write_cwriter(v, c) writeq_relaxed(v, c)
> +
> +#define gicr_read_propbaser(c) readq_relaxed(c)
> +#define gicr_write_propbaser(v, c) writeq_relaxed(v, c)
> +
> +#define gicr_write_pendbaser(v, c) writeq_relaxed(v, c)
> +#define gicr_read_pendbaser(c) readq_relaxed(c)
> +
> #endif /* __ASSEMBLY__ */
> #endif /* __ASM_ARCH_GICV3_H */
> diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
> index 86efa6e..9f74abc 100644
> --- a/drivers/irqchip/irq-gic-v3-its.c
> +++ b/drivers/irqchip/irq-gic-v3-its.c
> @@ -835,7 +835,7 @@ static u64 its_read_baser(struct its_node *its, struct its_baser *baser)
> {
> u32 idx = baser - its->tables;
>
> - return readq_relaxed(its->base + GITS_BASER + (idx << 3));
> + return gits_read_baser(its->base + GITS_BASER + (idx << 3));
> }
>
> static void its_write_baser(struct its_node *its, struct its_baser *baser,
> @@ -843,7 +843,7 @@ static void its_write_baser(struct its_node *its, struct its_baser *baser,
> {
> u32 idx = baser - its->tables;
>
> - writeq_relaxed(val, its->base + GITS_BASER + (idx << 3));
> + gits_write_baser(val, its->base + GITS_BASER + (idx << 3));
> baser->val = its_read_baser(its, baser);
> }
>
> @@ -1022,7 +1022,7 @@ static void its_free_tables(struct its_node *its)
>
> static int its_alloc_tables(struct its_node *its)
> {
> - u64 typer = readq_relaxed(its->base + GITS_TYPER);
> + u64 typer = gits_read_typer(its->base + GITS_TYPER);
This is going to conflict with the irq/irq-fixes-4.9 branch, which is
already on its way to mainline (and will hopefully hit -rc2) Could you
please rebase it once these patches are in mainline?
You'll notice that I didn't bother distinguishing between the various
GI*_TYPER registers, as they all have the same behaviour.
Otherwise looks good to me.
Thanks,
M.
--
Jazz is not dead. It just smells funny.
WARNING: multiple messages have this Message-ID (diff)
From: marc.zyngier@arm.com (Marc Zyngier)
To: linux-arm-kernel@lists.infradead.org
Subject: [RFC PATCH 4/8] irqchip/gicv3-its: specialise readq and writeq accesses
Date: Sat, 22 Oct 2016 16:43:49 +0100 [thread overview]
Message-ID: <20161022164349.18fe5d5a@arm.com> (raw)
In-Reply-To: <1477042601-15227-5-git-send-email-vladimir.murzin@arm.com>
On Fri, 21 Oct 2016 10:36:37 +0100
Vladimir Murzin <vladimir.murzin@arm.com> wrote:
Hi Vladimir,
> readq and writeq type of assessors are not supported in AArch32, so we
> need to specialise them and glue later with series of 32-bit accesses
> on AArch32 side.
>
> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
> ---
> arch/arm64/include/asm/arch_gicv3.h | 16 ++++++++++++++++
> drivers/irqchip/irq-gic-v3-its.c | 30 +++++++++++++++---------------
> 2 files changed, 31 insertions(+), 15 deletions(-)
>
> diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h
> index 4f0402a..e0ada98 100644
> --- a/arch/arm64/include/asm/arch_gicv3.h
> +++ b/arch/arm64/include/asm/arch_gicv3.h
> @@ -190,5 +190,21 @@ static inline void gic_write_bpr1(u32 val)
>
> #define gic_flush_dcache_to_poc(a,l) __flush_dcache_area((a), (l))
>
> +#define gits_read_typer(c) readq_relaxed(c)
> +
> +#define gits_read_baser(c) readq_relaxed(c)
> +#define gits_write_baser(v, c) writeq_relaxed(v, c)
> +
> +#define gits_read_cbaser(c) readq_relaxed(c)
> +#define gits_write_cbaser(v, c) writeq_relaxed(v, c)
> +
> +#define gits_write_cwriter(v, c) writeq_relaxed(v, c)
> +
> +#define gicr_read_propbaser(c) readq_relaxed(c)
> +#define gicr_write_propbaser(v, c) writeq_relaxed(v, c)
> +
> +#define gicr_write_pendbaser(v, c) writeq_relaxed(v, c)
> +#define gicr_read_pendbaser(c) readq_relaxed(c)
> +
> #endif /* __ASSEMBLY__ */
> #endif /* __ASM_ARCH_GICV3_H */
> diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
> index 86efa6e..9f74abc 100644
> --- a/drivers/irqchip/irq-gic-v3-its.c
> +++ b/drivers/irqchip/irq-gic-v3-its.c
> @@ -835,7 +835,7 @@ static u64 its_read_baser(struct its_node *its, struct its_baser *baser)
> {
> u32 idx = baser - its->tables;
>
> - return readq_relaxed(its->base + GITS_BASER + (idx << 3));
> + return gits_read_baser(its->base + GITS_BASER + (idx << 3));
> }
>
> static void its_write_baser(struct its_node *its, struct its_baser *baser,
> @@ -843,7 +843,7 @@ static void its_write_baser(struct its_node *its, struct its_baser *baser,
> {
> u32 idx = baser - its->tables;
>
> - writeq_relaxed(val, its->base + GITS_BASER + (idx << 3));
> + gits_write_baser(val, its->base + GITS_BASER + (idx << 3));
> baser->val = its_read_baser(its, baser);
> }
>
> @@ -1022,7 +1022,7 @@ static void its_free_tables(struct its_node *its)
>
> static int its_alloc_tables(struct its_node *its)
> {
> - u64 typer = readq_relaxed(its->base + GITS_TYPER);
> + u64 typer = gits_read_typer(its->base + GITS_TYPER);
This is going to conflict with the irq/irq-fixes-4.9 branch, which is
already on its way to mainline (and will hopefully hit -rc2) Could you
please rebase it once these patches are in mainline?
You'll notice that I didn't bother distinguishing between the various
GI*_TYPER registers, as they all have the same behaviour.
Otherwise looks good to me.
Thanks,
M.
--
Jazz is not dead. It just smells funny.
next prev parent reply other threads:[~2016-10-22 15:43 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-21 9:36 [RFC PATCH 0/8] Support GICv3 ITS and vITS in 32-bit mode Vladimir Murzin
2016-10-21 9:36 ` Vladimir Murzin
2016-10-21 9:36 ` [RFC PATCH 1/8] irqchip/gic-v3-its: Change unsigned types for AArch32 compatibility Vladimir Murzin
2016-10-21 9:36 ` Vladimir Murzin
2016-10-21 9:36 ` [RFC PATCH 2/8] irqchip/gic-v3-its: narrow down Entry Size when used as a divider Vladimir Murzin
2016-10-21 9:36 ` Vladimir Murzin
2016-10-21 9:36 ` [RFC PATCH 3/8] irqchip/gicv3-its: specialise flush_dcache operation Vladimir Murzin
2016-10-21 9:36 ` Vladimir Murzin
2016-10-21 9:36 ` [RFC PATCH 4/8] irqchip/gicv3-its: specialise readq and writeq accesses Vladimir Murzin
2016-10-21 9:36 ` Vladimir Murzin
2016-10-22 15:43 ` Marc Zyngier [this message]
2016-10-22 15:43 ` Marc Zyngier
2016-10-21 9:36 ` [RFC PATCH 5/8] ARM: gic-v3-its: Add 32bit support to GICv3 ITS Vladimir Murzin
2016-10-21 9:36 ` Vladimir Murzin
2016-10-21 9:36 ` [RFC PATCH 6/8] ARM: virt: select ARM_GIC_V3_ITS Vladimir Murzin
2016-10-21 9:36 ` Vladimir Murzin
2016-10-21 9:36 ` [RFC PATCH 7/8] KVM: arm64: vgic-its: fix compatability with 32-bit Vladimir Murzin
2016-10-21 9:36 ` Vladimir Murzin
2016-10-21 9:49 ` Andre Przywara
2016-10-21 9:49 ` Andre Przywara
2016-10-21 11:19 ` Vladimir Murzin
2016-10-21 11:19 ` Vladimir Murzin
2016-10-21 9:36 ` [RFC PATCH 8/8] ARM: KVM: Support vGICv3 ITS Vladimir Murzin
2016-10-21 9:36 ` Vladimir Murzin
2016-10-21 11:02 ` Andre Przywara
2016-10-21 11:02 ` Andre Przywara
2016-10-21 11:20 ` Vladimir Murzin
2016-10-21 11:20 ` Vladimir Murzin
2016-10-22 15:55 ` [RFC PATCH 0/8] Support GICv3 ITS and vITS in 32-bit mode Marc Zyngier
2016-10-22 15:55 ` Marc Zyngier
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