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From: Christoph Hellwig <hch@lst.de>
To: Dan Williams <dan.j.williams@intel.com>
Cc: Christoph Hellwig <hch@lst.de>, Tejun Heo <tj@kernel.org>,
	Keith Busch <keith.busch@intel.com>,
	IDE/ATA development list <linux-ide@vger.kernel.org>,
	linux-nvme@lists.infradead.org
Subject: Re: [PATCH 0/5] ahci: nvme remap support
Date: Mon, 24 Oct 2016 14:49:38 +0200	[thread overview]
Message-ID: <20161024124938.GB2389@lst.de> (raw)
In-Reply-To: <CAPcyv4iNNu5bxzEOx0XMy2Edd4d5xvrEK+6A4mYsNH5iXtbUTA@mail.gmail.com>

On Sun, Oct 23, 2016 at 06:57:41AM -0700, Dan Williams wrote:
> I should clarify that these are not new devices for the NVMe technical
> working group to consider. They are discrete / typical / off-the-shelf
> NVMe devices from any vendor.  It's just the memory bar and interrupt
> vector that are arranged to be shared with an ahci pci device.

But this has a profound effect on the NVMe operation, because fo
example the NVMe reset cycle is tied into PCIe function states.

Please bring this issue up with the relevant standards comittee first,
otherwise we're getting us into a nightmare of undefined behavior here.

And it's not like Intel isn't active in this group.  I'd suggest you
talk to Amber who is the editor for both the AHCI and NVMe spec,
that should get you started.

WARNING: multiple messages have this Message-ID (diff)
From: hch@lst.de (Christoph Hellwig)
Subject: [PATCH 0/5] ahci: nvme remap support
Date: Mon, 24 Oct 2016 14:49:38 +0200	[thread overview]
Message-ID: <20161024124938.GB2389@lst.de> (raw)
In-Reply-To: <CAPcyv4iNNu5bxzEOx0XMy2Edd4d5xvrEK+6A4mYsNH5iXtbUTA@mail.gmail.com>

On Sun, Oct 23, 2016@06:57:41AM -0700, Dan Williams wrote:
> I should clarify that these are not new devices for the NVMe technical
> working group to consider. They are discrete / typical / off-the-shelf
> NVMe devices from any vendor.  It's just the memory bar and interrupt
> vector that are arranged to be shared with an ahci pci device.

But this has a profound effect on the NVMe operation, because fo
example the NVMe reset cycle is tied into PCIe function states.

Please bring this issue up with the relevant standards comittee first,
otherwise we're getting us into a nightmare of undefined behavior here.

And it's not like Intel isn't active in this group.  I'd suggest you
talk to Amber who is the editor for both the AHCI and NVMe spec,
that should get you started.

  reply	other threads:[~2016-10-24 12:49 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-10-22  0:25 [PATCH 0/5] ahci: nvme remap support Dan Williams
2016-10-22  0:25 ` Dan Williams
2016-10-22  0:25 ` [PATCH 1/5] " Dan Williams
2016-10-22  0:25   ` Dan Williams
2016-10-22  0:25 ` [PATCH 2/5] nvme: rename "pci" operations to "mmio" Dan Williams
2016-10-22  0:25   ` Dan Williams
2016-10-22  0:25 ` [PATCH 3/5] nvme: introduce nvme_dev_ops Dan Williams
2016-10-22  0:25   ` Dan Williams
2016-10-22  0:25 ` [PATCH 4/5] nvme: move common definitions to pci.h Dan Williams
2016-10-22  0:25   ` Dan Williams
2016-10-22  0:25 ` [PATCH 5/5] nvme: ahci remap support Dan Williams
2016-10-22  0:25   ` Dan Williams
2016-10-22  6:50 ` [PATCH 0/5] ahci: nvme " Christoph Hellwig
2016-10-22  6:50   ` Christoph Hellwig
2016-10-22 19:26   ` Dan Williams
2016-10-22 19:26     ` Dan Williams
2016-10-23  8:34     ` Christoph Hellwig
2016-10-23  8:34       ` Christoph Hellwig
2016-10-23 13:57       ` Dan Williams
2016-10-23 13:57         ` Dan Williams
2016-10-24 12:49         ` Christoph Hellwig [this message]
2016-10-24 12:49           ` Christoph Hellwig
2016-10-24 14:46           ` Keith Busch
2016-10-24 14:46             ` Keith Busch
2016-10-24 15:16             ` Christoph Hellwig
2016-10-24 15:16               ` Christoph Hellwig
2016-10-24 17:46               ` Dan Williams
2016-10-24 17:46                 ` Dan Williams
2016-10-24 17:55                 ` Christoph Hellwig
2016-10-24 17:55                   ` Christoph Hellwig
2016-10-24 21:01                   ` Dan Williams
2016-10-24 21:01                     ` Dan Williams
2016-10-24 17:57                 ` Dan Williams
2016-10-24 17:57                   ` Dan Williams
2016-10-24 18:21                   ` Christoph Hellwig
2016-10-24 18:21                     ` Christoph Hellwig
2016-11-15 18:52 ` Christoph Hellwig
2016-11-15 18:52   ` Christoph Hellwig
2016-11-19  6:12   ` Dan Williams
2016-11-19  6:12     ` Dan Williams

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