From: David Gibson <david@gibson.dropbear.id.au>
To: "Cédric Le Goater" <clg@kaod.org>
Cc: qemu-ppc@nongnu.org,
Benjamin Herrenschmidt <benh@kernel.crashing.org>,
qemu-devel@nongnu.org, Alexander Graf <agraf@suse.de>
Subject: Re: [Qemu-devel] [PATCH v5 13/17] ppc/xics: add a xics_get_cpu_index_by_pir helper
Date: Fri, 28 Oct 2016 12:03:34 +1100 [thread overview]
Message-ID: <20161028010334.GC19349@umbus.fritz.box> (raw)
In-Reply-To: <ce67617b-a402-a475-a5e6-2ed885145c70@kaod.org>
[-- Attachment #1: Type: text/plain, Size: 2876 bytes --]
On Thu, Oct 27, 2016 at 08:05:02PM +0200, Cédric Le Goater wrote:
> On 10/27/2016 05:12 AM, David Gibson wrote:
> > On Tue, Oct 25, 2016 at 12:58:11PM +0200, Cédric Le Goater wrote:
> >> On 10/25/2016 07:36 AM, David Gibson wrote:
> >>> On Sat, Oct 22, 2016 at 11:46:46AM +0200, Cédric Le Goater wrote:
> >>>> We will need this helper to translate the server number of the XIVE
> >>>> (which is a PIR) into an ICPState index number (which is a cpu index).
> >>>>
> >>>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> >>>
> >>> Looks correct as far as it goes, but I wonder if this would be more
> >>> generally useful as a machine level function that searches the cpu
> >>> objects by PIR, returning a pointer. From that to the cpu_index is
> >>> then trivial.
> >>
> >> Well I guess so. The XICSState argument reduces the scope in case of
> >> multichip but as this routine is used to initialize the xive registers,
> >> it does not need to be fast.
> >
> > Ahh.. I was thinking of the top-level xics object as global, rather
> > than per-chip.
>
> well, the ICP MMIO region address is linked to the chip but that is all
> for the moment.
>
> > Except.. does having it per-chip work anyway? The server numbers are
> > globally unique, aren't they?
>
> yes.
>
> > What happens if you put a server number from one chip as the target
> > for an ICE on another chip?
>
> we have the chip number, so we could route ? I haven't gone that far
> in the modeling though. It might be overly complex to do for the purpose.
Right.. yeah, trying to route between XICS objects sounds like a
nightmare. Really the whole notion of the XICS overall object is that
it represents the whole irq propagation fabric - so it knows about all
the ICPS and all the ICSes and handles the routing between them.
So making the XICS object per-chip I think is a mistake which will
just lead to pain down the track. See my other mail for a new
suggestion on how to handle this.
> > The xics object is a bit weird, in that it doesn't represent a real
> > device in a sense, but is rather something to co-ordinate global
> > addressing between ICS and ICP units. Well, I suppose in that sense
> > it represent the interrupt propagation fabric.
>
> yes. See my other email. I think we can get rid of it and simply use
> a XICSState which links together the ICPs and the ICS of the system.
> but, let's keep it at the chip level for the moment, it is correct,
> and see if we need to move it upwards when we work on multichip.
No, I disagree. I think moving the XICs up a layer will only create
pain later for little benefit now.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
next prev parent reply other threads:[~2016-10-28 1:38 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-22 9:46 [Qemu-devel] [PATCH v5 00/17] ppc/pnv: booting the kernel and reaching user space Cédric Le Goater
2016-10-22 9:46 ` [Qemu-devel] [PATCH v5 01/17] ppc: add skiboot firmware for the pnv platform Cédric Le Goater
2016-10-22 9:46 ` [Qemu-devel] [PATCH v5 02/17] ppc/pnv: add skeleton PowerNV platform Cédric Le Goater
2016-10-22 9:46 ` [Qemu-devel] [PATCH v5 03/17] ppc/pnv: add a PnvChip object Cédric Le Goater
2016-10-22 9:46 ` [Qemu-devel] [PATCH v5 04/17] ppc/pnv: add a core mask to PnvChip Cédric Le Goater
2016-10-22 9:46 ` [Qemu-devel] [PATCH v5 05/17] ppc/pnv: add a PIR handler " Cédric Le Goater
2016-10-22 9:46 ` [Qemu-devel] [PATCH v5 06/17] ppc/pnv: add a PnvCore object Cédric Le Goater
2016-10-22 9:46 ` [Qemu-devel] [PATCH v5 07/17] ppc/pnv: add XSCOM infrastructure Cédric Le Goater
2016-10-25 1:13 ` David Gibson
2016-10-25 6:24 ` Cédric Le Goater
2016-10-22 9:46 ` [Qemu-devel] [PATCH v5 08/17] ppc/pnv: add XSCOM handlers to PnvCore Cédric Le Goater
2016-10-25 1:14 ` David Gibson
2016-10-22 9:46 ` [Qemu-devel] [PATCH v5 09/17] ppc/pnv: add a LPC controller Cédric Le Goater
2016-10-22 9:46 ` [Qemu-devel] [PATCH v5 10/17] ppc/pnv: add a ISA bus Cédric Le Goater
2016-10-22 9:46 ` [Qemu-devel] [PATCH v5 11/17] ppc/xics: Add "native" XICS subclass Cédric Le Goater
2016-10-25 5:08 ` David Gibson
2016-10-26 7:13 ` Cédric Le Goater
2016-10-27 3:09 ` David Gibson
2016-10-27 17:43 ` Cédric Le Goater
2016-10-28 1:00 ` David Gibson
2016-11-02 10:48 ` Cédric Le Goater
2016-11-08 1:44 ` David Gibson
2016-10-22 9:46 ` [Qemu-devel] [PATCH v5 12/17] ppc/pnv: add a XICS native to each PowerNV chip Cédric Le Goater
2016-10-24 15:42 ` Cédric Le Goater
2016-10-25 5:11 ` David Gibson
2016-10-22 9:46 ` [Qemu-devel] [PATCH v5 13/17] ppc/xics: add a xics_get_cpu_index_by_pir helper Cédric Le Goater
2016-10-25 5:36 ` David Gibson
2016-10-25 10:58 ` Cédric Le Goater
2016-10-27 3:12 ` David Gibson
2016-10-27 18:05 ` Cédric Le Goater
2016-10-28 1:03 ` David Gibson [this message]
2016-10-22 9:46 ` [Qemu-devel] [PATCH v5 14/17] ppc/xics: introduce a helper to insert a new ics Cédric Le Goater
2016-10-25 5:12 ` David Gibson
2016-10-22 9:46 ` [Qemu-devel] [PATCH v5 15/17] ppc/pnv: Add cut down PSI bridge model and hookup external interrupt Cédric Le Goater
2016-10-25 5:30 ` David Gibson
2016-10-25 7:58 ` Cédric Le Goater
2016-10-26 0:05 ` David Gibson
2016-10-25 11:00 ` Cédric Le Goater
2016-10-22 9:46 ` [Qemu-devel] [PATCH v5 16/17] ppc/pnv: Add OCC model stub with interrupt support Cédric Le Goater
2016-10-22 9:46 ` [Qemu-devel] [PATCH v5 17/17] ppc/pnv: Add Naples chip support for LPC interrupts Cédric Le Goater
2016-10-25 5:35 ` David Gibson
2016-10-24 5:33 ` [Qemu-devel] [PATCH v5 00/17] ppc/pnv: booting the kernel and reaching user space David Gibson
2016-10-25 1:38 ` David Gibson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20161028010334.GC19349@umbus.fritz.box \
--to=david@gibson.dropbear.id.au \
--cc=agraf@suse.de \
--cc=benh@kernel.crashing.org \
--cc=clg@kaod.org \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.