* [PATCH 1/7] drm/i915/guc: Make the GuC fw loading helper functions general
2016-10-29 0:05 [PATCH 0/7] HuC Loading Patches Anusha Srivatsa
@ 2016-10-29 0:05 ` Anusha Srivatsa
2016-10-29 0:05 ` [PATCH 2/7] drm/i915/huc: Unified css_header struct for GuC and HuC Anusha Srivatsa
` (6 subsequent siblings)
7 siblings, 0 replies; 14+ messages in thread
From: Anusha Srivatsa @ 2016-10-29 0:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Alex Dai, Peter Antoine
From: Peter Antoine <peter.antoine@intel.com>
Rename some of the GuC fw loading code to make them more general. We
will utilise them for HuC loading as well.
s/intel_guc_fw/intel_uc_fw/g
s/GUC_FIRMWARE/UC_FIRMWARE/g
Struct intel_guc_fw is renamed to intel_uc_fw. Prefix of tts members,
such as 'guc' or 'guc_fw' either is renamed to 'uc' or removed for
same purpose.
v2: rebased on top of nightly.
reapplied the search/replace as upstream code as changed.
v3: rebased again on drm-nightly.
v4: removed G from messages in shared fw fetch function.
v5: rebased.
v7: rebased.
v8: rebased.
v9: rebased.
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Jeff McGee <jeff.mcgee@intel.com>
Reviewed-by: Carlos Santa <carlos.santa@intel.com>
Tested-by: Carlos Santa <carlos.santa@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 12 +--
drivers/gpu/drm/i915/i915_guc_submission.c | 4 +-
drivers/gpu/drm/i915/intel_guc.h | 39 ++++----
drivers/gpu/drm/i915/intel_guc_loader.c | 156 ++++++++++++++---------------
4 files changed, 106 insertions(+), 105 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index be92efe..3e68d32 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2376,7 +2376,7 @@ static int i915_llc(struct seq_file *m, void *data)
static int i915_guc_load_status_info(struct seq_file *m, void *data)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
- struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
+ struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
u32 tmp, i;
if (!HAS_GUC_UCODE(dev_priv))
@@ -2384,15 +2384,15 @@ static int i915_guc_load_status_info(struct seq_file *m, void *data)
seq_printf(m, "GuC firmware status:\n");
seq_printf(m, "\tpath: %s\n",
- guc_fw->guc_fw_path);
+ guc_fw->uc_fw_path);
seq_printf(m, "\tfetch: %s\n",
- intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
+ intel_uc_fw_status_repr(guc_fw->fetch_status));
seq_printf(m, "\tload: %s\n",
- intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
+ intel_uc_fw_status_repr(guc_fw->load_status));
seq_printf(m, "\tversion wanted: %d.%d\n",
- guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
+ guc_fw->major_ver_wanted, guc_fw->minor_ver_wanted);
seq_printf(m, "\tversion found: %d.%d\n",
- guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
+ guc_fw->major_ver_found, guc_fw->minor_ver_found);
seq_printf(m, "\theader: offset is %d; size = %d\n",
guc_fw->header_offset, guc_fw->header_size);
seq_printf(m, "\tuCode: offset is %d; size = %d\n",
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index 74235ea..99dc5d9 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -1569,7 +1569,7 @@ int intel_guc_suspend(struct drm_device *dev)
struct i915_gem_context *ctx;
u32 data[3];
- if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
+ if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS)
return 0;
gen9_disable_guc_interrupts(dev_priv);
@@ -1597,7 +1597,7 @@ int intel_guc_resume(struct drm_device *dev)
struct i915_gem_context *ctx;
u32 data[3];
- if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
+ if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS)
return 0;
if (i915.guc_log_level >= 0)
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 49ced0b..186efa7 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -91,29 +91,29 @@ struct i915_guc_client {
uint64_t submissions[I915_NUM_ENGINES];
};
-enum intel_guc_fw_status {
- GUC_FIRMWARE_FAIL = -1,
- GUC_FIRMWARE_NONE = 0,
- GUC_FIRMWARE_PENDING,
- GUC_FIRMWARE_SUCCESS
+enum intel_uc_fw_status {
+ UC_FIRMWARE_FAIL = -1,
+ UC_FIRMWARE_NONE = 0,
+ UC_FIRMWARE_PENDING,
+ UC_FIRMWARE_SUCCESS
};
/*
* This structure encapsulates all the data needed during the process
* of fetching, caching, and loading the firmware image into the GuC.
*/
-struct intel_guc_fw {
- struct drm_device * guc_dev;
- const char * guc_fw_path;
- size_t guc_fw_size;
- struct drm_i915_gem_object * guc_fw_obj;
- enum intel_guc_fw_status guc_fw_fetch_status;
- enum intel_guc_fw_status guc_fw_load_status;
-
- uint16_t guc_fw_major_wanted;
- uint16_t guc_fw_minor_wanted;
- uint16_t guc_fw_major_found;
- uint16_t guc_fw_minor_found;
+struct intel_uc_fw {
+ struct drm_device *uc_dev;
+ const char *uc_fw_path;
+ size_t uc_fw_size;
+ struct drm_i915_gem_object *uc_fw_obj;
+ enum intel_uc_fw_status fetch_status;
+ enum intel_uc_fw_status load_status;
+
+ uint16_t major_ver_wanted;
+ uint16_t minor_ver_wanted;
+ uint16_t major_ver_found;
+ uint16_t minor_ver_found;
uint32_t header_size;
uint32_t header_offset;
@@ -140,7 +140,7 @@ struct intel_guc_log {
};
struct intel_guc {
- struct intel_guc_fw guc_fw;
+ struct intel_uc_fw guc_fw;
struct intel_guc_log log;
/* GuC2Host interrupt related state */
@@ -173,9 +173,10 @@ struct intel_guc {
extern void intel_guc_init(struct drm_device *dev);
extern int intel_guc_setup(struct drm_device *dev);
extern void intel_guc_fini(struct drm_device *dev);
-extern const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status);
+extern const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status);
extern int intel_guc_suspend(struct drm_device *dev);
extern int intel_guc_resume(struct drm_device *dev);
+void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw);
/* i915_guc_submission.c */
int i915_guc_submission_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 1aa8523..6683a88 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -81,16 +81,16 @@ MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
/* User-friendly representation of an enum */
-const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
+const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status)
{
switch (status) {
- case GUC_FIRMWARE_FAIL:
+ case UC_FIRMWARE_FAIL:
return "FAIL";
- case GUC_FIRMWARE_NONE:
+ case UC_FIRMWARE_NONE:
return "NONE";
- case GUC_FIRMWARE_PENDING:
+ case UC_FIRMWARE_PENDING:
return "PENDING";
- case GUC_FIRMWARE_SUCCESS:
+ case UC_FIRMWARE_SUCCESS:
return "SUCCESS";
default:
return "UNKNOWN!";
@@ -278,7 +278,7 @@ static inline bool guc_ucode_response(struct drm_i915_private *dev_priv,
static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
struct i915_vma *vma)
{
- struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
+ struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
unsigned long offset;
struct sg_table *sg = vma->pages;
u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT];
@@ -350,17 +350,17 @@ static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
*/
static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
{
- struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
+ struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
struct i915_vma *vma;
int ret;
- ret = i915_gem_object_set_to_gtt_domain(guc_fw->guc_fw_obj, false);
+ ret = i915_gem_object_set_to_gtt_domain(guc_fw->uc_fw_obj, false);
if (ret) {
DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
return ret;
}
- vma = i915_gem_object_ggtt_pin(guc_fw->guc_fw_obj, NULL, 0, 0, 0);
+ vma = i915_gem_object_ggtt_pin(guc_fw->uc_fw_obj, NULL, 0, 0, 0);
if (IS_ERR(vma)) {
DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
return PTR_ERR(vma);
@@ -451,14 +451,14 @@ static int guc_hw_reset(struct drm_i915_private *dev_priv)
int intel_guc_setup(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
- const char *fw_path = guc_fw->guc_fw_path;
+ struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
+ const char *fw_path = guc_fw->uc_fw_path;
int retries, ret, err;
DRM_DEBUG_DRIVER("GuC fw status: path %s, fetch %s, load %s\n",
fw_path,
- intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
- intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
+ intel_uc_fw_status_repr(guc_fw->fetch_status),
+ intel_uc_fw_status_repr(guc_fw->load_status));
/* Loading forbidden, or no firmware to load? */
if (!i915.enable_guc_loading) {
@@ -476,10 +476,10 @@ int intel_guc_setup(struct drm_device *dev)
}
/* Fetch failed, or already fetched but failed to load? */
- if (guc_fw->guc_fw_fetch_status != GUC_FIRMWARE_SUCCESS) {
+ if (guc_fw->fetch_status != UC_FIRMWARE_SUCCESS) {
err = -EIO;
goto fail;
- } else if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_FAIL) {
+ } else if (guc_fw->load_status == UC_FIRMWARE_FAIL) {
err = -ENOEXEC;
goto fail;
}
@@ -487,11 +487,11 @@ int intel_guc_setup(struct drm_device *dev)
guc_interrupts_release(dev_priv);
gen9_reset_guc_interrupts(dev_priv);
- guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
+ guc_fw->load_status = UC_FIRMWARE_PENDING;
DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
- intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
- intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
+ intel_uc_fw_status_repr(guc_fw->fetch_status),
+ intel_uc_fw_status_repr(guc_fw->load_status));
err = i915_guc_submission_init(dev_priv);
if (err)
@@ -523,11 +523,11 @@ int intel_guc_setup(struct drm_device *dev)
"retry %d more time(s)\n", err, retries);
}
- guc_fw->guc_fw_load_status = GUC_FIRMWARE_SUCCESS;
+ guc_fw->load_status = UC_FIRMWARE_SUCCESS;
DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
- intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
- intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
+ intel_uc_fw_status_repr(guc_fw->fetch_status),
+ intel_uc_fw_status_repr(guc_fw->load_status));
if (i915.enable_guc_submission) {
if (i915.guc_log_level >= 0)
@@ -542,8 +542,8 @@ int intel_guc_setup(struct drm_device *dev)
return 0;
fail:
- if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_PENDING)
- guc_fw->guc_fw_load_status = GUC_FIRMWARE_FAIL;
+ if (guc_fw->load_status == UC_FIRMWARE_PENDING)
+ guc_fw->load_status = UC_FIRMWARE_FAIL;
guc_interrupts_release(dev_priv);
i915_guc_submission_disable(dev_priv);
@@ -588,7 +588,7 @@ int intel_guc_setup(struct drm_device *dev)
return ret;
}
-static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
+void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw)
{
struct pci_dev *pdev = dev->pdev;
struct drm_i915_gem_object *obj;
@@ -597,17 +597,17 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
size_t size;
int err;
- DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n",
- intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
+ DRM_DEBUG_DRIVER("before requesting firmware: uC fw fetch status %s\n",
+ intel_uc_fw_status_repr(uc_fw->fetch_status));
- err = request_firmware(&fw, guc_fw->guc_fw_path, &pdev->dev);
+ err = request_firmware(&fw, uc_fw->uc_fw_path, &pdev->dev);
if (err)
goto fail;
if (!fw)
goto fail;
- DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n",
- guc_fw->guc_fw_path, fw);
+ DRM_DEBUG_DRIVER("fetch uC fw from %s succeeded, fw %p\n",
+ uc_fw->uc_fw_path, fw);
/* Check the size of the blob before examining buffer contents */
if (fw->size < sizeof(struct guc_css_header)) {
@@ -618,36 +618,36 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
css = (struct guc_css_header *)fw->data;
/* Firmware bits always start from header */
- guc_fw->header_offset = 0;
- guc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
+ uc_fw->header_offset = 0;
+ uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
- if (guc_fw->header_size != sizeof(struct guc_css_header)) {
+ if (uc_fw->header_size != sizeof(struct guc_css_header)) {
DRM_NOTE("CSS header definition mismatch\n");
goto fail;
}
/* then, uCode */
- guc_fw->ucode_offset = guc_fw->header_offset + guc_fw->header_size;
- guc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
+ uc_fw->ucode_offset = uc_fw->header_offset + uc_fw->header_size;
+ uc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
/* now RSA */
if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) {
DRM_NOTE("RSA key size is bad\n");
goto fail;
}
- guc_fw->rsa_offset = guc_fw->ucode_offset + guc_fw->ucode_size;
- guc_fw->rsa_size = css->key_size_dw * sizeof(u32);
+ uc_fw->rsa_offset = uc_fw->ucode_offset + uc_fw->ucode_size;
+ uc_fw->rsa_size = css->key_size_dw * sizeof(u32);
/* At least, it should have header, uCode and RSA. Size of all three. */
- size = guc_fw->header_size + guc_fw->ucode_size + guc_fw->rsa_size;
+ size = uc_fw->header_size + uc_fw->ucode_size + uc_fw->rsa_size;
if (fw->size < size) {
DRM_NOTE("Missing firmware components\n");
goto fail;
}
/* Header and uCode will be loaded to WOPCM. Size of the two. */
- size = guc_fw->header_size + guc_fw->ucode_size;
+ size = uc_fw->header_size + uc_fw->ucode_size;
if (size > guc_wopcm_size(to_i915(dev))) {
DRM_NOTE("Firmware is too large to fit in WOPCM\n");
goto fail;
@@ -659,21 +659,21 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
* TWO bytes each (i.e. u16), although all pointers and offsets are defined
* in terms of bytes (u8).
*/
- guc_fw->guc_fw_major_found = css->guc_sw_version >> 16;
- guc_fw->guc_fw_minor_found = css->guc_sw_version & 0xFFFF;
-
- if (guc_fw->guc_fw_major_found != guc_fw->guc_fw_major_wanted ||
- guc_fw->guc_fw_minor_found < guc_fw->guc_fw_minor_wanted) {
- DRM_NOTE("GuC firmware version %d.%d, required %d.%d\n",
- guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
- guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
+ uc_fw->major_ver_found = css->guc_sw_version >> 16;
+ uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
+
+ if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
+ uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) {
+ DRM_NOTE("uC firmware version %d.%d, required %d.%d\n",
+ uc_fw->major_ver_found, uc_fw->minor_ver_found,
+ uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
err = -ENOEXEC;
goto fail;
}
DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n",
- guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
- guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
+ uc_fw->major_ver_found, uc_fw->minor_ver_found,
+ uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
mutex_lock(&dev->struct_mutex);
obj = i915_gem_object_create_from_data(dev, fw->data, fw->size);
@@ -683,31 +683,31 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
goto fail;
}
- guc_fw->guc_fw_obj = obj;
- guc_fw->guc_fw_size = fw->size;
+ uc_fw->uc_fw_obj = obj;
+ uc_fw->uc_fw_size = fw->size;
- DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n",
- guc_fw->guc_fw_obj);
+ DRM_DEBUG_DRIVER("uC fw fetch status SUCCESS, obj %p\n",
+ uc_fw->uc_fw_obj);
release_firmware(fw);
- guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_SUCCESS;
+ uc_fw->fetch_status = UC_FIRMWARE_SUCCESS;
return;
fail:
- DRM_WARN("Failed to fetch valid GuC firmware from %s (error %d)\n",
- guc_fw->guc_fw_path, err);
- DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n",
- err, fw, guc_fw->guc_fw_obj);
+ DRM_WARN("Failed to fetch valid uC firmware from %s (error %d)\n",
+ uc_fw->uc_fw_path, err);
+ DRM_DEBUG_DRIVER("uC fw fetch status FAIL; err %d, fw %p, obj %p\n",
+ err, fw, uc_fw->uc_fw_obj);
mutex_lock(&dev->struct_mutex);
- obj = guc_fw->guc_fw_obj;
+ obj = uc_fw->uc_fw_obj;
if (obj)
i915_gem_object_put(obj);
- guc_fw->guc_fw_obj = NULL;
+ uc_fw->uc_fw_obj = NULL;
mutex_unlock(&dev->struct_mutex);
release_firmware(fw); /* OK even if fw is NULL */
- guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
+ uc_fw->fetch_status = UC_FIRMWARE_FAIL;
}
/**
@@ -722,7 +722,7 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
void intel_guc_init(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
+ struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
const char *fw_path;
if (!HAS_GUC(dev)) {
@@ -740,24 +740,24 @@ void intel_guc_init(struct drm_device *dev)
fw_path = NULL;
} else if (IS_SKYLAKE(dev_priv)) {
fw_path = I915_SKL_GUC_UCODE;
- guc_fw->guc_fw_major_wanted = SKL_FW_MAJOR;
- guc_fw->guc_fw_minor_wanted = SKL_FW_MINOR;
+ guc_fw->major_ver_wanted = SKL_FW_MAJOR;
+ guc_fw->minor_ver_wanted = SKL_FW_MINOR;
} else if (IS_BROXTON(dev_priv)) {
fw_path = I915_BXT_GUC_UCODE;
- guc_fw->guc_fw_major_wanted = BXT_FW_MAJOR;
- guc_fw->guc_fw_minor_wanted = BXT_FW_MINOR;
+ guc_fw->major_ver_wanted = BXT_FW_MAJOR;
+ guc_fw->minor_ver_wanted = BXT_FW_MINOR;
} else if (IS_KABYLAKE(dev_priv)) {
fw_path = I915_KBL_GUC_UCODE;
- guc_fw->guc_fw_major_wanted = KBL_FW_MAJOR;
- guc_fw->guc_fw_minor_wanted = KBL_FW_MINOR;
+ guc_fw->major_ver_wanted = KBL_FW_MAJOR;
+ guc_fw->minor_ver_wanted = KBL_FW_MINOR;
} else {
fw_path = ""; /* unknown device */
}
- guc_fw->guc_dev = dev;
- guc_fw->guc_fw_path = fw_path;
- guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
- guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE;
+ guc_fw->uc_dev = dev;
+ guc_fw->uc_fw_path = fw_path;
+ guc_fw->fetch_status = UC_FIRMWARE_NONE;
+ guc_fw->load_status = UC_FIRMWARE_NONE;
/* Early (and silent) return if GuC loading is disabled */
if (!i915.enable_guc_loading)
@@ -767,9 +767,9 @@ void intel_guc_init(struct drm_device *dev)
if (*fw_path == '\0')
return;
- guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING;
+ guc_fw->fetch_status = UC_FIRMWARE_PENDING;
DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path);
- guc_fw_fetch(dev, guc_fw);
+ intel_uc_fw_fetch(dev, guc_fw);
/* status must now be FAIL or SUCCESS */
}
@@ -780,17 +780,17 @@ void intel_guc_init(struct drm_device *dev)
void intel_guc_fini(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
+ struct intel_uc_fw *guc_fw = &dev_priv->guc.guc_fw;
mutex_lock(&dev->struct_mutex);
guc_interrupts_release(dev_priv);
i915_guc_submission_disable(dev_priv);
i915_guc_submission_fini(dev_priv);
- if (guc_fw->guc_fw_obj)
- i915_gem_object_put(guc_fw->guc_fw_obj);
- guc_fw->guc_fw_obj = NULL;
+ if (guc_fw->uc_fw_obj)
+ i915_gem_object_put(guc_fw->uc_fw_obj);
+ guc_fw->uc_fw_obj = NULL;
mutex_unlock(&dev->struct_mutex);
- guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
+ guc_fw->fetch_status = UC_FIRMWARE_NONE;
}
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 2/7] drm/i915/huc: Unified css_header struct for GuC and HuC
2016-10-29 0:05 [PATCH 0/7] HuC Loading Patches Anusha Srivatsa
2016-10-29 0:05 ` [PATCH 1/7] drm/i915/guc: Make the GuC fw loading helper functions general Anusha Srivatsa
@ 2016-10-29 0:05 ` Anusha Srivatsa
2016-10-31 20:02 ` Jeff McGee
2016-10-29 0:05 ` [PATCH 3/7] drm/i915/huc: Add HuC fw loading support Anusha Srivatsa
` (5 subsequent siblings)
7 siblings, 1 reply; 14+ messages in thread
From: Anusha Srivatsa @ 2016-10-29 0:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Alex Dai, Peter Antoine
From: Peter Antoine <peter.antoine@intel.com>
HuC firmware css header has almost exactly same definition as GuC
firmware except for the sw_version. Also, add a new member fw_type
into intel_uc_fw to indicate what kind of fw it is. So, the loader
will pull right sw_version from header.
v2: rebased on-top of drm-intel-nightly
v3: rebased on-top of drm-intel-nightly (again).
v4: rebased + spaces.
v7: rebased.
v8: rebased.
v9: rebased. Rename device_id to guc_branch_client_version,
make guc_sw_version a union. <Jeff Mcgee>. Put UC_FW_TYPE_GUC
and UC_FW_TYPE_HUC into an enum.
Tested-by: Xiang Haihao <haihao.xiang@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
---
drivers/gpu/drm/i915/intel_guc.h | 6 +++++
drivers/gpu/drm/i915/intel_guc_fwif.h | 21 +++++++++++++----
drivers/gpu/drm/i915/intel_guc_loader.c | 41 ++++++++++++++++++++++-----------
3 files changed, 51 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 186efa7..84ef2bf 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -98,6 +98,11 @@ enum intel_uc_fw_status {
UC_FIRMWARE_SUCCESS
};
+enum {
+ UC_FW_TYPE_GUC,
+ UC_FW_TYPE_HUC
+};
+
/*
* This structure encapsulates all the data needed during the process
* of fetching, caching, and loading the firmware image into the GuC.
@@ -115,6 +120,7 @@ struct intel_uc_fw {
uint16_t major_ver_found;
uint16_t minor_ver_found;
+ uint32_t fw_type;
uint32_t header_size;
uint32_t header_offset;
uint32_t rsa_size;
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 324ea90..c2a7fdd 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -154,7 +154,7 @@
* The GuC firmware layout looks like this:
*
* +-------------------------------+
- * | guc_css_header |
+ * | uc_css_header |
* | |
* | contains major/minor version |
* +-------------------------------+
@@ -181,9 +181,16 @@
* 3. Length info of each component can be found in header, in dwords.
* 4. Modulus and exponent key are not required by driver. They may not appear
* in fw. So driver will load a truncated firmware in this case.
+ *
+ * HuC firmware layout is same as GuC firmware.
+ *
+ * HuC firmware css header is different. However, the only difference is where
+ * the version information is saved. The uc_css_header is unified to support
+ * both. Driver should get HuC version from uc_css_header.huc_sw_version, while
+ * uc_css_header.guc_sw_version for GuC.
*/
-struct guc_css_header {
+struct uc_css_header {
uint32_t module_type;
/* header_size includes all non-uCode bits, including css_header, rsa
* key, modulus key and exponent data. */
@@ -214,8 +221,14 @@ struct guc_css_header {
char username[8];
char buildnumber[12];
- uint32_t device_id;
- uint32_t guc_sw_version;
+ union {
+ uint32_t guc_branch_client_version;
+ uint32_t huc_sw_version;
+ };
+ union {
+ uint32_t guc_sw_version;
+ uint32_t huc_reserved;
+ };
uint32_t prod_preprod_fw;
uint32_t reserved[12];
uint32_t header_info;
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 6683a88..ff26d2c 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -593,7 +593,7 @@ void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw)
struct pci_dev *pdev = dev->pdev;
struct drm_i915_gem_object *obj;
const struct firmware *fw;
- struct guc_css_header *css;
+ struct uc_css_header *css;
size_t size;
int err;
@@ -610,19 +610,19 @@ void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw)
uc_fw->uc_fw_path, fw);
/* Check the size of the blob before examining buffer contents */
- if (fw->size < sizeof(struct guc_css_header)) {
+ if (fw->size < sizeof(struct uc_css_header)) {
DRM_NOTE("Firmware header is missing\n");
goto fail;
}
- css = (struct guc_css_header *)fw->data;
+ css = (struct uc_css_header *)fw->data;
/* Firmware bits always start from header */
uc_fw->header_offset = 0;
uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
- if (uc_fw->header_size != sizeof(struct guc_css_header)) {
+ if (uc_fw->header_size != sizeof(struct uc_css_header)) {
DRM_NOTE("CSS header definition mismatch\n");
goto fail;
}
@@ -646,21 +646,36 @@ void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw)
goto fail;
}
- /* Header and uCode will be loaded to WOPCM. Size of the two. */
- size = uc_fw->header_size + uc_fw->ucode_size;
- if (size > guc_wopcm_size(to_i915(dev))) {
- DRM_NOTE("Firmware is too large to fit in WOPCM\n");
- goto fail;
- }
-
/*
* The GuC firmware image has the version number embedded at a well-known
* offset within the firmware blob; note that major / minor version are
* TWO bytes each (i.e. u16), although all pointers and offsets are defined
* in terms of bytes (u8).
*/
- uc_fw->major_ver_found = css->guc_sw_version >> 16;
- uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
+ switch (uc_fw->fw_type) {
+ case UC_FW_TYPE_GUC:
+ /* Header and uCode will be loaded to WOPCM. Size of the two. */
+ size = uc_fw->header_size + uc_fw->ucode_size;
+
+ /* Top 32k of WOPCM is reserved (8K stack + 24k RC6 context). */
+ if (size > guc_wopcm_size(to_i915(dev))) {
+ DRM_ERROR("Firmware is too large to fit in WOPCM\n");
+ goto fail;
+ }
+ uc_fw->major_ver_found = css->guc_sw_version >> 16;
+ uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
+ break;
+
+ case UC_FW_TYPE_HUC:
+ uc_fw->major_ver_found = css->huc_sw_version >> 16;
+ uc_fw->minor_ver_found = css->huc_sw_version & 0xFFFF;
+ break;
+
+ default:
+ DRM_ERROR("Unknown firmware type %d\n", uc_fw->fw_type);
+ err = -ENOEXEC;
+ goto fail;
+ }
if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) {
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH 2/7] drm/i915/huc: Unified css_header struct for GuC and HuC
2016-10-29 0:05 ` [PATCH 2/7] drm/i915/huc: Unified css_header struct for GuC and HuC Anusha Srivatsa
@ 2016-10-31 20:02 ` Jeff McGee
0 siblings, 0 replies; 14+ messages in thread
From: Jeff McGee @ 2016-10-31 20:02 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx, Alex Dai, Peter Antoine
Reviewed-by: Jeff McGee <jeff.mcgee@intel.com>
On Fri, Oct 28, 2016 at 05:05:41PM -0700, Anusha Srivatsa wrote:
> From: Peter Antoine <peter.antoine@intel.com>
>
> HuC firmware css header has almost exactly same definition as GuC
> firmware except for the sw_version. Also, add a new member fw_type
> into intel_uc_fw to indicate what kind of fw it is. So, the loader
> will pull right sw_version from header.
>
> v2: rebased on-top of drm-intel-nightly
> v3: rebased on-top of drm-intel-nightly (again).
> v4: rebased + spaces.
> v7: rebased.
> v8: rebased.
> v9: rebased. Rename device_id to guc_branch_client_version,
> make guc_sw_version a union. <Jeff Mcgee>. Put UC_FW_TYPE_GUC
> and UC_FW_TYPE_HUC into an enum.
>
> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
> ---
> drivers/gpu/drm/i915/intel_guc.h | 6 +++++
> drivers/gpu/drm/i915/intel_guc_fwif.h | 21 +++++++++++++----
> drivers/gpu/drm/i915/intel_guc_loader.c | 41 ++++++++++++++++++++++-----------
> 3 files changed, 51 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
> index 186efa7..84ef2bf 100644
> --- a/drivers/gpu/drm/i915/intel_guc.h
> +++ b/drivers/gpu/drm/i915/intel_guc.h
> @@ -98,6 +98,11 @@ enum intel_uc_fw_status {
> UC_FIRMWARE_SUCCESS
> };
>
> +enum {
> + UC_FW_TYPE_GUC,
> + UC_FW_TYPE_HUC
> +};
> +
> /*
> * This structure encapsulates all the data needed during the process
> * of fetching, caching, and loading the firmware image into the GuC.
> @@ -115,6 +120,7 @@ struct intel_uc_fw {
> uint16_t major_ver_found;
> uint16_t minor_ver_found;
>
> + uint32_t fw_type;
> uint32_t header_size;
> uint32_t header_offset;
> uint32_t rsa_size;
> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
> index 324ea90..c2a7fdd 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> @@ -154,7 +154,7 @@
> * The GuC firmware layout looks like this:
> *
> * +-------------------------------+
> - * | guc_css_header |
> + * | uc_css_header |
> * | |
> * | contains major/minor version |
> * +-------------------------------+
> @@ -181,9 +181,16 @@
> * 3. Length info of each component can be found in header, in dwords.
> * 4. Modulus and exponent key are not required by driver. They may not appear
> * in fw. So driver will load a truncated firmware in this case.
> + *
> + * HuC firmware layout is same as GuC firmware.
> + *
> + * HuC firmware css header is different. However, the only difference is where
> + * the version information is saved. The uc_css_header is unified to support
> + * both. Driver should get HuC version from uc_css_header.huc_sw_version, while
> + * uc_css_header.guc_sw_version for GuC.
> */
>
> -struct guc_css_header {
> +struct uc_css_header {
> uint32_t module_type;
> /* header_size includes all non-uCode bits, including css_header, rsa
> * key, modulus key and exponent data. */
> @@ -214,8 +221,14 @@ struct guc_css_header {
>
> char username[8];
> char buildnumber[12];
> - uint32_t device_id;
> - uint32_t guc_sw_version;
> + union {
> + uint32_t guc_branch_client_version;
> + uint32_t huc_sw_version;
> + };
> + union {
> + uint32_t guc_sw_version;
> + uint32_t huc_reserved;
> + };
> uint32_t prod_preprod_fw;
> uint32_t reserved[12];
> uint32_t header_info;
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 6683a88..ff26d2c 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -593,7 +593,7 @@ void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw)
> struct pci_dev *pdev = dev->pdev;
> struct drm_i915_gem_object *obj;
> const struct firmware *fw;
> - struct guc_css_header *css;
> + struct uc_css_header *css;
> size_t size;
> int err;
>
> @@ -610,19 +610,19 @@ void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw)
> uc_fw->uc_fw_path, fw);
>
> /* Check the size of the blob before examining buffer contents */
> - if (fw->size < sizeof(struct guc_css_header)) {
> + if (fw->size < sizeof(struct uc_css_header)) {
> DRM_NOTE("Firmware header is missing\n");
> goto fail;
> }
>
> - css = (struct guc_css_header *)fw->data;
> + css = (struct uc_css_header *)fw->data;
>
> /* Firmware bits always start from header */
> uc_fw->header_offset = 0;
> uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
> css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
>
> - if (uc_fw->header_size != sizeof(struct guc_css_header)) {
> + if (uc_fw->header_size != sizeof(struct uc_css_header)) {
> DRM_NOTE("CSS header definition mismatch\n");
> goto fail;
> }
> @@ -646,21 +646,36 @@ void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw)
> goto fail;
> }
>
> - /* Header and uCode will be loaded to WOPCM. Size of the two. */
> - size = uc_fw->header_size + uc_fw->ucode_size;
> - if (size > guc_wopcm_size(to_i915(dev))) {
> - DRM_NOTE("Firmware is too large to fit in WOPCM\n");
> - goto fail;
> - }
> -
> /*
> * The GuC firmware image has the version number embedded at a well-known
> * offset within the firmware blob; note that major / minor version are
> * TWO bytes each (i.e. u16), although all pointers and offsets are defined
> * in terms of bytes (u8).
> */
> - uc_fw->major_ver_found = css->guc_sw_version >> 16;
> - uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
> + switch (uc_fw->fw_type) {
> + case UC_FW_TYPE_GUC:
> + /* Header and uCode will be loaded to WOPCM. Size of the two. */
> + size = uc_fw->header_size + uc_fw->ucode_size;
> +
> + /* Top 32k of WOPCM is reserved (8K stack + 24k RC6 context). */
> + if (size > guc_wopcm_size(to_i915(dev))) {
> + DRM_ERROR("Firmware is too large to fit in WOPCM\n");
> + goto fail;
> + }
> + uc_fw->major_ver_found = css->guc_sw_version >> 16;
> + uc_fw->minor_ver_found = css->guc_sw_version & 0xFFFF;
> + break;
> +
> + case UC_FW_TYPE_HUC:
> + uc_fw->major_ver_found = css->huc_sw_version >> 16;
> + uc_fw->minor_ver_found = css->huc_sw_version & 0xFFFF;
> + break;
> +
> + default:
> + DRM_ERROR("Unknown firmware type %d\n", uc_fw->fw_type);
> + err = -ENOEXEC;
> + goto fail;
> + }
>
> if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
> uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) {
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 3/7] drm/i915/huc: Add HuC fw loading support
2016-10-29 0:05 [PATCH 0/7] HuC Loading Patches Anusha Srivatsa
2016-10-29 0:05 ` [PATCH 1/7] drm/i915/guc: Make the GuC fw loading helper functions general Anusha Srivatsa
2016-10-29 0:05 ` [PATCH 2/7] drm/i915/huc: Unified css_header struct for GuC and HuC Anusha Srivatsa
@ 2016-10-29 0:05 ` Anusha Srivatsa
2016-10-31 20:21 ` Jeff McGee
2016-10-29 0:05 ` [PATCH 4/7] drm/i915/huc: Add debugfs for HuC loading status check Anusha Srivatsa
` (4 subsequent siblings)
7 siblings, 1 reply; 14+ messages in thread
From: Anusha Srivatsa @ 2016-10-29 0:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Alex Dai, Peter Antoine
From: Peter Antoine <peter.antoine@intel.com>
The HuC loading process is similar to GuC. The intel_uc_fw_fetch()
is used for both cases.
HuC loading needs to be before GuC loading. The WOPCM setting must
be done early before loading any of them.
v2: rebased on-top of drm-intel-nightly.
removed if(HAS_GUC()) before the guc call. (D.Gordon)
update huc_version number of format.
v3: rebased to drm-intel-nightly, changed the file name format to
match the one in the huc package.
Changed dev->dev_private to to_i915()
v4: moved function back to where it was.
change wait_for_atomic to wait_for.
v5: rebased + comment changes.
v7: rebased.
v8: rebased.
v9: rebased. Changed the year in the copyright message to reflect
the right year.Correct the comments,remove the unwanted WARN message,
replace drm_gem_object_unreference() with i915_gem_object_put().Make the
prototypes in intel_huc.h non-extern.
Tested-by: Xiang Haihao <haihao.xiang@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_drv.c | 3 +
drivers/gpu/drm/i915/i915_drv.h | 3 +
drivers/gpu/drm/i915/i915_guc_reg.h | 3 +
drivers/gpu/drm/i915/intel_guc.h | 1 +
drivers/gpu/drm/i915/intel_guc_loader.c | 6 +-
drivers/gpu/drm/i915/intel_huc.h | 42 ++++++
drivers/gpu/drm/i915/intel_huc_loader.c | 260 ++++++++++++++++++++++++++++++++
8 files changed, 317 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_huc.h
create mode 100644 drivers/gpu/drm/i915/intel_huc_loader.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 6123400..0528168 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -52,6 +52,7 @@ i915-y += i915_cmd_parser.o \
# general-purpose microcontroller (GuC) support
i915-y += intel_guc_loader.o \
+ intel_huc_loader.o \
i915_guc_submission.o
# autogenerated null render state
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index af3559d..2f36672 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -594,6 +594,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
* working irqs for e.g. gmbus and dp aux transfers. */
intel_modeset_init(dev);
+ intel_huc_init(dev);
intel_guc_init(dev);
ret = i915_gem_init(dev);
@@ -621,6 +622,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
DRM_ERROR("failed to idle hardware; continuing to unload!\n");
i915_gem_fini(dev);
cleanup_irq:
+ intel_huc_fini(dev);
intel_guc_fini(dev);
drm_irq_uninstall(dev);
intel_teardown_gmbus(dev);
@@ -1304,6 +1306,7 @@ void i915_driver_unload(struct drm_device *dev)
/* Flush any outstanding unpin_work. */
drain_workqueue(dev_priv->wq);
+ intel_huc_fini(dev);
intel_guc_fini(dev);
i915_gem_fini(dev);
intel_fbc_cleanup_cfb(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 55afb66..b0376f0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -55,6 +55,7 @@
#include "intel_bios.h"
#include "intel_dpll_mgr.h"
#include "intel_guc.h"
+#include "intel_huc.h"
#include "intel_lrc.h"
#include "intel_ringbuffer.h"
@@ -1786,6 +1787,7 @@ struct drm_i915_private {
struct intel_gvt *gvt;
+ struct intel_huc huc;
struct intel_guc guc;
struct intel_csr csr;
@@ -2837,6 +2839,7 @@ struct drm_i915_cmd_table {
#define HAS_GUC(dev) (INTEL_INFO(dev)->has_guc)
#define HAS_GUC_UCODE(dev) (HAS_GUC(dev))
#define HAS_GUC_SCHED(dev) (HAS_GUC(dev))
+#define HAS_HUC_UCODE(dev) (HAS_GUC(dev))
#define HAS_RESOURCE_STREAMER(dev) (INTEL_INFO(dev)->has_resource_streamer)
diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h
index a47e1e4..64e942a 100644
--- a/drivers/gpu/drm/i915/i915_guc_reg.h
+++ b/drivers/gpu/drm/i915/i915_guc_reg.h
@@ -61,9 +61,12 @@
#define DMA_ADDRESS_SPACE_GTT (8 << 16)
#define DMA_COPY_SIZE _MMIO(0xc310)
#define DMA_CTRL _MMIO(0xc314)
+#define HUC_UKERNEL (1<<9)
#define UOS_MOVE (1<<4)
#define START_DMA (1<<0)
#define DMA_GUC_WOPCM_OFFSET _MMIO(0xc340)
+#define HUC_LOADING_AGENT_VCR (0<<1)
+#define HUC_LOADING_AGENT_GUC (1<<1)
#define GUC_WOPCM_OFFSET_VALUE 0x80000 /* 512KB */
#define GUC_MAX_IDLE_COUNT _MMIO(0xC3E4)
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 84ef2bf..4647e41 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -183,6 +183,7 @@ extern const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status);
extern int intel_guc_suspend(struct drm_device *dev);
extern int intel_guc_resume(struct drm_device *dev);
void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw);
+u32 guc_wopcm_size(struct drm_i915_private *dev_priv);
/* i915_guc_submission.c */
int i915_guc_submission_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index ff26d2c..dc79968 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -309,7 +309,8 @@ static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
/* Finally start the DMA */
- I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
+ I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA) |
+ _MASKED_BIT_DISABLE(HUC_UKERNEL));
/*
* Wait for the DMA to complete & the GuC to start up.
@@ -334,7 +335,7 @@ static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
return ret;
}
-static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
+u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
{
u32 wopcm_size = GUC_WOPCM_TOP;
@@ -512,6 +513,7 @@ int intel_guc_setup(struct drm_device *dev)
if (err)
goto fail;
+ intel_huc_load(dev);
err = guc_ucode_xfer(dev_priv);
if (!err)
break;
diff --git a/drivers/gpu/drm/i915/intel_huc.h b/drivers/gpu/drm/i915/intel_huc.h
new file mode 100644
index 0000000..3ce0299
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_huc.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+#ifndef _INTEL_HUC_H_
+#define _INTEL_HUC_H_
+
+#include "intel_guc.h"
+
+#define HUC_STATUS2 _MMIO(0xD3B0)
+#define HUC_FW_VERIFIED (1<<7)
+
+struct intel_huc {
+ /* Generic uC firmware management */
+ struct intel_uc_fw huc_fw;
+
+ /* HuC-specific additions */
+};
+
+void intel_huc_init(struct drm_device *dev);
+void intel_huc_fini(struct drm_device *dev);
+int intel_huc_load(struct drm_device *dev);
+#endif
diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
new file mode 100644
index 0000000..dcd9970
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_huc_loader.c
@@ -0,0 +1,260 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+#include <linux/firmware.h>
+#include "i915_drv.h"
+#include "intel_huc.h"
+
+/**
+ * DOC: HuC Firmware
+ *
+ * Motivation:
+ * GEN9 introduces a new dedicated firmware for usage in media HEVC (High
+ * Efficiency Video Coding) operations. Userspace can use the firmware
+ * capabilities by adding HuC specific commands to batch buffers.
+ *
+ * Implementation:
+ * The same firmware loader is used as the GuC. However, the actual
+ * loading to HW is deferred until GEM initialization is done.
+ *
+ * Note that HuC firmware loading must be done before GuC loading.
+ */
+
+#define I915_SKL_HUC_UCODE "i915/skl_huc_ver01_07_1398.bin"
+MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
+
+/**
+ * huc_ucode_xfer() - DMA's the firmware
+ * @dev_priv: the drm device
+ *
+ * This function takes the gem object containing the firmware, sets up the DMA
+ * engine MMIO, triggers the DMA operation and waits for it to finish.
+ *
+ * Transfer the firmware image to RAM for execution by the microcontroller.
+ *
+ * Return: 0 on success, non-zero on failure
+ */
+
+static int huc_ucode_xfer(struct drm_i915_private *dev_priv)
+{
+ struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
+ struct i915_vma *vma;
+ unsigned long offset = 0;
+ u32 size;
+ int ret;
+
+ ret = i915_gem_object_set_to_gtt_domain(huc_fw->uc_fw_obj, false);
+ if (ret) {
+ DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
+ return ret;
+ }
+
+ vma = i915_gem_object_ggtt_pin(huc_fw->uc_fw_obj, NULL, 0, 0, 0);
+ if (IS_ERR(vma)) {
+ DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
+ return PTR_ERR(vma);
+ }
+
+ /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
+ I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
+
+ intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+
+ /* init WOPCM */
+ I915_WRITE(GUC_WOPCM_SIZE, guc_wopcm_size(dev_priv));
+ I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE |
+ HUC_LOADING_AGENT_GUC);
+
+ /* Set the source address for the uCode */
+ offset = i915_ggtt_offset(vma) + huc_fw->header_offset;
+ I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
+ I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
+
+ /* Hardware doesn't look at destination address for HuC. Set it to 0,
+ * but still program the correct address space.
+ */
+ I915_WRITE(DMA_ADDR_1_LOW, 0);
+ I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
+
+ size = huc_fw->header_size + huc_fw->ucode_size;
+ I915_WRITE(DMA_COPY_SIZE, size);
+
+ /* Start the DMA */
+ I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA));
+
+ /* Wait for DMA to finish */
+ ret = wait_for((I915_READ(DMA_CTRL) & START_DMA) == 0, 100);
+
+ DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret);
+
+ intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+ /*
+ * We keep the object pages for reuse during resume. But we can unpin it
+ * now that DMA has completed, so it doesn't continue to take up space.
+ */
+ i915_vma_unpin(vma);
+
+ return ret;
+}
+
+/**
+ * intel_huc_init() - initiate HuC firmware loading request
+ * @dev: the drm device
+ *
+ * Called early during driver load, but after GEM is initialised. The loading
+ * will continue only when driver explicitly specify firmware name and version.
+ * All other cases are considered as UC_FIRMWARE_NONE either because HW is not
+ * capable or driver yet support it. And there will be no error message for
+ * UC_FIRMWARE_NONE cases.
+ *
+ * The DMA-copying to HW is done later when intel_huc_load() is called.
+ */
+void intel_huc_init(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_huc *huc = &dev_priv->huc;
+ struct intel_uc_fw *huc_fw = &huc->huc_fw;
+ const char *fw_path = NULL;
+
+ huc_fw->uc_dev = dev;
+ huc_fw->uc_fw_path = NULL;
+ huc_fw->fetch_status = UC_FIRMWARE_NONE;
+ huc_fw->load_status = UC_FIRMWARE_NONE;
+ huc_fw->fw_type = UC_FW_TYPE_HUC;
+
+ if (!HAS_HUC_UCODE(dev_priv))
+ return;
+
+ if (IS_SKYLAKE(dev_priv)) {
+ fw_path = I915_SKL_HUC_UCODE;
+ huc_fw->major_ver_wanted = 1;
+ huc_fw->minor_ver_wanted = 7;
+ }
+
+ if (fw_path == NULL)
+ return;
+
+ huc_fw->uc_fw_path = fw_path;
+ huc_fw->fetch_status = UC_FIRMWARE_PENDING;
+
+ DRM_DEBUG_DRIVER("HuC firmware pending, path %s\n", fw_path);
+
+ intel_uc_fw_fetch(dev, huc_fw);
+}
+
+/**
+ * intel_huc_load() - load HuC uCode to device
+ * @dev: the drm device
+ *
+ * Called from gem_init_hw() during driver loading and also after a GPU reset.
+ * Be note that HuC loading must be done before GuC loading.
+ *
+ * The firmware image should have already been fetched into memory by the
+ * earlier call to intel_huc_ucode_init(), so here we need only check that
+ * is succeeded, and then transfer the image to the h/w.
+ *
+ * Return: non-zero code on error
+ */
+int intel_huc_load(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
+ int err;
+
+ if (huc_fw->fetch_status == UC_FIRMWARE_NONE)
+ return 0;
+
+ DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n",
+ huc_fw->uc_fw_path,
+ intel_uc_fw_status_repr(huc_fw->fetch_status),
+ intel_uc_fw_status_repr(huc_fw->load_status));
+
+ if (huc_fw->fetch_status == UC_FIRMWARE_SUCCESS &&
+ huc_fw->load_status == UC_FIRMWARE_FAIL)
+ return -ENOEXEC;
+
+ huc_fw->load_status = UC_FIRMWARE_PENDING;
+
+ switch (huc_fw->fetch_status) {
+ case UC_FIRMWARE_FAIL:
+ /* something went wrong :( */
+ err = -EIO;
+ goto fail;
+
+ case UC_FIRMWARE_NONE:
+ case UC_FIRMWARE_PENDING:
+ default:
+ /* "can't happen" */
+ WARN_ONCE(1, "HuC fw %s invalid fetch_status %s [%d]\n",
+ huc_fw->uc_fw_path,
+ intel_uc_fw_status_repr(huc_fw->fetch_status),
+ huc_fw->fetch_status);
+ err = -ENXIO;
+ goto fail;
+
+ case UC_FIRMWARE_SUCCESS:
+ break;
+ }
+
+ err = huc_ucode_xfer(dev_priv);
+ if (err)
+ goto fail;
+
+ huc_fw->load_status = UC_FIRMWARE_SUCCESS;
+
+ DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n",
+ huc_fw->uc_fw_path,
+ intel_uc_fw_status_repr(huc_fw->fetch_status),
+ intel_uc_fw_status_repr(huc_fw->load_status));
+
+ return 0;
+
+fail:
+ if (huc_fw->load_status == UC_FIRMWARE_PENDING)
+ huc_fw->load_status = UC_FIRMWARE_FAIL;
+
+ DRM_ERROR("Failed to complete HuC uCode load with ret %d\n", err);
+
+ return err;
+}
+
+/**
+ * intel_huc_fini() - clean up resources allocated for HuC
+ * @dev: the drm device
+ *
+ * Cleans up by releasing the huc firmware GEM obj.
+ */
+void intel_huc_fini(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
+
+ mutex_lock(&dev->struct_mutex);
+ if (huc_fw->uc_fw_obj)
+ i915_gem_object_put(huc_fw->uc_fw_obj);
+ huc_fw->uc_fw_obj = NULL;
+ mutex_unlock(&dev->struct_mutex);
+
+ huc_fw->fetch_status = UC_FIRMWARE_NONE;
+}
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH 3/7] drm/i915/huc: Add HuC fw loading support
2016-10-29 0:05 ` [PATCH 3/7] drm/i915/huc: Add HuC fw loading support Anusha Srivatsa
@ 2016-10-31 20:21 ` Jeff McGee
0 siblings, 0 replies; 14+ messages in thread
From: Jeff McGee @ 2016-10-31 20:21 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx, Alex Dai, Peter Antoine
On Fri, Oct 28, 2016 at 05:05:42PM -0700, Anusha Srivatsa wrote:
> From: Peter Antoine <peter.antoine@intel.com>
>
> The HuC loading process is similar to GuC. The intel_uc_fw_fetch()
> is used for both cases.
>
> HuC loading needs to be before GuC loading. The WOPCM setting must
> be done early before loading any of them.
>
> v2: rebased on-top of drm-intel-nightly.
> removed if(HAS_GUC()) before the guc call. (D.Gordon)
> update huc_version number of format.
> v3: rebased to drm-intel-nightly, changed the file name format to
> match the one in the huc package.
> Changed dev->dev_private to to_i915()
> v4: moved function back to where it was.
> change wait_for_atomic to wait_for.
> v5: rebased + comment changes.
> v7: rebased.
> v8: rebased.
> v9: rebased. Changed the year in the copyright message to reflect
> the right year.Correct the comments,remove the unwanted WARN message,
> replace drm_gem_object_unreference() with i915_gem_object_put().Make the
> prototypes in intel_huc.h non-extern.
>
> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/i915_drv.c | 3 +
> drivers/gpu/drm/i915/i915_drv.h | 3 +
> drivers/gpu/drm/i915/i915_guc_reg.h | 3 +
> drivers/gpu/drm/i915/intel_guc.h | 1 +
> drivers/gpu/drm/i915/intel_guc_loader.c | 6 +-
> drivers/gpu/drm/i915/intel_huc.h | 42 ++++++
> drivers/gpu/drm/i915/intel_huc_loader.c | 260 ++++++++++++++++++++++++++++++++
> 8 files changed, 317 insertions(+), 2 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/intel_huc.h
> create mode 100644 drivers/gpu/drm/i915/intel_huc_loader.c
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 6123400..0528168 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -52,6 +52,7 @@ i915-y += i915_cmd_parser.o \
>
> # general-purpose microcontroller (GuC) support
> i915-y += intel_guc_loader.o \
> + intel_huc_loader.o \
> i915_guc_submission.o
>
> # autogenerated null render state
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index af3559d..2f36672 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -594,6 +594,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
> * working irqs for e.g. gmbus and dp aux transfers. */
> intel_modeset_init(dev);
>
> + intel_huc_init(dev);
> intel_guc_init(dev);
>
> ret = i915_gem_init(dev);
> @@ -621,6 +622,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
> DRM_ERROR("failed to idle hardware; continuing to unload!\n");
> i915_gem_fini(dev);
> cleanup_irq:
> + intel_huc_fini(dev);
> intel_guc_fini(dev);
> drm_irq_uninstall(dev);
> intel_teardown_gmbus(dev);
> @@ -1304,6 +1306,7 @@ void i915_driver_unload(struct drm_device *dev)
> /* Flush any outstanding unpin_work. */
> drain_workqueue(dev_priv->wq);
>
> + intel_huc_fini(dev);
> intel_guc_fini(dev);
> i915_gem_fini(dev);
> intel_fbc_cleanup_cfb(dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 55afb66..b0376f0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -55,6 +55,7 @@
> #include "intel_bios.h"
> #include "intel_dpll_mgr.h"
> #include "intel_guc.h"
> +#include "intel_huc.h"
> #include "intel_lrc.h"
> #include "intel_ringbuffer.h"
>
> @@ -1786,6 +1787,7 @@ struct drm_i915_private {
>
> struct intel_gvt *gvt;
>
> + struct intel_huc huc;
> struct intel_guc guc;
>
> struct intel_csr csr;
> @@ -2837,6 +2839,7 @@ struct drm_i915_cmd_table {
> #define HAS_GUC(dev) (INTEL_INFO(dev)->has_guc)
> #define HAS_GUC_UCODE(dev) (HAS_GUC(dev))
> #define HAS_GUC_SCHED(dev) (HAS_GUC(dev))
> +#define HAS_HUC_UCODE(dev) (HAS_GUC(dev))
>
> #define HAS_RESOURCE_STREAMER(dev) (INTEL_INFO(dev)->has_resource_streamer)
>
> diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h
> index a47e1e4..64e942a 100644
> --- a/drivers/gpu/drm/i915/i915_guc_reg.h
> +++ b/drivers/gpu/drm/i915/i915_guc_reg.h
> @@ -61,9 +61,12 @@
> #define DMA_ADDRESS_SPACE_GTT (8 << 16)
> #define DMA_COPY_SIZE _MMIO(0xc310)
> #define DMA_CTRL _MMIO(0xc314)
> +#define HUC_UKERNEL (1<<9)
> #define UOS_MOVE (1<<4)
> #define START_DMA (1<<0)
> #define DMA_GUC_WOPCM_OFFSET _MMIO(0xc340)
> +#define HUC_LOADING_AGENT_VCR (0<<1)
> +#define HUC_LOADING_AGENT_GUC (1<<1)
> #define GUC_WOPCM_OFFSET_VALUE 0x80000 /* 512KB */
> #define GUC_MAX_IDLE_COUNT _MMIO(0xC3E4)
>
> diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
> index 84ef2bf..4647e41 100644
> --- a/drivers/gpu/drm/i915/intel_guc.h
> +++ b/drivers/gpu/drm/i915/intel_guc.h
> @@ -183,6 +183,7 @@ extern const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status);
> extern int intel_guc_suspend(struct drm_device *dev);
> extern int intel_guc_resume(struct drm_device *dev);
> void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw);
> +u32 guc_wopcm_size(struct drm_i915_private *dev_priv);
>
> /* i915_guc_submission.c */
> int i915_guc_submission_init(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index ff26d2c..dc79968 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -309,7 +309,8 @@ static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
> I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
>
> /* Finally start the DMA */
> - I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
> + I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA) |
> + _MASKED_BIT_DISABLE(HUC_UKERNEL));
>
> /*
> * Wait for the DMA to complete & the GuC to start up.
> @@ -334,7 +335,7 @@ static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
> return ret;
> }
>
> -static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
> +u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
> {
> u32 wopcm_size = GUC_WOPCM_TOP;
>
> @@ -512,6 +513,7 @@ int intel_guc_setup(struct drm_device *dev)
> if (err)
> goto fail;
>
> + intel_huc_load(dev);
> err = guc_ucode_xfer(dev_priv);
> if (!err)
> break;
> diff --git a/drivers/gpu/drm/i915/intel_huc.h b/drivers/gpu/drm/i915/intel_huc.h
> new file mode 100644
> index 0000000..3ce0299
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_huc.h
> @@ -0,0 +1,42 @@
> +/*
> + * Copyright © 2016 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + *
> + */
> +#ifndef _INTEL_HUC_H_
> +#define _INTEL_HUC_H_
> +
> +#include "intel_guc.h"
> +
> +#define HUC_STATUS2 _MMIO(0xD3B0)
> +#define HUC_FW_VERIFIED (1<<7)
> +
> +struct intel_huc {
> + /* Generic uC firmware management */
> + struct intel_uc_fw huc_fw;
> +
> + /* HuC-specific additions */
> +};
> +
> +void intel_huc_init(struct drm_device *dev);
> +void intel_huc_fini(struct drm_device *dev);
> +int intel_huc_load(struct drm_device *dev);
> +#endif
> diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
> new file mode 100644
> index 0000000..dcd9970
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_huc_loader.c
> @@ -0,0 +1,260 @@
> +/*
> + * Copyright © 2016 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + *
> + */
> +#include <linux/firmware.h>
> +#include "i915_drv.h"
> +#include "intel_huc.h"
> +
> +/**
> + * DOC: HuC Firmware
> + *
> + * Motivation:
> + * GEN9 introduces a new dedicated firmware for usage in media HEVC (High
> + * Efficiency Video Coding) operations. Userspace can use the firmware
> + * capabilities by adding HuC specific commands to batch buffers.
> + *
> + * Implementation:
> + * The same firmware loader is used as the GuC. However, the actual
> + * loading to HW is deferred until GEM initialization is done.
> + *
> + * Note that HuC firmware loading must be done before GuC loading.
> + */
> +
> +#define I915_SKL_HUC_UCODE "i915/skl_huc_ver01_07_1398.bin"
> +MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
Please update to use the new approach used by GuC for specifying
required version and constructing the file path. See intel_guc_loader.c.
HuC firmware versioning includes the build number after the minor so
some modification will be needed.
Example... (not tested)
#define SKL_HUC_FW_MAJOR 01
#define SKL_HUC_FW_MINOR 07
#define SKL_HUC_FW_BUILD 1398
#define HUC_FW_PATH(platform, major, minor, build) \
"i915/" __stringify(platform) "_huc_ver" \
__stringify(major) "_" __stringify(minor) "_" __stringify(build) ".bin"
#define I915_SKL_HUC_UCODE HUC_FW_PATH(skl, SKL_HUC_FW_MAJOR, SKL_HUC_FW_MINOR, SKL_HUC_FW_BUILD)
MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
-Jeff
> +
> +/**
> + * huc_ucode_xfer() - DMA's the firmware
> + * @dev_priv: the drm device
> + *
> + * This function takes the gem object containing the firmware, sets up the DMA
> + * engine MMIO, triggers the DMA operation and waits for it to finish.
> + *
> + * Transfer the firmware image to RAM for execution by the microcontroller.
> + *
> + * Return: 0 on success, non-zero on failure
> + */
> +
> +static int huc_ucode_xfer(struct drm_i915_private *dev_priv)
> +{
> + struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
> + struct i915_vma *vma;
> + unsigned long offset = 0;
> + u32 size;
> + int ret;
> +
> + ret = i915_gem_object_set_to_gtt_domain(huc_fw->uc_fw_obj, false);
> + if (ret) {
> + DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
> + return ret;
> + }
> +
> + vma = i915_gem_object_ggtt_pin(huc_fw->uc_fw_obj, NULL, 0, 0, 0);
> + if (IS_ERR(vma)) {
> + DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
> + return PTR_ERR(vma);
> + }
> +
> + /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
> + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
> +
> + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> +
> + /* init WOPCM */
> + I915_WRITE(GUC_WOPCM_SIZE, guc_wopcm_size(dev_priv));
> + I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE |
> + HUC_LOADING_AGENT_GUC);
> +
> + /* Set the source address for the uCode */
> + offset = i915_ggtt_offset(vma) + huc_fw->header_offset;
> + I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
> + I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
> +
> + /* Hardware doesn't look at destination address for HuC. Set it to 0,
> + * but still program the correct address space.
> + */
> + I915_WRITE(DMA_ADDR_1_LOW, 0);
> + I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
> +
> + size = huc_fw->header_size + huc_fw->ucode_size;
> + I915_WRITE(DMA_COPY_SIZE, size);
> +
> + /* Start the DMA */
> + I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA));
> +
> + /* Wait for DMA to finish */
> + ret = wait_for((I915_READ(DMA_CTRL) & START_DMA) == 0, 100);
> +
> + DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret);
> +
> + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> +
> + /*
> + * We keep the object pages for reuse during resume. But we can unpin it
> + * now that DMA has completed, so it doesn't continue to take up space.
> + */
> + i915_vma_unpin(vma);
> +
> + return ret;
> +}
> +
> +/**
> + * intel_huc_init() - initiate HuC firmware loading request
> + * @dev: the drm device
> + *
> + * Called early during driver load, but after GEM is initialised. The loading
> + * will continue only when driver explicitly specify firmware name and version.
> + * All other cases are considered as UC_FIRMWARE_NONE either because HW is not
> + * capable or driver yet support it. And there will be no error message for
> + * UC_FIRMWARE_NONE cases.
> + *
> + * The DMA-copying to HW is done later when intel_huc_load() is called.
> + */
> +void intel_huc_init(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_huc *huc = &dev_priv->huc;
> + struct intel_uc_fw *huc_fw = &huc->huc_fw;
> + const char *fw_path = NULL;
> +
> + huc_fw->uc_dev = dev;
> + huc_fw->uc_fw_path = NULL;
> + huc_fw->fetch_status = UC_FIRMWARE_NONE;
> + huc_fw->load_status = UC_FIRMWARE_NONE;
> + huc_fw->fw_type = UC_FW_TYPE_HUC;
> +
> + if (!HAS_HUC_UCODE(dev_priv))
> + return;
> +
> + if (IS_SKYLAKE(dev_priv)) {
> + fw_path = I915_SKL_HUC_UCODE;
> + huc_fw->major_ver_wanted = 1;
> + huc_fw->minor_ver_wanted = 7;
> + }
With above change we can use SKL_HUC_FW_MAJOR and SKL_HUC_FW_MINOR macros
here instead of hardcoded values. Now version and filename update can be
made cleanly in one place.
-Jeff
> +
> + if (fw_path == NULL)
> + return;
> +
> + huc_fw->uc_fw_path = fw_path;
> + huc_fw->fetch_status = UC_FIRMWARE_PENDING;
> +
> + DRM_DEBUG_DRIVER("HuC firmware pending, path %s\n", fw_path);
> +
> + intel_uc_fw_fetch(dev, huc_fw);
> +}
> +
> +/**
> + * intel_huc_load() - load HuC uCode to device
> + * @dev: the drm device
> + *
> + * Called from gem_init_hw() during driver loading and also after a GPU reset.
> + * Be note that HuC loading must be done before GuC loading.
> + *
> + * The firmware image should have already been fetched into memory by the
> + * earlier call to intel_huc_ucode_init(), so here we need only check that
> + * is succeeded, and then transfer the image to the h/w.
> + *
> + * Return: non-zero code on error
> + */
> +int intel_huc_load(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
> + int err;
> +
> + if (huc_fw->fetch_status == UC_FIRMWARE_NONE)
> + return 0;
> +
> + DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n",
> + huc_fw->uc_fw_path,
> + intel_uc_fw_status_repr(huc_fw->fetch_status),
> + intel_uc_fw_status_repr(huc_fw->load_status));
> +
> + if (huc_fw->fetch_status == UC_FIRMWARE_SUCCESS &&
> + huc_fw->load_status == UC_FIRMWARE_FAIL)
> + return -ENOEXEC;
> +
> + huc_fw->load_status = UC_FIRMWARE_PENDING;
> +
> + switch (huc_fw->fetch_status) {
> + case UC_FIRMWARE_FAIL:
> + /* something went wrong :( */
> + err = -EIO;
> + goto fail;
> +
> + case UC_FIRMWARE_NONE:
> + case UC_FIRMWARE_PENDING:
> + default:
> + /* "can't happen" */
> + WARN_ONCE(1, "HuC fw %s invalid fetch_status %s [%d]\n",
> + huc_fw->uc_fw_path,
> + intel_uc_fw_status_repr(huc_fw->fetch_status),
> + huc_fw->fetch_status);
> + err = -ENXIO;
> + goto fail;
> +
> + case UC_FIRMWARE_SUCCESS:
> + break;
> + }
> +
> + err = huc_ucode_xfer(dev_priv);
> + if (err)
> + goto fail;
> +
> + huc_fw->load_status = UC_FIRMWARE_SUCCESS;
> +
> + DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n",
> + huc_fw->uc_fw_path,
> + intel_uc_fw_status_repr(huc_fw->fetch_status),
> + intel_uc_fw_status_repr(huc_fw->load_status));
> +
> + return 0;
> +
> +fail:
> + if (huc_fw->load_status == UC_FIRMWARE_PENDING)
> + huc_fw->load_status = UC_FIRMWARE_FAIL;
> +
> + DRM_ERROR("Failed to complete HuC uCode load with ret %d\n", err);
> +
> + return err;
> +}
> +
> +/**
> + * intel_huc_fini() - clean up resources allocated for HuC
> + * @dev: the drm device
> + *
> + * Cleans up by releasing the huc firmware GEM obj.
> + */
> +void intel_huc_fini(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
> +
> + mutex_lock(&dev->struct_mutex);
> + if (huc_fw->uc_fw_obj)
> + i915_gem_object_put(huc_fw->uc_fw_obj);
> + huc_fw->uc_fw_obj = NULL;
> + mutex_unlock(&dev->struct_mutex);
> +
> + huc_fw->fetch_status = UC_FIRMWARE_NONE;
> +}
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 4/7] drm/i915/huc: Add debugfs for HuC loading status check
2016-10-29 0:05 [PATCH 0/7] HuC Loading Patches Anusha Srivatsa
` (2 preceding siblings ...)
2016-10-29 0:05 ` [PATCH 3/7] drm/i915/huc: Add HuC fw loading support Anusha Srivatsa
@ 2016-10-29 0:05 ` Anusha Srivatsa
2016-10-29 0:05 ` [PATCH 5/7] drm/i915/huc: Support HuC authentication Anusha Srivatsa
` (3 subsequent siblings)
7 siblings, 0 replies; 14+ messages in thread
From: Anusha Srivatsa @ 2016-10-29 0:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Alex Dai, Peter Antoine
From: Peter Antoine <peter.antoine@intel.com>
Add debugfs entry for HuC loading status check.
v2: rebase on-top of drm-intel-nightly.
v3: rebased again.
v7: rebased.
v8: rebased.
v9: rebased.
Tested-by: Xiang Haihao <haihao.xiang@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Jeff McGee <jeff.mcgee@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 3e68d32..cc20b45e 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2373,6 +2373,36 @@ static int i915_llc(struct seq_file *m, void *data)
return 0;
}
+static int i915_huc_load_status_info(struct seq_file *m, void *data)
+{
+ struct drm_i915_private *dev_priv = node_to_i915(m->private);
+ struct intel_uc_fw *huc_fw = &dev_priv->huc.huc_fw;
+
+ if (!HAS_HUC_UCODE(dev_priv))
+ return 0;
+
+ seq_puts(m, "HuC firmware status:\n");
+ seq_printf(m, "\tpath: %s\n", huc_fw->uc_fw_path);
+ seq_printf(m, "\tfetch: %s\n",
+ intel_uc_fw_status_repr(huc_fw->fetch_status));
+ seq_printf(m, "\tload: %s\n",
+ intel_uc_fw_status_repr(huc_fw->load_status));
+ seq_printf(m, "\tversion wanted: %d.%d\n",
+ huc_fw->major_ver_wanted, huc_fw->minor_ver_wanted);
+ seq_printf(m, "\tversion found: %d.%d\n",
+ huc_fw->major_ver_found, huc_fw->minor_ver_found);
+ seq_printf(m, "\theader: offset is %d; size = %d\n",
+ huc_fw->header_offset, huc_fw->header_size);
+ seq_printf(m, "\tuCode: offset is %d; size = %d\n",
+ huc_fw->ucode_offset, huc_fw->ucode_size);
+ seq_printf(m, "\tRSA: offset is %d; size = %d\n",
+ huc_fw->rsa_offset, huc_fw->rsa_size);
+
+ seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2));
+
+ return 0;
+}
+
static int i915_guc_load_status_info(struct seq_file *m, void *data)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -5433,6 +5463,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_guc_info", i915_guc_info, 0},
{"i915_guc_load_status", i915_guc_load_status_info, 0},
{"i915_guc_log_dump", i915_guc_log_dump, 0},
+ {"i915_huc_load_status", i915_huc_load_status_info, 0},
{"i915_frequency_info", i915_frequency_info, 0},
{"i915_hangcheck_info", i915_hangcheck_info, 0},
{"i915_drpc_info", i915_drpc_info, 0},
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 5/7] drm/i915/huc: Support HuC authentication
2016-10-29 0:05 [PATCH 0/7] HuC Loading Patches Anusha Srivatsa
` (3 preceding siblings ...)
2016-10-29 0:05 ` [PATCH 4/7] drm/i915/huc: Add debugfs for HuC loading status check Anusha Srivatsa
@ 2016-10-29 0:05 ` Anusha Srivatsa
2016-10-31 20:26 ` Jeff McGee
2016-10-29 0:05 ` [PATCH 6/7] drm/i915/huc: Add BXT HuC Loading Support Anusha Srivatsa
` (2 subsequent siblings)
7 siblings, 1 reply; 14+ messages in thread
From: Anusha Srivatsa @ 2016-10-29 0:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Alex Dai, Peter Antoine
From: Peter Antoine <peter.antoine@intel.com>
The HuC authentication is done by host2guc call. The HuC RSA keys
are sent to GuC for authentication.
v2: rebased on top of drm-intel-nightly.
changed name format and upped version 1.7.
v3: rebased on top of drm-intel-nightly.
v4: changed wait_for_automic to wait_for
v5: rebased.
v7: rebased.
v8: rebased.
v9: rebased. Rename intel_huc_auh() to intel_guc_auth_huc()
and place the prototype in intel_guc.h,correct the comments.
Tested-by: Xiang Haihao <haihao.xiang@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
---
drivers/gpu/drm/i915/i915_guc_submission.c | 63 ++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_guc.h | 2 +-
drivers/gpu/drm/i915/intel_guc_fwif.h | 1 +
drivers/gpu/drm/i915/intel_guc_loader.c | 2 +
4 files changed, 67 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index 99dc5d9..936eefc 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -27,6 +27,7 @@
#include <linux/relay.h>
#include "i915_drv.h"
#include "intel_guc.h"
+#include "intel_huc.h"
/**
* DOC: GuC-based command submission
@@ -1713,3 +1714,65 @@ int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val)
return ret;
}
+
+/**
+ * intel_guc_auth_huc() - authenticate ucode
+ * @dev: the drm device
+ *
+ * Triggers a HuC fw authentication request to the GuC via host-2-guc
+ * interface.
+ */
+void intel_guc_auth_huc(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_guc *guc = &dev_priv->guc;
+ struct intel_huc *huc = &dev_priv->huc;
+ struct i915_vma *vma;
+ int ret;
+ u32 data[2];
+
+ /* Bypass the case where there is no HuC firmware */
+ if (huc->huc_fw.fetch_status == UC_FIRMWARE_NONE ||
+ huc->huc_fw.load_status == UC_FIRMWARE_NONE)
+ return;
+
+ if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS) {
+ DRM_ERROR("HuC: GuC fw wasn't loaded. Can't authenticate");
+ return;
+ }
+
+ if (huc->huc_fw.load_status != UC_FIRMWARE_SUCCESS) {
+ DRM_ERROR("HuC: fw wasn't loaded. Nothing to authenticate");
+ return;
+ }
+
+ vma = i915_gem_object_ggtt_pin(huc->huc_fw.uc_fw_obj, NULL, 0, 0, 0);
+ if (IS_ERR(vma)) {
+ DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
+ return;
+ }
+
+
+ /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
+ I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
+
+ /* Specify auth action and where public signature is. */
+ data[0] = HOST2GUC_ACTION_AUTHENTICATE_HUC;
+ data[1] = i915_ggtt_offset(vma) + huc->huc_fw.rsa_offset;
+
+ ret = host2guc_action(guc, data, ARRAY_SIZE(data));
+ if (ret) {
+ DRM_ERROR("HuC: GuC did not ack Auth request\n");
+ goto out;
+ }
+
+ /* Check authentication status, it should be done by now */
+ ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0, 50);
+ if (ret) {
+ DRM_ERROR("HuC: Authentication failed\n");
+ goto out;
+ }
+
+out:
+ i915_vma_unpin(vma);
+}
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 4647e41..ffdd5b9 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -197,5 +197,5 @@ void i915_guc_flush_logs(struct drm_i915_private *dev_priv);
void i915_guc_register(struct drm_i915_private *dev_priv);
void i915_guc_unregister(struct drm_i915_private *dev_priv);
int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val);
-
+void intel_guc_auth_huc(struct drm_device *dev);
#endif
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index c2a7fdd..99a092d 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -513,6 +513,7 @@ enum host2guc_action {
HOST2GUC_ACTION_EXIT_S_STATE = 0x502,
HOST2GUC_ACTION_SLPC_REQUEST = 0x3003,
HOST2GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
+ HOST2GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
HOST2GUC_ACTION_LIMIT
};
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index dc79968..11e3bbb 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -531,6 +531,8 @@ int intel_guc_setup(struct drm_device *dev)
intel_uc_fw_status_repr(guc_fw->fetch_status),
intel_uc_fw_status_repr(guc_fw->load_status));
+ intel_guc_auth_huc(dev);
+
if (i915.enable_guc_submission) {
if (i915.guc_log_level >= 0)
gen9_enable_guc_interrupts(dev_priv);
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH 5/7] drm/i915/huc: Support HuC authentication
2016-10-29 0:05 ` [PATCH 5/7] drm/i915/huc: Support HuC authentication Anusha Srivatsa
@ 2016-10-31 20:26 ` Jeff McGee
0 siblings, 0 replies; 14+ messages in thread
From: Jeff McGee @ 2016-10-31 20:26 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx, Alex Dai, Peter Antoine
Reviewed-by: Jeff McGee <jeff.mcgee@intel.com>
On Fri, Oct 28, 2016 at 05:05:44PM -0700, Anusha Srivatsa wrote:
> From: Peter Antoine <peter.antoine@intel.com>
>
> The HuC authentication is done by host2guc call. The HuC RSA keys
> are sent to GuC for authentication.
>
> v2: rebased on top of drm-intel-nightly.
> changed name format and upped version 1.7.
> v3: rebased on top of drm-intel-nightly.
> v4: changed wait_for_automic to wait_for
> v5: rebased.
> v7: rebased.
> v8: rebased.
> v9: rebased. Rename intel_huc_auh() to intel_guc_auth_huc()
> and place the prototype in intel_guc.h,correct the comments.
>
> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
> ---
> drivers/gpu/drm/i915/i915_guc_submission.c | 63 ++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_guc.h | 2 +-
> drivers/gpu/drm/i915/intel_guc_fwif.h | 1 +
> drivers/gpu/drm/i915/intel_guc_loader.c | 2 +
> 4 files changed, 67 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
> index 99dc5d9..936eefc 100644
> --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> @@ -27,6 +27,7 @@
> #include <linux/relay.h>
> #include "i915_drv.h"
> #include "intel_guc.h"
> +#include "intel_huc.h"
>
> /**
> * DOC: GuC-based command submission
> @@ -1713,3 +1714,65 @@ int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val)
>
> return ret;
> }
> +
> +/**
> + * intel_guc_auth_huc() - authenticate ucode
> + * @dev: the drm device
> + *
> + * Triggers a HuC fw authentication request to the GuC via host-2-guc
> + * interface.
> + */
> +void intel_guc_auth_huc(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_guc *guc = &dev_priv->guc;
> + struct intel_huc *huc = &dev_priv->huc;
> + struct i915_vma *vma;
> + int ret;
> + u32 data[2];
> +
> + /* Bypass the case where there is no HuC firmware */
> + if (huc->huc_fw.fetch_status == UC_FIRMWARE_NONE ||
> + huc->huc_fw.load_status == UC_FIRMWARE_NONE)
> + return;
> +
> + if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS) {
> + DRM_ERROR("HuC: GuC fw wasn't loaded. Can't authenticate");
> + return;
> + }
> +
> + if (huc->huc_fw.load_status != UC_FIRMWARE_SUCCESS) {
> + DRM_ERROR("HuC: fw wasn't loaded. Nothing to authenticate");
> + return;
> + }
> +
> + vma = i915_gem_object_ggtt_pin(huc->huc_fw.uc_fw_obj, NULL, 0, 0, 0);
> + if (IS_ERR(vma)) {
> + DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
> + return;
> + }
> +
> +
> + /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
> + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
> +
> + /* Specify auth action and where public signature is. */
> + data[0] = HOST2GUC_ACTION_AUTHENTICATE_HUC;
> + data[1] = i915_ggtt_offset(vma) + huc->huc_fw.rsa_offset;
> +
> + ret = host2guc_action(guc, data, ARRAY_SIZE(data));
> + if (ret) {
> + DRM_ERROR("HuC: GuC did not ack Auth request\n");
> + goto out;
> + }
> +
> + /* Check authentication status, it should be done by now */
> + ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0, 50);
> + if (ret) {
> + DRM_ERROR("HuC: Authentication failed\n");
> + goto out;
> + }
> +
> +out:
> + i915_vma_unpin(vma);
> +}
> diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
> index 4647e41..ffdd5b9 100644
> --- a/drivers/gpu/drm/i915/intel_guc.h
> +++ b/drivers/gpu/drm/i915/intel_guc.h
> @@ -197,5 +197,5 @@ void i915_guc_flush_logs(struct drm_i915_private *dev_priv);
> void i915_guc_register(struct drm_i915_private *dev_priv);
> void i915_guc_unregister(struct drm_i915_private *dev_priv);
> int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val);
> -
> +void intel_guc_auth_huc(struct drm_device *dev);
> #endif
> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
> index c2a7fdd..99a092d 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> @@ -513,6 +513,7 @@ enum host2guc_action {
> HOST2GUC_ACTION_EXIT_S_STATE = 0x502,
> HOST2GUC_ACTION_SLPC_REQUEST = 0x3003,
> HOST2GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
> + HOST2GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
> HOST2GUC_ACTION_LIMIT
> };
>
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index dc79968..11e3bbb 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -531,6 +531,8 @@ int intel_guc_setup(struct drm_device *dev)
> intel_uc_fw_status_repr(guc_fw->fetch_status),
> intel_uc_fw_status_repr(guc_fw->load_status));
>
> + intel_guc_auth_huc(dev);
> +
> if (i915.enable_guc_submission) {
> if (i915.guc_log_level >= 0)
> gen9_enable_guc_interrupts(dev_priv);
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 6/7] drm/i915/huc: Add BXT HuC Loading Support
2016-10-29 0:05 [PATCH 0/7] HuC Loading Patches Anusha Srivatsa
` (4 preceding siblings ...)
2016-10-29 0:05 ` [PATCH 5/7] drm/i915/huc: Support HuC authentication Anusha Srivatsa
@ 2016-10-29 0:05 ` Anusha Srivatsa
2016-10-31 20:29 ` Jeff McGee
2016-10-29 0:05 ` [PATCH 7/7] drm/i915/get_params: Add HuC status to getparams Anusha Srivatsa
2016-10-29 0:46 ` ✓ Fi.CI.BAT: success for HuC Loading Patches Patchwork
7 siblings, 1 reply; 14+ messages in thread
From: Anusha Srivatsa @ 2016-10-29 0:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Peter Antoine
From: Peter Antoine <peter.antoine@intel.com>
This patch adds the HuC Loading for the BXT.
Version 1.7 of the HuC firmware.
v2: rebased.
v3: rebased.
changed file name to match the install package format.
v7: rebased.
v8: rebased.
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
Reviewed-by: David Gordon <david.s.gordon@intel.com>
---
drivers/gpu/drm/i915/intel_huc_loader.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
index dcd9970..0969bdf 100644
--- a/drivers/gpu/drm/i915/intel_huc_loader.c
+++ b/drivers/gpu/drm/i915/intel_huc_loader.c
@@ -43,6 +43,9 @@
#define I915_SKL_HUC_UCODE "i915/skl_huc_ver01_07_1398.bin"
MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
+#define I915_BXT_HUC_UCODE "i915/bxt_huc_ver01_07_1398.bin"
+MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
+
/**
* huc_ucode_xfer() - DMA's the firmware
* @dev_priv: the drm device
@@ -150,6 +153,10 @@ void intel_huc_init(struct drm_device *dev)
fw_path = I915_SKL_HUC_UCODE;
huc_fw->major_ver_wanted = 1;
huc_fw->minor_ver_wanted = 7;
+ } else if (IS_BROXTON(dev_priv)) {
+ fw_path = I915_BXT_HUC_UCODE;
+ huc_fw->major_ver_wanted = 1;
+ huc_fw->minor_ver_wanted = 7;
}
if (fw_path == NULL)
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH 6/7] drm/i915/huc: Add BXT HuC Loading Support
2016-10-29 0:05 ` [PATCH 6/7] drm/i915/huc: Add BXT HuC Loading Support Anusha Srivatsa
@ 2016-10-31 20:29 ` Jeff McGee
0 siblings, 0 replies; 14+ messages in thread
From: Jeff McGee @ 2016-10-31 20:29 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx, Peter Antoine
On Fri, Oct 28, 2016 at 05:05:45PM -0700, Anusha Srivatsa wrote:
> From: Peter Antoine <peter.antoine@intel.com>
>
> This patch adds the HuC Loading for the BXT.
> Version 1.7 of the HuC firmware.
>
> v2: rebased.
> v3: rebased.
> changed file name to match the install package format.
> v7: rebased.
> v8: rebased.
>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> Reviewed-by: David Gordon <david.s.gordon@intel.com>
> ---
> drivers/gpu/drm/i915/intel_huc_loader.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
> index dcd9970..0969bdf 100644
> --- a/drivers/gpu/drm/i915/intel_huc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_huc_loader.c
> @@ -43,6 +43,9 @@
> #define I915_SKL_HUC_UCODE "i915/skl_huc_ver01_07_1398.bin"
> MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
>
> +#define I915_BXT_HUC_UCODE "i915/bxt_huc_ver01_07_1398.bin"
> +MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
> +
This will need updating if the newer firmware version/name macros in
intel_guc_loader.c are adopted.
-Jeff
> /**
> * huc_ucode_xfer() - DMA's the firmware
> * @dev_priv: the drm device
> @@ -150,6 +153,10 @@ void intel_huc_init(struct drm_device *dev)
> fw_path = I915_SKL_HUC_UCODE;
> huc_fw->major_ver_wanted = 1;
> huc_fw->minor_ver_wanted = 7;
> + } else if (IS_BROXTON(dev_priv)) {
> + fw_path = I915_BXT_HUC_UCODE;
> + huc_fw->major_ver_wanted = 1;
> + huc_fw->minor_ver_wanted = 7;
Use version macros here when that part is ready.
-Jeff
> }
>
> if (fw_path == NULL)
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 7/7] drm/i915/get_params: Add HuC status to getparams
2016-10-29 0:05 [PATCH 0/7] HuC Loading Patches Anusha Srivatsa
` (5 preceding siblings ...)
2016-10-29 0:05 ` [PATCH 6/7] drm/i915/huc: Add BXT HuC Loading Support Anusha Srivatsa
@ 2016-10-29 0:05 ` Anusha Srivatsa
2016-10-31 20:31 ` Jeff McGee
2016-10-29 0:46 ` ✓ Fi.CI.BAT: success for HuC Loading Patches Patchwork
7 siblings, 1 reply; 14+ messages in thread
From: Anusha Srivatsa @ 2016-10-29 0:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Peter Antoine
From: Peter Antoine <peter.antoine@intel.com>
This patch will allow for getparams to return the status of the HuC.
As the HuC has to be validated by the GuC this patch uses the validated
status to show when the HuC is loaded and ready for use. You cannot use
the loaded status as with the GuC as the HuC is verified after it is
loaded and is not usable until it is verified.
v2: removed the forewakes as the registers are already force-woken.
(T.Ursulin)
v4: rebased.
v5: rebased.
v6: rebased.
Tested-by: Xiang Haihao <haihao.xiang@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 5 +++++
drivers/gpu/drm/i915/intel_huc.h | 1 +
drivers/gpu/drm/i915/intel_huc_loader.c | 14 ++++++++++++++
include/uapi/drm/i915_drm.h | 1 +
4 files changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 2f36672..038ed8d 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -49,6 +49,8 @@
#include "i915_trace.h"
#include "i915_vgpu.h"
#include "intel_drv.h"
+#include "intel_guc.h"
+#include "intel_huc.h"
static struct drm_driver driver;
@@ -346,6 +348,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
*/
value = 1;
break;
+ case I915_PARAM_HAS_HUC:
+ value = intel_is_huc_valid(dev_priv);
+ break;
default:
DRM_DEBUG("Unknown parameter %d\n", param->param);
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/intel_huc.h b/drivers/gpu/drm/i915/intel_huc.h
index 3ce0299..2e150be 100644
--- a/drivers/gpu/drm/i915/intel_huc.h
+++ b/drivers/gpu/drm/i915/intel_huc.h
@@ -39,4 +39,5 @@ struct intel_huc {
void intel_huc_init(struct drm_device *dev);
void intel_huc_fini(struct drm_device *dev);
int intel_huc_load(struct drm_device *dev);
+extern int intel_is_huc_valid(struct drm_i915_private *dev_priv);
#endif
diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
index 0969bdf..2f5d9d9 100644
--- a/drivers/gpu/drm/i915/intel_huc_loader.c
+++ b/drivers/gpu/drm/i915/intel_huc_loader.c
@@ -265,3 +265,17 @@ void intel_huc_fini(struct drm_device *dev)
huc_fw->fetch_status = UC_FIRMWARE_NONE;
}
+
+/**
+ * intel_is_huc_valid() - Check to see if the HuC is fully loaded.
+ * @dev_priv: drm device to check.
+ *
+ * This function will return true if the guc has been loaded and
+ * has valid firmware. The simplest way of doing this is to check
+ * if the HuC has been validated, if so it must have been loaded.
+ */
+int intel_is_huc_valid(struct drm_i915_private *dev_priv)
+{
+ return ((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) != 0);
+}
+
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 03725fe..aa7667e 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -388,6 +388,7 @@ typedef struct drm_i915_irq_wait {
#define I915_PARAM_HAS_POOLED_EU 38
#define I915_PARAM_MIN_EU_IN_POOL 39
#define I915_PARAM_MMAP_GTT_VERSION 40
+#define I915_PARAM_HAS_HUC 42
typedef struct drm_i915_getparam {
__s32 param;
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH 7/7] drm/i915/get_params: Add HuC status to getparams
2016-10-29 0:05 ` [PATCH 7/7] drm/i915/get_params: Add HuC status to getparams Anusha Srivatsa
@ 2016-10-31 20:31 ` Jeff McGee
0 siblings, 0 replies; 14+ messages in thread
From: Jeff McGee @ 2016-10-31 20:31 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx, Peter Antoine
Patch set header includes links to libva intent to use the interface. Thanks
Reviewed-by: Jeff McGee <jeff.mcgee@intel.com>
On Fri, Oct 28, 2016 at 05:05:46PM -0700, Anusha Srivatsa wrote:
> From: Peter Antoine <peter.antoine@intel.com>
>
> This patch will allow for getparams to return the status of the HuC.
> As the HuC has to be validated by the GuC this patch uses the validated
> status to show when the HuC is loaded and ready for use. You cannot use
> the loaded status as with the GuC as the HuC is verified after it is
> loaded and is not usable until it is verified.
>
> v2: removed the forewakes as the registers are already force-woken.
> (T.Ursulin)
> v4: rebased.
> v5: rebased.
> v6: rebased.
>
> Tested-by: Xiang Haihao <haihao.xiang@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 5 +++++
> drivers/gpu/drm/i915/intel_huc.h | 1 +
> drivers/gpu/drm/i915/intel_huc_loader.c | 14 ++++++++++++++
> include/uapi/drm/i915_drm.h | 1 +
> 4 files changed, 21 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 2f36672..038ed8d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -49,6 +49,8 @@
> #include "i915_trace.h"
> #include "i915_vgpu.h"
> #include "intel_drv.h"
> +#include "intel_guc.h"
> +#include "intel_huc.h"
>
> static struct drm_driver driver;
>
> @@ -346,6 +348,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
> */
> value = 1;
> break;
> + case I915_PARAM_HAS_HUC:
> + value = intel_is_huc_valid(dev_priv);
> + break;
> default:
> DRM_DEBUG("Unknown parameter %d\n", param->param);
> return -EINVAL;
> diff --git a/drivers/gpu/drm/i915/intel_huc.h b/drivers/gpu/drm/i915/intel_huc.h
> index 3ce0299..2e150be 100644
> --- a/drivers/gpu/drm/i915/intel_huc.h
> +++ b/drivers/gpu/drm/i915/intel_huc.h
> @@ -39,4 +39,5 @@ struct intel_huc {
> void intel_huc_init(struct drm_device *dev);
> void intel_huc_fini(struct drm_device *dev);
> int intel_huc_load(struct drm_device *dev);
> +extern int intel_is_huc_valid(struct drm_i915_private *dev_priv);
> #endif
> diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c
> index 0969bdf..2f5d9d9 100644
> --- a/drivers/gpu/drm/i915/intel_huc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_huc_loader.c
> @@ -265,3 +265,17 @@ void intel_huc_fini(struct drm_device *dev)
>
> huc_fw->fetch_status = UC_FIRMWARE_NONE;
> }
> +
> +/**
> + * intel_is_huc_valid() - Check to see if the HuC is fully loaded.
> + * @dev_priv: drm device to check.
> + *
> + * This function will return true if the guc has been loaded and
> + * has valid firmware. The simplest way of doing this is to check
> + * if the HuC has been validated, if so it must have been loaded.
> + */
> +int intel_is_huc_valid(struct drm_i915_private *dev_priv)
> +{
> + return ((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) != 0);
> +}
> +
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 03725fe..aa7667e 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -388,6 +388,7 @@ typedef struct drm_i915_irq_wait {
> #define I915_PARAM_HAS_POOLED_EU 38
> #define I915_PARAM_MIN_EU_IN_POOL 39
> #define I915_PARAM_MMAP_GTT_VERSION 40
> +#define I915_PARAM_HAS_HUC 42
>
> typedef struct drm_i915_getparam {
> __s32 param;
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* ✓ Fi.CI.BAT: success for HuC Loading Patches
2016-10-29 0:05 [PATCH 0/7] HuC Loading Patches Anusha Srivatsa
` (6 preceding siblings ...)
2016-10-29 0:05 ` [PATCH 7/7] drm/i915/get_params: Add HuC status to getparams Anusha Srivatsa
@ 2016-10-29 0:46 ` Patchwork
7 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2016-10-29 0:46 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
== Series Details ==
Series: HuC Loading Patches
URL : https://patchwork.freedesktop.org/series/14555/
State : success
== Summary ==
Series 14555v1 HuC Loading Patches
https://patchwork.freedesktop.org/api/1.0/series/14555/revisions/1/mbox/
Test drv_module_reload_basic:
dmesg-warn -> PASS (fi-hsw-4770)
Test kms_force_connector_basic:
Subgroup force-edid:
dmesg-warn -> PASS (fi-snb-2520m)
Test kms_pipe_crc_basic:
Subgroup bad-pipe:
dmesg-warn -> PASS (fi-ilk-650)
fi-bdw-5557u total:239 pass:224 dwarn:0 dfail:0 fail:0 skip:15
fi-bsw-n3050 total:239 pass:199 dwarn:0 dfail:0 fail:0 skip:40
fi-bxt-t5700 total:239 pass:211 dwarn:0 dfail:0 fail:0 skip:28
fi-byt-j1900 total:239 pass:211 dwarn:0 dfail:0 fail:0 skip:28
fi-byt-n2820 total:239 pass:207 dwarn:0 dfail:0 fail:0 skip:32
fi-hsw-4770 total:239 pass:219 dwarn:0 dfail:0 fail:0 skip:20
fi-hsw-4770r total:239 pass:218 dwarn:0 dfail:0 fail:0 skip:21
fi-ilk-650 total:239 pass:185 dwarn:0 dfail:0 fail:0 skip:54
fi-ivb-3520m total:239 pass:216 dwarn:0 dfail:0 fail:0 skip:23
fi-ivb-3770 total:239 pass:216 dwarn:0 dfail:0 fail:0 skip:23
fi-kbl-7200u total:239 pass:217 dwarn:0 dfail:0 fail:0 skip:22
fi-skl-6260u total:239 pass:225 dwarn:0 dfail:0 fail:0 skip:14
fi-skl-6700hq total:239 pass:218 dwarn:0 dfail:0 fail:0 skip:21
fi-skl-6700k total:239 pass:217 dwarn:1 dfail:0 fail:0 skip:21
fi-skl-6770hq total:239 pass:225 dwarn:0 dfail:0 fail:0 skip:14
fi-snb-2520m total:239 pass:206 dwarn:0 dfail:0 fail:0 skip:33
fi-snb-2600 total:239 pass:205 dwarn:0 dfail:0 fail:0 skip:34
f3968d51ade8c02e8868c2608ea4adb5a4afe301 drm-intel-nightly: 2016y-10m-28d-19h-57m-33s UTC integration manifest
205ca35 drm/i915/get_params: Add HuC status to getparams
0e6d958 drm/i915/huc: Add BXT HuC Loading Support
f8962e9 drm/i915/huc: Support HuC authentication
0be76d3 drm/i915/huc: Add debugfs for HuC loading status check
72ce1c1 drm/i915/huc: Add HuC fw loading support
bcbb87a drm/i915/huc: Unified css_header struct for GuC and HuC
7fd6b4e drm/i915/guc: Make the GuC fw loading helper functions general
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_2853/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread