MIPS74K dma coherence issue

MIPS74K dma coherence issue

[Sven Schnelle]

Hi List,

i was debugging a nasty problem where DMA data was incorrect
after dma_unmap_single(). Reason was that cache wasn't flushed
after DMA. Attached patch fixes this.

Regards
Sven

[PATCH] MIPS: MIPS74K needs post dma flush

[Sven Schnelle]

The manual states "A 74K processor contains no direct hardware
support for managing coherency with respect to its caches, so
it must be handled via the system design or software"

Signed-off-by: Sven Schnelle <svens@stackframe.org>
---
 arch/mips/mm/dma-default.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index 46d5696..575b7b8 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -73,7 +73,8 @@ static inline int cpu_needs_post_dma_flush(struct device *dev)
 	return !plat_device_is_coherent(dev) &&
 	       (boot_cpu_type() == CPU_R10000 ||
 		boot_cpu_type() == CPU_R12000 ||
-		boot_cpu_type() == CPU_BMIPS5000);
+		boot_cpu_type() == CPU_BMIPS5000 ||
+		boot_cpu_type() == CPU_74K);
 }
 
 static gfp_t massage_gfp_flags(const struct device *dev, gfp_t gfp)
-- 
2.10.2

Re: MIPS: MIPS74K needs post dma flush

[Leonid Yegoshin]

74K does NOT have an aggressive speculation, never for D-Cache, never 
for I-cache. D-Cache doesn't an advance speculation load at all, I-cache 
never does a wrong speculation.

So, post-DMA flush is not needed in any form.

- Leonid.

Re: MIPS: MIPS74K needs post dma flush

[Leonid Yegoshin]

74K does NOT have an aggressive speculation, never for D-Cache, never 
for I-cache. D-Cache doesn't an advance speculation load at all, I-cache 
never does a wrong speculation.

So, post-DMA flush is not needed in any form.

- Leonid.