Re: task isolation discussion at Linux Plumbers

["Paul E. McKenney" <paulmck@linux.vnet.ibm.com>]

On Wed, Nov 09, 2016 at 06:57:43PM +0000, Will Deacon wrote:
> Hi Paul,
> 
> Just a couple of comments, but they be more suited to Andy.
> 
> On Wed, Nov 09, 2016 at 09:38:08AM -0800, Paul E. McKenney wrote:
> > @@ -355,10 +373,33 @@ static bool rcu_dynticks_in_eqs_since(struct rcu_dynticks *rdtp, int snap)
> >  static void rcu_dynticks_momentary_idle(void)
> >  {
> >  	struct rcu_dynticks *rdtp = this_cpu_ptr(&rcu_dynticks);
> > -	int special = atomic_add_return(2, &rdtp->dynticks);
> > +	int special = atomic_add_return(2 * RCU_DYNTICK_CTRL_CTR,
> > +					&rdtp->dynticks);
> >  
> >  	/* It is illegal to call this from idle state. */
> > -	WARN_ON_ONCE(!(special & 0x1));
> > +	WARN_ON_ONCE(!(special & RCU_DYNTICK_CTRL_CTR));
> > +}
> > +
> > +/*
> > + * Set the special (bottom) bit of the specified CPU so that it
> > + * will take special action (such as flushing its TLB) on the
> > + * next exit from an extended quiescent state.  Returns true if
> > + * the bit was successfully set, or false if the CPU was not in
> > + * an extended quiescent state.
> > + */
> 
> Given that TLB maintenance on arm is handled in hardware (no need for IPI),
> I'd like to avoid this work if at all possible. However, without seeing the
> call site I can't tell if it's optional.

For this, I must defer to Andy.

> > +bool rcu_eqs_special_set(int cpu)
> > +{
> > +	int old;
> > +	int new;
> > +	struct rcu_dynticks *rdtp = &per_cpu(rcu_dynticks, cpu);
> > +
> > +	do {
> > +		old = atomic_read(&rdtp->dynticks);
> > +		if (old & RCU_DYNTICK_CTRL_CTR)
> > +			return false;
> > +		new = old | RCU_DYNTICK_CTRL_MASK;
> > +	} while (atomic_cmpxchg(&rdtp->dynticks, old, new) != old);
> > +	return true;
> >  }
> 
> Can this be a cmpxchg_relaxed? What is it attempting to order?

It is attmepting to order my paranoia.  ;-)

If Andy shows me that less ordering is possible, I can weaken it.

							Thanx, Paul