[PATCH 0/5] Fixes for Exynos5433 TM2 board

[PATCH 0/5] Fixes for Exynos5433 TM2 board

[Marek Szyprowski]

Hi!

This is a collection of various fixes (mainly related to clocks
configuration) for Exynos 5433 based TM2 board dts. I'm really sorry
that I missed those issues in the initial board submission, but
most of those issue were detected while testing improved clocks driver.

Best regards
Marek Szyprowski
Samsung R&D Institute Poland


Patch summary:

Marek Szyprowski (4):
  arm64: dts: exynos: Fix FSYS CMU parent clocks in Exynos 5433 SoC
  arm64: dts: exynos: Add missing parent clocks to audio block in Exynos
    5433 SoC
  arm64: dts: exynos: Move FSYS CMU configuration from Exynos5433 dtsi
    to TM2 dts
  arm64: dts: exynos: TM2 - remove unused UART3 and set clocks directly
    on CMU

Sylwester Nawrocki (1):
  arm64: dts: exynos: Assign parent clock of the clkout clock for TM2
    board

 arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 21 +++++++++++++++--
 arch/arm64/boot/dts/exynos/exynos5433.dtsi    | 34 ++++-----------------------
 2 files changed, 23 insertions(+), 32 deletions(-)

-- 
1.9.1

[PATCH 1/5] arm64: dts: exynos: Fix FSYS CMU parent clocks in Exynos 5433 SoC

[Marek Szyprowski]

This patch corrects FSYS CMU parent clocks specified in clock controller
node to let improved Exynos 5433 clocks driver to control proper clocks
on FSYS<->TOP CMU boundary.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 arch/arm64/boot/dts/exynos/exynos5433.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 1188630..6564875 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -312,7 +312,7 @@
 
 			clock-names = "oscclk",
 				"sclk_ufs_mphy",
-				"div_aclk_fsys_200",
+				"aclk_fsys_200",
 				"sclk_pcie_100_fsys",
 				"sclk_ufsunipro_fsys",
 				"sclk_mmc2_fsys",
@@ -322,7 +322,7 @@
 				"sclk_usbdrd30_fsys";
 			clocks = <&xxti>,
 				<&cmu_cpif CLK_SCLK_UFS_MPHY>,
-				<&cmu_top CLK_DIV_ACLK_FSYS_200>,
+				<&cmu_top CLK_ACLK_FSYS_200>,
 				<&cmu_top CLK_SCLK_PCIE_100_FSYS>,
 				<&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
 				<&cmu_top CLK_SCLK_MMC2_FSYS>,
-- 
1.9.1

[PATCH 2/5] arm64: dts: exynos: Add missing parent clocks to audio block in Exynos 5433 SoC

[Marek Szyprowski]

Audio pll and oscilator clocks are proper parent clocks for AUD CMU.
They are not visible as such on first glance on Exynos 5433 SoC docs,
but they are needed for this CMU to operate properly.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 arch/arm64/boot/dts/exynos/exynos5433.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 6564875..a80eb4c 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -374,6 +374,8 @@
 			compatible = "samsung,exynos5433-cmu-aud";
 			reg = <0x114c0000 0x1000>;
 			#clock-cells = <1>;
+			clock-names = "oscclk", "fout_aud_pll";
+			clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>;
 		};
 
 		cmu_bus0: clock-controller@13600000 {
-- 
1.9.1

[PATCH 3/5] arm64: dts: exynos: Move FSYS CMU configuration from Exynos5433 dtsi to TM2 dts

[Marek Szyprowski]

Move initial FSYS CMU (related to USB 3.0 devices) clocks configuration
from generic exynos5433.dtsi file to exynos5433-tm2.dts, as this is
a board specific item.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 13 +++++++++++++
 arch/arm64/boot/dts/exynos/exynos5433.dtsi    | 28 ---------------------------
 2 files changed, 13 insertions(+), 28 deletions(-)

diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
index 9ea3f32..b7b2482 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
@@ -892,6 +892,19 @@
 	status = "okay";
 };
 
+&cmu_fsys {
+	assigned-clocks = <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>,
+		<&cmu_top CLK_MOUT_SCLK_USBDRD30>,
+		<&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>,
+		<&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>,
+		<&cmu_top CLK_DIV_SCLK_USBDRD30>;
+	assigned-clock-parents = <&cmu_top CLK_SCLK_USBDRD30_FSYS>,
+		<&cmu_top CLK_MOUT_BUS_PLL_USER>,
+		<&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>,
+		<&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>;
+	assigned-clock-rates = <0>, <0>, <0>, <0>, <66700000>;
+};
+
 &spi_1 {
 	cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>;
 	status = "okay";
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index a80eb4c..ab29352 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -1134,14 +1134,6 @@
 			clocks = <&cmu_fsys CLK_ACLK_USBDRD30>,
 				<&cmu_fsys CLK_SCLK_USBDRD30>;
 			clock-names = "usbdrd30", "usbdrd30_susp_clk";
-			assigned-clocks =
-				<&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>,
-				<&cmu_top CLK_MOUT_SCLK_USBDRD30>,
-				<&cmu_top CLK_DIV_SCLK_USBDRD30>;
-			assigned-clock-parents =
-				<&cmu_top CLK_SCLK_USBDRD30_FSYS>,
-				<&cmu_top CLK_MOUT_BUS_PLL_USER>;
-			assigned-clock-rates = <0>, <0>, <66700000>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges;
@@ -1165,12 +1157,6 @@
 				<&cmu_fsys CLK_SCLK_USBDRD30>;
 			clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
 					"itp";
-			assigned-clocks =
-				<&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>,
-				<&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>;
-			assigned-clock-parents =
-				<&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>,
-				<&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>;
 			#phy-cells = <1>;
 			samsung,pmu-syscon = <&pmu_system_controller>;
 			status = "disabled";
@@ -1185,12 +1171,6 @@
 				<&cmu_fsys CLK_SCLK_USBHOST30>;
 			clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
 					"itp";
-			assigned-clocks =
-				<&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>,
-				<&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>;
-			assigned-clock-parents =
-				<&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>,
-				<&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>;
 			#phy-cells = <1>;
 			samsung,pmu-syscon = <&pmu_system_controller>;
 			status = "disabled";
@@ -1201,14 +1181,6 @@
 			clocks = <&cmu_fsys CLK_ACLK_USBHOST30>,
 				<&cmu_fsys CLK_SCLK_USBHOST30>;
 			clock-names = "usbdrd30", "usbdrd30_susp_clk";
-			assigned-clocks =
-				<&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>,
-				<&cmu_top CLK_MOUT_SCLK_USBHOST30>,
-				<&cmu_top CLK_DIV_SCLK_USBHOST30>;
-			assigned-clock-parents =
-				<&cmu_top CLK_SCLK_USBHOST30_FSYS>,
-				<&cmu_top CLK_MOUT_BUS_PLL_USER>;
-			assigned-clock-rates = <0>, <0>, <66700000>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges;
-- 
1.9.1

[PATCH 4/5] arm64: dts: exynos: Assign parent clock of the clkout clock for TM2 board

[Marek Szyprowski]

From: Sylwester Nawrocki <s.nawrocki@samsung.com>

Without this patch the clkout clock is orphaned and sound doesn't
work properly.

Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
index b7b2482..506f8ab 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
@@ -882,6 +882,11 @@
 	};
 };
 
+&pmu_system_controller {
+	assigned-clocks = <&pmu_system_controller 0>;
+	assigned-clock-parents = <&xxti>;
+};
+
 &serial_1 {
 	status = "okay";
 };
-- 
1.9.1

[PATCH 5/5] arm64: dts: exynos: TM2 - remove unused UART3 and set clocks directly on CMU

[Marek Szyprowski]

UART3 device is not really needed for enabling audio block on TM2.
Enabling it made it working by enabling some common parent clocks,
what is now handled by improved exynos5433 clocks driver. Thus the UART3
device node can be safetly disabled. The assigned-clocks entries are
however still needed, so move them under the respective CMU node.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
index 506f8ab..5ab1028 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
@@ -891,10 +891,9 @@
 	status = "okay";
 };
 
-&serial_3 {
+&cmu_aud {
 	assigned-clocks = <&cmu_aud CLK_MOUT_AUD_PLL_USER>;
 	assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>;
-	status = "okay";
 };
 
 &cmu_fsys {
-- 
1.9.1

Re: [PATCH 2/5] arm64: dts: exynos: Add missing parent clocks to audio block in Exynos 5433 SoC

[Sylwester Nawrocki]

On 11/16/2016 02:06 PM, Marek Szyprowski wrote:
> Audio pll and oscilator clocks are proper parent clocks for AUD CMU.

s/pll/PLL, s/oscilator/oscillator

> They are not visible as such on first glance on Exynos 5433 SoC docs,
> but they are needed for this CMU to operate properly.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

Re: [PATCH 0/5] Fixes for Exynos5433 TM2 board

[Sylwester Nawrocki]

On 11/16/2016 02:06 PM, Marek Szyprowski wrote:
> This is a collection of various fixes (mainly related to clocks
> configuration) for Exynos 5433 based TM2 board dts. I'm really sorry
> that I missed those issues in the initial board submission, but
> most of those issue were detected while testing improved clocks driver.

For the whole series:
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

Re: [PATCH 1/5] arm64: dts: exynos: Fix FSYS CMU parent clocks in Exynos 5433 SoC

[Chanwoo Choi]

Hi Marek,

2016-11-16 22:06 GMT+09:00 Marek Szyprowski <m.szyprowski@samsung.com>:
> This patch corrects FSYS CMU parent clocks specified in clock controller
> node to let improved Exynos 5433 clocks driver to control proper clocks
> on FSYS<->TOP CMU boundary.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  arch/arm64/boot/dts/exynos/exynos5433.dtsi | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> index 1188630..6564875 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> @@ -312,7 +312,7 @@
>
>                         clock-names = "oscclk",
>                                 "sclk_ufs_mphy",
> -                               "div_aclk_fsys_200",
> +                               "aclk_fsys_200",

FSYS cmu doesn't use the "aclk_fsys_200" clock as parent clock.

When I check the clk-exynos5433.c driver, CLK_MOUT_ACLK_FSYS_200_USER
mux in the FSYS cmu
uses the "div_aclk_fsys_200" clock as parent clock instead of "aclk_fsys_200".

>                                 "sclk_pcie_100_fsys",
>                                 "sclk_ufsunipro_fsys",
>                                 "sclk_mmc2_fsys",
> @@ -322,7 +322,7 @@
>                                 "sclk_usbdrd30_fsys";
>                         clocks = <&xxti>,
>                                 <&cmu_cpif CLK_SCLK_UFS_MPHY>,
> -                               <&cmu_top CLK_DIV_ACLK_FSYS_200>,
> +                               <&cmu_top CLK_ACLK_FSYS_200>,
>                                 <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
>                                 <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
>                                 <&cmu_top CLK_SCLK_MMC2_FSYS>,
> --
> 1.9.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Best Regards,
Chanwoo Choi

Re: [PATCH 2/5] arm64: dts: exynos: Add missing parent clocks to audio block in Exynos 5433 SoC

[Chanwoo Choi]

Hi Marek,

2016-11-16 22:06 GMT+09:00 Marek Szyprowski <m.szyprowski@samsung.com>:
> Audio pll and oscilator clocks are proper parent clocks for AUD CMU.
> They are not visible as such on first glance on Exynos 5433 SoC docs,
> but they are needed for this CMU to operate properly.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  arch/arm64/boot/dts/exynos/exynos5433.dtsi | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> index 6564875..a80eb4c 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> @@ -374,6 +374,8 @@
>                         compatible = "samsung,exynos5433-cmu-aud";
>                         reg = <0x114c0000 0x1000>;
>                         #clock-cells = <1>;
> +                       clock-names = "oscclk", "fout_aud_pll";
> +                       clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>;
>                 };
>
>                 cmu_bus0: clock-controller@13600000 {

Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>

Also, you should update the binding documentation of exynos5433's clock[1].
[1] Documentation/devicetree/bindings/clock/exynos5433-clock.txt

Best Regards,
Chanwoo Choi

Re: [PATCH 3/5] arm64: dts: exynos: Move FSYS CMU configuration from Exynos5433 dtsi to TM2 dts

[Chanwoo Choi]

Hi Marek,

2016-11-16 22:06 GMT+09:00 Marek Szyprowski <m.szyprowski@samsung.com>:
> Move initial FSYS CMU (related to USB 3.0 devices) clocks configuration
> from generic exynos5433.dtsi file to exynos5433-tm2.dts, as this is
> a board specific item.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 13 +++++++++++++
>  arch/arm64/boot/dts/exynos/exynos5433.dtsi    | 28 ---------------------------
>  2 files changed, 13 insertions(+), 28 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
> index 9ea3f32..b7b2482 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
> @@ -892,6 +892,19 @@
>         status = "okay";
>  };
>
> +&cmu_fsys {
> +       assigned-clocks = <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>,
> +               <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
> +               <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>,
> +               <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>,
> +               <&cmu_top CLK_DIV_SCLK_USBDRD30>;
> +       assigned-clock-parents = <&cmu_top CLK_SCLK_USBDRD30_FSYS>,
> +               <&cmu_top CLK_MOUT_BUS_PLL_USER>,
> +               <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>,
> +               <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>;
> +       assigned-clock-rates = <0>, <0>, <0>, <0>, <66700000>;
> +};
> +
>  &spi_1 {
>         cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>;
>         status = "okay";
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> index a80eb4c..ab29352 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> @@ -1134,14 +1134,6 @@
>                         clocks = <&cmu_fsys CLK_ACLK_USBDRD30>,
>                                 <&cmu_fsys CLK_SCLK_USBDRD30>;
>                         clock-names = "usbdrd30", "usbdrd30_susp_clk";
> -                       assigned-clocks =
> -                               <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>,
> -                               <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
> -                               <&cmu_top CLK_DIV_SCLK_USBDRD30>;
> -                       assigned-clock-parents =
> -                               <&cmu_top CLK_SCLK_USBDRD30_FSYS>,
> -                               <&cmu_top CLK_MOUT_BUS_PLL_USER>;
> -                       assigned-clock-rates = <0>, <0>, <66700000>;
>                         #address-cells = <1>;
>                         #size-cells = <1>;
>                         ranges;
> @@ -1165,12 +1157,6 @@
>                                 <&cmu_fsys CLK_SCLK_USBDRD30>;
>                         clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
>                                         "itp";
> -                       assigned-clocks =
> -                               <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>,
> -                               <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>;
> -                       assigned-clock-parents =
> -                               <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>,
> -                               <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>;
>                         #phy-cells = <1>;
>                         samsung,pmu-syscon = <&pmu_system_controller>;
>                         status = "disabled";
> @@ -1185,12 +1171,6 @@
>                                 <&cmu_fsys CLK_SCLK_USBHOST30>;
>                         clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
>                                         "itp";
> -                       assigned-clocks =
> -                               <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>,
> -                               <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>;
> -                       assigned-clock-parents =
> -                               <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>,
> -                               <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>;
>                         #phy-cells = <1>;
>                         samsung,pmu-syscon = <&pmu_system_controller>;
>                         status = "disabled";
> @@ -1201,14 +1181,6 @@
>                         clocks = <&cmu_fsys CLK_ACLK_USBHOST30>,
>                                 <&cmu_fsys CLK_SCLK_USBHOST30>;
>                         clock-names = "usbdrd30", "usbdrd30_susp_clk";
> -                       assigned-clocks =
> -                               <&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>,
> -                               <&cmu_top CLK_MOUT_SCLK_USBHOST30>,
> -                               <&cmu_top CLK_DIV_SCLK_USBHOST30>;
> -                       assigned-clock-parents =
> -                               <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
> -                               <&cmu_top CLK_MOUT_BUS_PLL_USER>;
> -                       assigned-clock-rates = <0>, <0>, <66700000>;
>                         #address-cells = <1>;
>                         #size-cells = <1>;
>                         ranges;


Looks good to me.

Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>

-- 
Best Regards,
Chanwoo Choi

Re: [PATCH 5/5] arm64: dts: exynos: TM2 - remove unused UART3 and set clocks directly on CMU

[Chanwoo Choi]

Hi Marek,

2016-11-16 22:06 GMT+09:00 Marek Szyprowski <m.szyprowski@samsung.com>:
> UART3 device is not really needed for enabling audio block on TM2.
> Enabling it made it working by enabling some common parent clocks,
> what is now handled by improved exynos5433 clocks driver. Thus the UART3
> device node can be safetly disabled. The assigned-clocks entries are
> however still needed, so move them under the respective CMU node.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
> index 506f8ab..5ab1028 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
> @@ -891,10 +891,9 @@
>         status = "okay";
>  };
>
> -&serial_3 {
> +&cmu_aud {
>         assigned-clocks = <&cmu_aud CLK_MOUT_AUD_PLL_USER>;
>         assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>;
> -       status = "okay";
>  };


Looks good to me.

The UART3 of TM2 was used for bluetooth device. CLK_MOUT_AUD_PLL_USER
clock is the parent clock of CLK_SCLK_AUD_UART of uart3 for bluetooth.
So, in the legacy, we assigned the parent clock in the uart3
Device-tree node.

Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>

Best Regards,
Chanwoo Choi

Re: [PATCH 3/5] arm64: dts: exynos: Move FSYS CMU configuration from Exynos5433 dtsi to TM2 dts

[Krzysztof Kozlowski]

On Wed, Nov 16, 2016 at 02:06:53PM +0100, Marek Szyprowski wrote:
> Move initial FSYS CMU (related to USB 3.0 devices) clocks configuration
> from generic exynos5433.dtsi file to exynos5433-tm2.dts, as this is
> a board specific item.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 13 +++++++++++++
>  arch/arm64/boot/dts/exynos/exynos5433.dtsi    | 28 ---------------------------
>  2 files changed, 13 insertions(+), 28 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
> index 9ea3f32..b7b2482 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
> @@ -892,6 +892,19 @@
>  	status = "okay";
>  };
>  
> +&cmu_fsys {

If there would be a resubmit, please put it in alphabetical order.

> +	assigned-clocks = <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>,
> +		<&cmu_top CLK_MOUT_SCLK_USBDRD30>,
> +		<&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>,
> +		<&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>,
> +		<&cmu_top CLK_DIV_SCLK_USBDRD30>;
> +	assigned-clock-parents = <&cmu_top CLK_SCLK_USBDRD30_FSYS>,
> +		<&cmu_top CLK_MOUT_BUS_PLL_USER>,
> +		<&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>,
> +		<&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>;
> +	assigned-clock-rates = <0>, <0>, <0>, <0>, <66700000>;

I see this is not an equivalent change - some clocks are not assigned
now. I had impression from the commit msg that it will be just a move so
no practical impact. Won't there be a problem with missing clock
assigns?

BR,
Krzysztof

> +};
> +
>  &spi_1 {
>  	cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>;
>  	status = "okay";
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> index a80eb4c..ab29352 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> @@ -1134,14 +1134,6 @@
>  			clocks = <&cmu_fsys CLK_ACLK_USBDRD30>,
>  				<&cmu_fsys CLK_SCLK_USBDRD30>;
>  			clock-names = "usbdrd30", "usbdrd30_susp_clk";
> -			assigned-clocks =
> -				<&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>,
> -				<&cmu_top CLK_MOUT_SCLK_USBDRD30>,
> -				<&cmu_top CLK_DIV_SCLK_USBDRD30>;
> -			assigned-clock-parents =
> -				<&cmu_top CLK_SCLK_USBDRD30_FSYS>,
> -				<&cmu_top CLK_MOUT_BUS_PLL_USER>;
> -			assigned-clock-rates = <0>, <0>, <66700000>;
>  			#address-cells = <1>;
>  			#size-cells = <1>;
>  			ranges;
> @@ -1165,12 +1157,6 @@
>  				<&cmu_fsys CLK_SCLK_USBDRD30>;
>  			clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
>  					"itp";
> -			assigned-clocks =
> -				<&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>,
> -				<&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>;
> -			assigned-clock-parents =
> -				<&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>,
> -				<&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>;
>  			#phy-cells = <1>;
>  			samsung,pmu-syscon = <&pmu_system_controller>;
>  			status = "disabled";
> @@ -1185,12 +1171,6 @@
>  				<&cmu_fsys CLK_SCLK_USBHOST30>;
>  			clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
>  					"itp";
> -			assigned-clocks =
> -				<&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>,
> -				<&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>;
> -			assigned-clock-parents =
> -				<&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>,
> -				<&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>;
>  			#phy-cells = <1>;
>  			samsung,pmu-syscon = <&pmu_system_controller>;
>  			status = "disabled";
> @@ -1201,14 +1181,6 @@
>  			clocks = <&cmu_fsys CLK_ACLK_USBHOST30>,
>  				<&cmu_fsys CLK_SCLK_USBHOST30>;
>  			clock-names = "usbdrd30", "usbdrd30_susp_clk";
> -			assigned-clocks =
> -				<&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>,
> -				<&cmu_top CLK_MOUT_SCLK_USBHOST30>,
> -				<&cmu_top CLK_DIV_SCLK_USBHOST30>;
> -			assigned-clock-parents =
> -				<&cmu_top CLK_SCLK_USBHOST30_FSYS>,
> -				<&cmu_top CLK_MOUT_BUS_PLL_USER>;
> -			assigned-clock-rates = <0>, <0>, <66700000>;
>  			#address-cells = <1>;
>  			#size-cells = <1>;
>  			ranges;
> -- 
> 1.9.1
> 

Re: [PATCH 3/5] arm64: dts: exynos: Move FSYS CMU configuration from Exynos5433 dtsi to TM2 dts

[Marek Szyprowski]

Hi Krzysztof,


On 2016-11-16 17:54, Krzysztof Kozlowski wrote:
> On Wed, Nov 16, 2016 at 02:06:53PM +0100, Marek Szyprowski wrote:
>> Move initial FSYS CMU (related to USB 3.0 devices) clocks configuration
>> from generic exynos5433.dtsi file to exynos5433-tm2.dts, as this is
>> a board specific item.
>>
>> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
>> ---
>>   arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 13 +++++++++++++
>>   arch/arm64/boot/dts/exynos/exynos5433.dtsi    | 28 ---------------------------
>>   2 files changed, 13 insertions(+), 28 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
>> index 9ea3f32..b7b2482 100644
>> --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
>> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
>> @@ -892,6 +892,19 @@
>>   	status = "okay";
>>   };
>>   
>> +&cmu_fsys {
> If there would be a resubmit, please put it in alphabetical order.
>
>> +	assigned-clocks = <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>,
>> +		<&cmu_top CLK_MOUT_SCLK_USBDRD30>,
>> +		<&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>,
>> +		<&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>,
>> +		<&cmu_top CLK_DIV_SCLK_USBDRD30>;
>> +	assigned-clock-parents = <&cmu_top CLK_SCLK_USBDRD30_FSYS>,
>> +		<&cmu_top CLK_MOUT_BUS_PLL_USER>,
>> +		<&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>,
>> +		<&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>;
>> +	assigned-clock-rates = <0>, <0>, <0>, <0>, <66700000>;
> I see this is not an equivalent change - some clocks are not assigned
> now. I had impression from the commit msg that it will be just a move so
> no practical impact. Won't there be a problem with missing clock
> assigns?

I've checked those clocks 2 times and I must have been blind. The clock
identifiers are so long that I missed that some PHYCLK related clocks are
for DRD and some for HOST USB. I will add missing assigns in the next 
version.

Best regards
-- 
Marek Szyprowski, PhD
Samsung R&D Institute Poland

Re: [PATCH 5/5] arm64: dts: exynos: TM2 - remove unused UART3 and set clocks directly on CMU

[Marek Szyprowski]

Hi Chanwoo,


On 2016-11-16 17:51, Chanwoo Choi wrote:
> Hi Marek,
>
> 2016-11-16 22:06 GMT+09:00 Marek Szyprowski <m.szyprowski@samsung.com>:
>> UART3 device is not really needed for enabling audio block on TM2.
>> Enabling it made it working by enabling some common parent clocks,
>> what is now handled by improved exynos5433 clocks driver. Thus the UART3
>> device node can be safetly disabled. The assigned-clocks entries are
>> however still needed, so move them under the respective CMU node.
>>
>> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
>> ---
>>   arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 3 +--
>>   1 file changed, 1 insertion(+), 2 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
>> index 506f8ab..5ab1028 100644
>> --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
>> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
>> @@ -891,10 +891,9 @@
>>          status = "okay";
>>   };
>>
>> -&serial_3 {
>> +&cmu_aud {
>>          assigned-clocks = <&cmu_aud CLK_MOUT_AUD_PLL_USER>;
>>          assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>;
>> -       status = "okay";
>>   };
>
> Looks good to me.
>
> The UART3 of TM2 was used for bluetooth device. CLK_MOUT_AUD_PLL_USER
> clock is the parent clock of CLK_SCLK_AUD_UART of uart3 for bluetooth.
> So, in the legacy, we assigned the parent clock in the uart3
> Device-tree node.
>
> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>

Selecting AUD_PLL as a parent affects the whole audio block and it is needed
to get it working, so it is not only related to bluetooth device.

Best regards
-- 
Marek Szyprowski, PhD
Samsung R&D Institute Poland

Re: [PATCH 1/5] arm64: dts: exynos: Fix FSYS CMU parent clocks in Exynos 5433 SoC

[Marek Szyprowski]

Hi Chanwoo,


On 2016-11-16 17:31, Chanwoo Choi wrote:
> Hi Marek,
>
> 2016-11-16 22:06 GMT+09:00 Marek Szyprowski <m.szyprowski@samsung.com>:
>> This patch corrects FSYS CMU parent clocks specified in clock controller
>> node to let improved Exynos 5433 clocks driver to control proper clocks
>> on FSYS<->TOP CMU boundary.
>>
>> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
>> ---
>>   arch/arm64/boot/dts/exynos/exynos5433.dtsi | 4 ++--
>>   1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
>> index 1188630..6564875 100644
>> --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
>> +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
>> @@ -312,7 +312,7 @@
>>
>>                          clock-names = "oscclk",
>>                                  "sclk_ufs_mphy",
>> -                               "div_aclk_fsys_200",
>> +                               "aclk_fsys_200",
> FSYS cmu doesn't use the "aclk_fsys_200" clock as parent clock.
>
> When I check the clk-exynos5433.c driver, CLK_MOUT_ACLK_FSYS_200_USER
> mux in the FSYS cmu
> uses the "div_aclk_fsys_200" clock as parent clock instead of "aclk_fsys_200".

Then this is a bug in clk-exynos5433.c driver. aclk_fsys_200 is the correct
parent for CLK_MOUT_ACLK_FSYS_200_USER mux. See page 582 and 814
(CLK_MUX_SEL_FSYS0 register description) of Exynos 5433 User Manual (rev 
0.10).
Also my experiments revealed that aclk_fsys_200 gate register
(CLK_ACLK_FSYS_200 clk) has to be enabled to do any operation on devices in
FSYS block, so this is definitely the clock that is a parent of the whole
block.

I will prepare a fix for clk-exynos5433.c driver and dt bindings docs too.

>
>>                                  "sclk_pcie_100_fsys",
>>                                  "sclk_ufsunipro_fsys",
>>                                  "sclk_mmc2_fsys",
>> @@ -322,7 +322,7 @@
>>                                  "sclk_usbdrd30_fsys";
>>                          clocks = <&xxti>,
>>                                  <&cmu_cpif CLK_SCLK_UFS_MPHY>,
>> -                               <&cmu_top CLK_DIV_ACLK_FSYS_200>,
>> +                               <&cmu_top CLK_ACLK_FSYS_200>,
>>                                  <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
>>                                  <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
>>                                  <&cmu_top CLK_SCLK_MMC2_FSYS>,
>> --
>> 1.9.1
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Best Regards,
> Chanwoo Choi
>
>
>

Best regards
-- 
Marek Szyprowski, PhD
Samsung R&D Institute Poland