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From: will.deacon@arm.com (Will Deacon)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 5/9] arm64: cpufeature: Define helpers for sys_reg id
Date: Wed, 30 Nov 2016 11:04:56 +0000	[thread overview]
Message-ID: <20161130110455.GD2724@arm.com> (raw)
In-Reply-To: <1479994809-9081-6-git-send-email-suzuki.poulose@arm.com>

On Thu, Nov 24, 2016 at 01:40:05PM +0000, Suzuki K Poulose wrote:
> Define helper macros to extract op0, op1, CRn, CRm & op2
> for a given sys_reg id.
> 
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Will Deacon <will.deacon@arm.com>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
>  arch/arm64/include/asm/sysreg.h | 21 ++++++++++++++++++++-
>  1 file changed, 20 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 6c80b36..488b939 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -34,8 +34,27 @@
>   *	[11-8]  : CRm
>   *	[7-5]   : Op2
>   */
> +#define Op0_shift	19
> +#define Op0_mask	0x3
> +#define Op1_shift	16
> +#define Op1_mask	0x7
> +#define CRn_shift	12
> +#define CRn_mask	0xf
> +#define CRm_shift	8
> +#define CRm_mask	0xf
> +#define Op2_shift	5
> +#define Op2_mask	0x7
> +
>  #define sys_reg(op0, op1, crn, crm, op2) \
> -	((((op0)&3)<<19)|((op1)<<16)|((crn)<<12)|((crm)<<8)|((op2)<<5))
> +	((((op0) & Op0_mask) << Op0_shift) | \
> +	 ((op1) << Op1_shift) | ((crn) << CRn_shift) | \
> +	 ((crm) << CRm_shift) | ((op2) << Op2_shift))

You're preserving the current behaviour here, but why do we care so much
about masking op0 but then not bother masking any of the other fields?

Will

WARNING: multiple messages have this Message-ID (diff)
From: Will Deacon <will.deacon@arm.com>
To: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, catalin.marinas@arm.com,
	dave.martin@arm.com, aph@redhat.com, ryan.arnold@linaro.org,
	sid@reserved-bit.com, adhemerval.zanella@linaro.org,
	mark.rutland@arm.com, marc.zyngier@arm.com
Subject: Re: [PATCH 5/9] arm64: cpufeature: Define helpers for sys_reg id
Date: Wed, 30 Nov 2016 11:04:56 +0000	[thread overview]
Message-ID: <20161130110455.GD2724@arm.com> (raw)
In-Reply-To: <1479994809-9081-6-git-send-email-suzuki.poulose@arm.com>

On Thu, Nov 24, 2016 at 01:40:05PM +0000, Suzuki K Poulose wrote:
> Define helper macros to extract op0, op1, CRn, CRm & op2
> for a given sys_reg id.
> 
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Will Deacon <will.deacon@arm.com>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
>  arch/arm64/include/asm/sysreg.h | 21 ++++++++++++++++++++-
>  1 file changed, 20 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 6c80b36..488b939 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -34,8 +34,27 @@
>   *	[11-8]  : CRm
>   *	[7-5]   : Op2
>   */
> +#define Op0_shift	19
> +#define Op0_mask	0x3
> +#define Op1_shift	16
> +#define Op1_mask	0x7
> +#define CRn_shift	12
> +#define CRn_mask	0xf
> +#define CRm_shift	8
> +#define CRm_mask	0xf
> +#define Op2_shift	5
> +#define Op2_mask	0x7
> +
>  #define sys_reg(op0, op1, crn, crm, op2) \
> -	((((op0)&3)<<19)|((op1)<<16)|((crn)<<12)|((crm)<<8)|((op2)<<5))
> +	((((op0) & Op0_mask) << Op0_shift) | \
> +	 ((op1) << Op1_shift) | ((crn) << CRn_shift) | \
> +	 ((crm) << CRm_shift) | ((op2) << Op2_shift))

You're preserving the current behaviour here, but why do we care so much
about masking op0 but then not bother masking any of the other fields?

Will

  reply	other threads:[~2016-11-30 11:04 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-11-24 13:40 [PATCH 0/9] arm64: Expose CPUID registers via emulation Suzuki K Poulose
2016-11-24 13:40 ` Suzuki K Poulose
2016-11-24 13:40 ` [PATCH 1/9] arm64: cpufeature: treat unknown fields as RES0 Suzuki K Poulose
2016-11-24 13:40   ` Suzuki K Poulose
2016-11-24 13:40 ` [PATCH 2/9] arm64: cpufeature: remove explicit RAZ fields Suzuki K Poulose
2016-11-24 13:40   ` Suzuki K Poulose
2016-11-24 13:40 ` [PATCH 3/9] arm64: cpufeature: Cleanup feature bit tables Suzuki K Poulose
2016-11-24 13:40   ` Suzuki K Poulose
2016-11-24 13:40 ` [PATCH 4/9] arm64: cpufeature: Document the rules of safe value for features Suzuki K Poulose
2016-11-24 13:40   ` Suzuki K Poulose
2016-11-24 13:40 ` [PATCH 5/9] arm64: cpufeature: Define helpers for sys_reg id Suzuki K Poulose
2016-11-24 13:40   ` Suzuki K Poulose
2016-11-30 11:04   ` Will Deacon [this message]
2016-11-30 11:04     ` Will Deacon
2016-11-30 14:16     ` Suzuki K Poulose
2016-11-30 14:16       ` Suzuki K Poulose
2016-11-24 13:40 ` [PATCH 6/9] arm64: Add helper to decode register from instruction Suzuki K Poulose
2016-11-24 13:40   ` Suzuki K Poulose
2016-11-24 13:40 ` [PATCH 7/9] arm64: cpufeature: Track user visible fields Suzuki K Poulose
2016-11-24 13:40   ` Suzuki K Poulose
2016-11-24 13:40 ` [PATCH 8/9] arm64: cpufeature: Expose CPUID registers by emulation Suzuki K Poulose
2016-11-24 13:40   ` Suzuki K Poulose
2016-11-24 13:40 ` [PATCH 9/9] arm64: Documentation - Expose CPU feature registers Suzuki K Poulose
2016-11-24 13:40   ` Suzuki K Poulose
2016-11-24 18:44   ` Catalin Marinas
2016-11-24 18:44     ` Catalin Marinas
2016-11-30 11:41     ` Suzuki K Poulose
2016-11-30 11:41       ` Suzuki K Poulose
2016-11-30 11:14   ` Siddhesh Poyarekar
2016-11-30 11:14     ` Siddhesh Poyarekar
2016-11-30 11:30     ` Suzuki K Poulose
2016-11-30 11:30       ` Suzuki K Poulose
2016-11-30 11:33       ` Siddhesh Poyarekar
2016-11-30 11:33         ` Siddhesh Poyarekar
2016-11-30 11:31     ` Catalin Marinas
2016-11-30 11:31       ` Catalin Marinas

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