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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 15/15] drm/i915: Pass crtc state to vlv_compute_wm_level()
Date: Fri, 2 Dec 2016 11:59:16 +0200	[thread overview]
Message-ID: <20161202095916.GR31595@intel.com> (raw)
In-Reply-To: <903dbda5-e97f-ee8b-bcbc-3de5682c076f@linux.intel.com>

On Thu, Dec 01, 2016 at 03:47:55PM +0100, Maarten Lankhorst wrote:
> Op 28-11-16 om 18:37 schreef ville.syrjala@linux.intel.com:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Rather than accessing crtc->config in vlv_compute_wm_level() let's
> > pass in the crtc state explicitly. One step closer to atomic.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Yay. All users of intel_crtc->config have to die in the future, but this is temporarily a legit use for it.
> 
> For patch 13, 14 and 15
> 
> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> >  drivers/gpu/drm/i915/intel_pm.c | 20 +++++++++++---------
> >  1 file changed, 11 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 291843c2b61b..2a2aa8968b93 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -978,24 +978,26 @@ static void vlv_setup_wm_latency(struct drm_i915_private *dev_priv)
> >  	}
> >  }
> >  
> > -static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
> > -				     struct intel_crtc *crtc,
> > -				     const struct intel_plane_state *state,
> > +static uint16_t vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
> > +				     const struct intel_plane_state *plane_state,
> >  				     int level)
> >  {
> > +	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
> >  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > +	const struct drm_display_mode *adjusted_mode =
> > +		&crtc_state->base.adjusted_mode;
> >  	int clock, htotal, cpp, width, wm;
> >  
> >  	if (dev_priv->wm.pri_latency[level] == 0)
> >  		return USHRT_MAX;
> >  
> > -	if (!state->base.visible)
> > +	if (!plane_state->base.visible)
> >  		return 0;
> >  
> > -	cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
> > -	clock = crtc->config->base.adjusted_mode.crtc_clock;
> > -	htotal = crtc->config->base.adjusted_mode.crtc_htotal;
> > -	width = crtc->config->pipe_src_w;
> > +	cpp = drm_format_plane_cpp(plane_state->base.fb->pixel_format, 0);
> > +	clock = adjusted_mode->crtc_clock;
> > +	htotal = adjusted_mode->crtc_htotal;
> > +	width = crtc_state->pipe_src_w;
> >  	if (WARN_ON(htotal == 0))
> >  		htotal = 1;
> >  
> > @@ -1145,7 +1147,7 @@ static void vlv_compute_wm(struct intel_crtc *crtc)
> >  
> >  		/* normal watermarks */
> >  		for (level = 0; level < wm_state->num_levels; level++) {
> > -			int wm = vlv_compute_wm_level(plane, crtc, state, level);
> > +			int wm = vlv_compute_wm_level(crtc->config, state, level);
> >  			int max_wm = plane->wm.fifo_size;
> >  
> >  			/* hack */
> 

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2016-12-02  9:59 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-11-28 17:37 [PATCH 00/15] drm/i915: VLV/CHV atomic wm prep work ville.syrjala
2016-11-28 17:37 ` [PATCH 01/15] drm/i915: Drop the nop intel_update_watermarks() call from haswell_crtc_enable() ville.syrjala
2016-11-28 17:37 ` [PATCH 02/15] drm/i915: Use the ilk_disable_lp_wm() return value ville.syrjala
2016-11-28 17:37 ` [PATCH 03/15] drm/i915: Fix the level 0 max_wm hack on VLV/CHV ville.syrjala
2016-11-28 17:37 ` [PATCH 04/15] drm/i915: Clean up VLV/CHV maxfifo watermark setup ville.syrjala
2016-11-28 17:37 ` [PATCH 05/15] drm/i915: Remove duplicated wm setup for vlv and chv ville.syrjala
2016-11-28 17:37 ` [PATCH 06/15] drm/i915: Organize vlv/chv watermarks by plane_id ville.syrjala
2016-11-28 17:37 ` [PATCH 07/15] drm/i915: Introduce vlv_invert_wm_value() ville.syrjala
2016-11-28 17:37 ` [PATCH 08/15] drm/i915: Pass around dev_priv in vlv wm functions ville.syrjala
2016-12-01 11:51   ` Maarten Lankhorst
2016-11-28 17:37 ` [PATCH 09/15] drm/i915: Protect cxsr state with wm_mutex ville.syrjala
2016-11-28 17:37 ` [PATCH 10/15] drm/i915: Skip vblank wait if cxsr was already off ville.syrjala
2016-11-28 17:37 ` [PATCH 11/15] drm/i915: Protect DSPARB registers with a spinlock ville.syrjala
2016-12-01 11:56   ` Maarten Lankhorst
2016-12-01 13:13     ` Ville Syrjälä
2016-12-01 14:45       ` Maarten Lankhorst
2016-12-02  9:57         ` Ville Syrjälä
2016-12-05 14:13   ` [PATCH v2 " ville.syrjala
2016-12-06  8:26     ` Maarten Lankhorst
2016-12-07 15:57       ` Ville Syrjälä
2016-11-28 17:37 ` [PATCH 12/15] drm/i915: Zero out HOWM registers before writing new WM/HOWM register values ville.syrjala
2016-12-01 14:43   ` Maarten Lankhorst
2016-12-02  9:51     ` Ville Syrjälä
2016-11-28 17:37 ` [PATCH 13/15] drm/i915: Write all DDL registers in one go ville.syrjala
2016-11-28 17:37 ` [PATCH 14/15] drm/i915: Clean up vlv_program_watermarks() ville.syrjala
2016-11-28 17:37 ` [PATCH 15/15] drm/i915: Pass crtc state to vlv_compute_wm_level() ville.syrjala
2016-12-01 14:47   ` Maarten Lankhorst
2016-12-02  9:59     ` Ville Syrjälä [this message]
2016-12-02 13:07     ` Ville Syrjälä
2016-12-06  8:27       ` Maarten Lankhorst
2016-11-28 18:14 ` ✓ Fi.CI.BAT: success for drm/i915: VLV/CHV atomic wm prep work Patchwork
2016-11-29 12:45 ` Patchwork
2016-12-05 14:33 ` [PATCH 00/15] " Ville Syrjälä

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