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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2 11/15] drm/i915: Protect DSPARB registers with a spinlock
Date: Wed, 7 Dec 2016 17:57:47 +0200	[thread overview]
Message-ID: <20161207155747.GO31595@intel.com> (raw)
In-Reply-To: <6df45ce4-dce1-9630-6979-7c8a495190ca@linux.intel.com>

On Tue, Dec 06, 2016 at 09:26:22AM +0100, Maarten Lankhorst wrote:
> Op 05-12-16 om 15:13 schreef ville.syrjala@linux.intel.com:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Each DSPARB register can house bits for two separate pipes, hence
> > we must protect the registers during reprogramming so that parallel
> > FIFO reconfigurations happening simultaneosly on multiple pipes won't
> > corrupt each others values.
> >
> > We'll use a new spinlock for this instead of the wm_mutex since we'll
> > have to move the DSPARB programming to happen from the vblank evade
> > critical section, and we can't use mutexes in there.
> >
> > v2: Document why we use a spinlock instead of a mutex (Maarten)
> >
> > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

Thanks. Pushed to dinq.

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2016-12-07 15:57 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-11-28 17:37 [PATCH 00/15] drm/i915: VLV/CHV atomic wm prep work ville.syrjala
2016-11-28 17:37 ` [PATCH 01/15] drm/i915: Drop the nop intel_update_watermarks() call from haswell_crtc_enable() ville.syrjala
2016-11-28 17:37 ` [PATCH 02/15] drm/i915: Use the ilk_disable_lp_wm() return value ville.syrjala
2016-11-28 17:37 ` [PATCH 03/15] drm/i915: Fix the level 0 max_wm hack on VLV/CHV ville.syrjala
2016-11-28 17:37 ` [PATCH 04/15] drm/i915: Clean up VLV/CHV maxfifo watermark setup ville.syrjala
2016-11-28 17:37 ` [PATCH 05/15] drm/i915: Remove duplicated wm setup for vlv and chv ville.syrjala
2016-11-28 17:37 ` [PATCH 06/15] drm/i915: Organize vlv/chv watermarks by plane_id ville.syrjala
2016-11-28 17:37 ` [PATCH 07/15] drm/i915: Introduce vlv_invert_wm_value() ville.syrjala
2016-11-28 17:37 ` [PATCH 08/15] drm/i915: Pass around dev_priv in vlv wm functions ville.syrjala
2016-12-01 11:51   ` Maarten Lankhorst
2016-11-28 17:37 ` [PATCH 09/15] drm/i915: Protect cxsr state with wm_mutex ville.syrjala
2016-11-28 17:37 ` [PATCH 10/15] drm/i915: Skip vblank wait if cxsr was already off ville.syrjala
2016-11-28 17:37 ` [PATCH 11/15] drm/i915: Protect DSPARB registers with a spinlock ville.syrjala
2016-12-01 11:56   ` Maarten Lankhorst
2016-12-01 13:13     ` Ville Syrjälä
2016-12-01 14:45       ` Maarten Lankhorst
2016-12-02  9:57         ` Ville Syrjälä
2016-12-05 14:13   ` [PATCH v2 " ville.syrjala
2016-12-06  8:26     ` Maarten Lankhorst
2016-12-07 15:57       ` Ville Syrjälä [this message]
2016-11-28 17:37 ` [PATCH 12/15] drm/i915: Zero out HOWM registers before writing new WM/HOWM register values ville.syrjala
2016-12-01 14:43   ` Maarten Lankhorst
2016-12-02  9:51     ` Ville Syrjälä
2016-11-28 17:37 ` [PATCH 13/15] drm/i915: Write all DDL registers in one go ville.syrjala
2016-11-28 17:37 ` [PATCH 14/15] drm/i915: Clean up vlv_program_watermarks() ville.syrjala
2016-11-28 17:37 ` [PATCH 15/15] drm/i915: Pass crtc state to vlv_compute_wm_level() ville.syrjala
2016-12-01 14:47   ` Maarten Lankhorst
2016-12-02  9:59     ` Ville Syrjälä
2016-12-02 13:07     ` Ville Syrjälä
2016-12-06  8:27       ` Maarten Lankhorst
2016-11-28 18:14 ` ✓ Fi.CI.BAT: success for drm/i915: VLV/CHV atomic wm prep work Patchwork
2016-11-29 12:45 ` Patchwork
2016-12-05 14:33 ` [PATCH 00/15] " Ville Syrjälä

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