From: Andi Kleen <andi@firstfloor.org>
To: Peter Zijlstra <peterz@infradead.org>
Cc: Andi Kleen <andi@firstfloor.org>,
linux-kernel@vger.kernel.org, Andi Kleen <ak@linux.intel.com>,
alexander.shishkin@intel.com, kan.liang@intel.com,
stable@vger.kernel.org
Subject: Re: [PATCH] perf/x86: Fix exclusion of BTS and LBR for Goldmont
Date: Tue, 6 Dec 2016 06:53:49 -0800 [thread overview]
Message-ID: <20161206145349.GN26852@two.firstfloor.org> (raw)
In-Reply-To: <20161206123848.GS3207@twins.programming.kicks-ass.net>
> > - if (x86_pmu.lbr_pt_coexist)
> > + if (what == x86_lbr_exclusive_pt && x86_pmu.lbr_pt_coexist)
> > return 0;
>
> This would also allow PT & BTS at the same time, is that a supported
> configuration?
Yes it is on Goldmont.
-Andi
next prev parent reply other threads:[~2016-12-06 14:53 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-12-02 23:17 [PATCH] perf/x86: Fix exclusion of BTS and LBR for Goldmont Andi Kleen
2016-12-06 12:38 ` Peter Zijlstra
2016-12-06 14:53 ` Andi Kleen [this message]
-- strict thread matches above, loose matches on Subject: below --
2016-12-09 0:14 Andi Kleen
2016-12-09 15:49 ` Peter Zijlstra
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