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From: Christoffer Dall <christoffer.dall@linaro.org>
To: Auger Eric <eric.auger@redhat.com>
Cc: marc.zyngier@arm.com, Vijaya Kumar K <Vijaya.Kumar@cavium.com>,
	kvmarm@lists.cs.columbia.edu,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v9 05/11] arm/arm64: vgic: Introduce VENG0 and VENG1 fields to vmcr struct
Date: Thu, 8 Dec 2016 13:21:15 +0100	[thread overview]
Message-ID: <20161208122115.GG4816@cbox> (raw)
In-Reply-To: <ace0aa83-aa6e-ca64-8edf-fcd2dd07585e@redhat.com>

On Thu, Dec 08, 2016 at 12:52:39PM +0100, Auger Eric wrote:
> Hi Vijay,
> 
> On 28/11/2016 15:28, Christoffer Dall wrote:
> > On Wed, Nov 23, 2016 at 06:31:52PM +0530, vijay.kilari@gmail.com wrote:
> >> From: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
> >>
> >> ICC_VMCR_EL2 supports virtual access to ICC_IGRPEN1_EL1.Enable
> >> and ICC_IGRPEN0_EL1.Enable fields. Add grpen0 and grpen1 member
> >> variables to struct vmcr to support read and write of these fields.
> >>
> >> Also refactor vgic_set_vmcr and vgic_get_vmcr() code.
> >> Drop ICH_VMCR_CTLR_SHIFT and ICH_VMCR_CTLR_MASK macros and instead
> >> use ICH_VMCR_EOI* and ICH_VMCR_CBPR* macros
> >> .
> >> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
> >> ---
> >>  include/linux/irqchip/arm-gic-v3.h |  2 --
> >>  virt/kvm/arm/vgic/vgic-mmio-v2.c   | 16 ----------------
> >>  virt/kvm/arm/vgic/vgic-mmio.c      | 16 ++++++++++++++++
> >>  virt/kvm/arm/vgic/vgic-v3.c        | 22 ++++++++++++++++++++--
> >>  virt/kvm/arm/vgic/vgic.h           |  5 +++++
> >>  5 files changed, 41 insertions(+), 20 deletions(-)
> >>
> >> diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
> >> index b4f8287..406fc3e 100644
> >> --- a/include/linux/irqchip/arm-gic-v3.h
> >> +++ b/include/linux/irqchip/arm-gic-v3.h
> >> @@ -404,8 +404,6 @@
> >>  #define ICH_HCR_EN			(1 << 0)
> >>  #define ICH_HCR_UIE			(1 << 1)
> >>  
> >> -#define ICH_VMCR_CTLR_SHIFT		0
> >> -#define ICH_VMCR_CTLR_MASK		(0x21f << ICH_VMCR_CTLR_SHIFT)
> >>  #define ICH_VMCR_CBPR_SHIFT		4
> >>  #define ICH_VMCR_CBPR_MASK		(1 << ICH_VMCR_CBPR_SHIFT)
> >>  #define ICH_VMCR_EOIM_SHIFT		9
> >> diff --git a/virt/kvm/arm/vgic/vgic-mmio-v2.c b/virt/kvm/arm/vgic/vgic-mmio-v2.c
> >> index 2cb04b7..ad353b5 100644
> >> --- a/virt/kvm/arm/vgic/vgic-mmio-v2.c
> >> +++ b/virt/kvm/arm/vgic/vgic-mmio-v2.c
> >> @@ -212,22 +212,6 @@ static void vgic_mmio_write_sgipends(struct kvm_vcpu *vcpu,
> >>  	}
> >>  }
> >>  
> >> -static void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
> >> -{
> >> -	if (kvm_vgic_global_state.type == VGIC_V2)
> >> -		vgic_v2_set_vmcr(vcpu, vmcr);
> >> -	else
> >> -		vgic_v3_set_vmcr(vcpu, vmcr);
> >> -}
> >> -
> >> -static void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
> >> -{
> >> -	if (kvm_vgic_global_state.type == VGIC_V2)
> >> -		vgic_v2_get_vmcr(vcpu, vmcr);
> >> -	else
> >> -		vgic_v3_get_vmcr(vcpu, vmcr);
> >> -}
> >> -
> >>  #define GICC_ARCH_VERSION_V2	0x2
> >>  
> >>  /* These are for userland accesses only, there is no guest-facing emulation. */
> >> diff --git a/virt/kvm/arm/vgic/vgic-mmio.c b/virt/kvm/arm/vgic/vgic-mmio.c
> >> index 0d1bc98..f81e0e5 100644
> >> --- a/virt/kvm/arm/vgic/vgic-mmio.c
> >> +++ b/virt/kvm/arm/vgic/vgic-mmio.c
> >> @@ -416,6 +416,22 @@ int vgic_validate_mmio_region_addr(struct kvm_device *dev,
> >>  	return -ENXIO;
> >>  }
> >>  
> >> +void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
> >> +{
> >> +	if (kvm_vgic_global_state.type == VGIC_V2)
> >> +		vgic_v2_set_vmcr(vcpu, vmcr);
> >> +	else
> >> +		vgic_v3_set_vmcr(vcpu, vmcr);
> >> +}
> >> +
> >> +void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
> >> +{
> >> +	if (kvm_vgic_global_state.type == VGIC_V2)
> >> +		vgic_v2_get_vmcr(vcpu, vmcr);
> >> +	else
> >> +		vgic_v3_get_vmcr(vcpu, vmcr);
> >> +}
> >> +
> >>  /*
> >>   * kvm_mmio_read_buf() returns a value in a format where it can be converted
> >>   * to a byte array and be directly observed as the guest wanted it to appear
> >> diff --git a/virt/kvm/arm/vgic/vgic-v3.c b/virt/kvm/arm/vgic/vgic-v3.c
> >> index 9f0dae3..a3ff04b 100644
> >> --- a/virt/kvm/arm/vgic/vgic-v3.c
> >> +++ b/virt/kvm/arm/vgic/vgic-v3.c
> >> @@ -175,10 +175,19 @@ void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
> >>  {
> >>  	u32 vmcr;
> >>  
> >> -	vmcr  = (vmcrp->ctlr << ICH_VMCR_CTLR_SHIFT) & ICH_VMCR_CTLR_MASK;
> >> +	/*
> >> +	 * Ignore the FIQen bit, because GIC emulation always implies
> >> +	 * SRE=1 which means the vFIQEn bit is also RES1.
> >> +	 */
> >> +	vmcr = (vmcrp->ctlr & ICC_CTLR_EL1_EOImode_MASK) >>
> >> +		ICC_CTLR_EL1_EOImode_SHIFT;
> >> +	vmcr = (vmcr << ICH_VMCR_EOIM_SHIFT) & ICH_VMCR_EOIM_MASK;

> I am not able to understand why we use ICC_CTLR _*macros here? Please
> could you explain it to me? Besides if we want to ignore the FIQen bit
> can't we change the ICH_VMCR_CTLR_MASK value?
> 
This first statement is setting the vmcr to the ctlr's bit[1], but
placed in bit[0], and then the next statement is moving that bit value
to the corresponding place in the vmcr.  I think this is correct
(although a little opaque).

There's also a newer series on the list, just so you know.

Thanks,
-Christoffer

WARNING: multiple messages have this Message-ID (diff)
From: christoffer.dall@linaro.org (Christoffer Dall)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v9 05/11] arm/arm64: vgic: Introduce VENG0 and VENG1 fields to vmcr struct
Date: Thu, 8 Dec 2016 13:21:15 +0100	[thread overview]
Message-ID: <20161208122115.GG4816@cbox> (raw)
In-Reply-To: <ace0aa83-aa6e-ca64-8edf-fcd2dd07585e@redhat.com>

On Thu, Dec 08, 2016 at 12:52:39PM +0100, Auger Eric wrote:
> Hi Vijay,
> 
> On 28/11/2016 15:28, Christoffer Dall wrote:
> > On Wed, Nov 23, 2016 at 06:31:52PM +0530, vijay.kilari at gmail.com wrote:
> >> From: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
> >>
> >> ICC_VMCR_EL2 supports virtual access to ICC_IGRPEN1_EL1.Enable
> >> and ICC_IGRPEN0_EL1.Enable fields. Add grpen0 and grpen1 member
> >> variables to struct vmcr to support read and write of these fields.
> >>
> >> Also refactor vgic_set_vmcr and vgic_get_vmcr() code.
> >> Drop ICH_VMCR_CTLR_SHIFT and ICH_VMCR_CTLR_MASK macros and instead
> >> use ICH_VMCR_EOI* and ICH_VMCR_CBPR* macros
> >> .
> >> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
> >> ---
> >>  include/linux/irqchip/arm-gic-v3.h |  2 --
> >>  virt/kvm/arm/vgic/vgic-mmio-v2.c   | 16 ----------------
> >>  virt/kvm/arm/vgic/vgic-mmio.c      | 16 ++++++++++++++++
> >>  virt/kvm/arm/vgic/vgic-v3.c        | 22 ++++++++++++++++++++--
> >>  virt/kvm/arm/vgic/vgic.h           |  5 +++++
> >>  5 files changed, 41 insertions(+), 20 deletions(-)
> >>
> >> diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
> >> index b4f8287..406fc3e 100644
> >> --- a/include/linux/irqchip/arm-gic-v3.h
> >> +++ b/include/linux/irqchip/arm-gic-v3.h
> >> @@ -404,8 +404,6 @@
> >>  #define ICH_HCR_EN			(1 << 0)
> >>  #define ICH_HCR_UIE			(1 << 1)
> >>  
> >> -#define ICH_VMCR_CTLR_SHIFT		0
> >> -#define ICH_VMCR_CTLR_MASK		(0x21f << ICH_VMCR_CTLR_SHIFT)
> >>  #define ICH_VMCR_CBPR_SHIFT		4
> >>  #define ICH_VMCR_CBPR_MASK		(1 << ICH_VMCR_CBPR_SHIFT)
> >>  #define ICH_VMCR_EOIM_SHIFT		9
> >> diff --git a/virt/kvm/arm/vgic/vgic-mmio-v2.c b/virt/kvm/arm/vgic/vgic-mmio-v2.c
> >> index 2cb04b7..ad353b5 100644
> >> --- a/virt/kvm/arm/vgic/vgic-mmio-v2.c
> >> +++ b/virt/kvm/arm/vgic/vgic-mmio-v2.c
> >> @@ -212,22 +212,6 @@ static void vgic_mmio_write_sgipends(struct kvm_vcpu *vcpu,
> >>  	}
> >>  }
> >>  
> >> -static void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
> >> -{
> >> -	if (kvm_vgic_global_state.type == VGIC_V2)
> >> -		vgic_v2_set_vmcr(vcpu, vmcr);
> >> -	else
> >> -		vgic_v3_set_vmcr(vcpu, vmcr);
> >> -}
> >> -
> >> -static void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
> >> -{
> >> -	if (kvm_vgic_global_state.type == VGIC_V2)
> >> -		vgic_v2_get_vmcr(vcpu, vmcr);
> >> -	else
> >> -		vgic_v3_get_vmcr(vcpu, vmcr);
> >> -}
> >> -
> >>  #define GICC_ARCH_VERSION_V2	0x2
> >>  
> >>  /* These are for userland accesses only, there is no guest-facing emulation. */
> >> diff --git a/virt/kvm/arm/vgic/vgic-mmio.c b/virt/kvm/arm/vgic/vgic-mmio.c
> >> index 0d1bc98..f81e0e5 100644
> >> --- a/virt/kvm/arm/vgic/vgic-mmio.c
> >> +++ b/virt/kvm/arm/vgic/vgic-mmio.c
> >> @@ -416,6 +416,22 @@ int vgic_validate_mmio_region_addr(struct kvm_device *dev,
> >>  	return -ENXIO;
> >>  }
> >>  
> >> +void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
> >> +{
> >> +	if (kvm_vgic_global_state.type == VGIC_V2)
> >> +		vgic_v2_set_vmcr(vcpu, vmcr);
> >> +	else
> >> +		vgic_v3_set_vmcr(vcpu, vmcr);
> >> +}
> >> +
> >> +void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
> >> +{
> >> +	if (kvm_vgic_global_state.type == VGIC_V2)
> >> +		vgic_v2_get_vmcr(vcpu, vmcr);
> >> +	else
> >> +		vgic_v3_get_vmcr(vcpu, vmcr);
> >> +}
> >> +
> >>  /*
> >>   * kvm_mmio_read_buf() returns a value in a format where it can be converted
> >>   * to a byte array and be directly observed as the guest wanted it to appear
> >> diff --git a/virt/kvm/arm/vgic/vgic-v3.c b/virt/kvm/arm/vgic/vgic-v3.c
> >> index 9f0dae3..a3ff04b 100644
> >> --- a/virt/kvm/arm/vgic/vgic-v3.c
> >> +++ b/virt/kvm/arm/vgic/vgic-v3.c
> >> @@ -175,10 +175,19 @@ void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
> >>  {
> >>  	u32 vmcr;
> >>  
> >> -	vmcr  = (vmcrp->ctlr << ICH_VMCR_CTLR_SHIFT) & ICH_VMCR_CTLR_MASK;
> >> +	/*
> >> +	 * Ignore the FIQen bit, because GIC emulation always implies
> >> +	 * SRE=1 which means the vFIQEn bit is also RES1.
> >> +	 */
> >> +	vmcr = (vmcrp->ctlr & ICC_CTLR_EL1_EOImode_MASK) >>
> >> +		ICC_CTLR_EL1_EOImode_SHIFT;
> >> +	vmcr = (vmcr << ICH_VMCR_EOIM_SHIFT) & ICH_VMCR_EOIM_MASK;

> I am not able to understand why we use ICC_CTLR _*macros here? Please
> could you explain it to me? Besides if we want to ignore the FIQen bit
> can't we change the ICH_VMCR_CTLR_MASK value?
> 
This first statement is setting the vmcr to the ctlr's bit[1], but
placed in bit[0], and then the next statement is moving that bit value
to the corresponding place in the vmcr.  I think this is correct
(although a little opaque).

There's also a newer series on the list, just so you know.

Thanks,
-Christoffer

  reply	other threads:[~2016-12-08 12:20 UTC|newest]

Thread overview: 78+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-11-23 13:01 [PATCH v9 0/11] arm/arm64: vgic: Implement API for vGICv3 live migration vijay.kilari
2016-11-23 13:01 ` vijay.kilari at gmail.com
2016-11-23 13:01 ` [PATCH v9 01/11] arm/arm64: vgic: Implement support for userspace access vijay.kilari
2016-11-23 13:01   ` vijay.kilari at gmail.com
2016-11-28 13:05   ` Christoffer Dall
2016-11-28 13:05     ` Christoffer Dall
2016-12-06 11:42     ` Auger Eric
2016-12-06 11:42       ` Auger Eric
2016-12-06 14:30       ` Christoffer Dall
2016-12-06 14:30         ` Christoffer Dall
2016-12-15  7:36       ` Vijay Kilari
2016-12-15  7:36         ` Vijay Kilari
2016-12-16 12:40         ` Auger Eric
2016-12-16 12:40           ` Auger Eric
2016-11-23 13:01 ` [PATCH v9 02/11] arm/arm64: vgic: Add distributor and redistributor access vijay.kilari
2016-11-23 13:01   ` vijay.kilari at gmail.com
2016-11-28 13:08   ` Christoffer Dall
2016-11-28 13:08     ` Christoffer Dall
2016-12-06 13:18     ` Auger Eric
2016-12-06 13:18       ` Auger Eric
2016-11-23 13:01 ` [PATCH v9 03/11] arm/arm64: vgic: Introduce find_reg_by_id() vijay.kilari
2016-11-23 13:01   ` vijay.kilari at gmail.com
2016-12-06 13:27   ` Auger Eric
2016-12-06 13:27     ` Auger Eric
2016-11-23 13:01 ` [PATCH v9 04/11] irqchip/gic-v3: Add missing system register definitions vijay.kilari
2016-11-23 13:01   ` vijay.kilari at gmail.com
2016-12-06 13:53   ` Auger Eric
2016-12-06 13:53     ` Auger Eric
2017-01-23 10:55     ` Vijay Kilari
2017-01-23 10:55       ` Vijay Kilari
2016-11-23 13:01 ` [PATCH v9 05/11] arm/arm64: vgic: Introduce VENG0 and VENG1 fields to vmcr struct vijay.kilari
2016-11-23 13:01   ` vijay.kilari at gmail.com
2016-11-28 14:28   ` Christoffer Dall
2016-11-28 14:28     ` Christoffer Dall
2016-12-08 11:52     ` Auger Eric
2016-12-08 11:52       ` Auger Eric
2016-12-08 12:21       ` Christoffer Dall [this message]
2016-12-08 12:21         ` Christoffer Dall
2016-12-08 12:50         ` Auger Eric
2016-12-08 12:50           ` Auger Eric
2016-12-11 16:38           ` Christoffer Dall
2016-12-11 16:38             ` Christoffer Dall
2016-11-23 13:01 ` [PATCH v9 06/11] arm/arm64: vgic: Implement VGICv3 CPU interface access vijay.kilari
2016-11-23 13:01   ` vijay.kilari at gmail.com
2016-11-28 19:39   ` Christoffer Dall
2016-11-28 19:39     ` Christoffer Dall
2016-11-29  7:38     ` Vijay Kilari
2016-11-29  7:38       ` Vijay Kilari
2016-11-29  8:37       ` Christoffer Dall
2016-11-29  8:37         ` Christoffer Dall
2016-11-29 10:01         ` Vijay Kilari
2016-11-29 10:01           ` Vijay Kilari
2016-11-29 10:51           ` Christoffer Dall
2016-11-29 10:51             ` Christoffer Dall
2016-11-23 13:01 ` [PATCH v9 07/11] arm/arm64: vgic: Implement KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO ioctl vijay.kilari
2016-11-23 13:01   ` vijay.kilari at gmail.com
2016-11-28 19:50   ` Christoffer Dall
2016-11-28 19:50     ` Christoffer Dall
2016-11-29 16:36     ` Vijay Kilari
2016-11-29 16:36       ` Vijay Kilari
2016-11-29 21:09       ` Christoffer Dall
2016-11-29 21:09         ` Christoffer Dall
2016-11-30  7:10         ` Peter Maydell
2016-11-30  7:10           ` Peter Maydell
2016-11-30  8:24           ` Christoffer Dall
2016-11-30  8:24             ` Christoffer Dall
2016-11-30  8:29             ` Peter Maydell
2016-11-30  8:29               ` Peter Maydell
2016-11-23 13:01 ` [PATCH v9 08/11] arm/arm64: Documentation: Update arm-vgic-v3.txt vijay.kilari
2016-11-23 13:01   ` vijay.kilari at gmail.com
2016-11-23 13:01 ` [PATCH v9 09/11] arm: coproc: Drop const from coproc reg access function vijay.kilari
2016-11-23 13:01   ` vijay.kilari at gmail.com
2016-11-23 13:01 ` [PATCH v9 10/11] arm: coproc: Introduce find_coproc_reg_by_id() vijay.kilari
2016-11-23 13:01   ` vijay.kilari at gmail.com
2016-11-23 13:01 ` [PATCH v9 11/11] arm: vgic: Save and restore GICv3 CPU interface regs for AArch32 vijay.kilari
2016-11-23 13:01   ` vijay.kilari at gmail.com
2016-11-28 19:51 ` [PATCH v9 0/11] arm/arm64: vgic: Implement API for vGICv3 live migration Christoffer Dall
2016-11-28 19:51   ` Christoffer Dall

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