From: Peter Zijlstra <peterz@infradead.org>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: LKML <linux-kernel@vger.kernel.org>,
x86@kernel.org, Borislav Petkov <bp@alien8.de>,
Bruce Schlobohm <bruce.schlobohm@intel.com>,
Roland Scheidegger <rscheidegger_lists@hispeed.ch>,
Kevin Stanton <kevin.b.stanton@intel.com>,
Allen Hung <allen_hung@dell.com>
Subject: Re: [patch 1/2] x86/tsc: Validate TSC_ADJUST after resume
Date: Tue, 13 Dec 2016 14:22:50 +0100 [thread overview]
Message-ID: <20161213132250.GK3124@twins.programming.kicks-ass.net> (raw)
In-Reply-To: <20161213131211.317654500@linutronix.de>
On Tue, Dec 13, 2016 at 01:14:17PM -0000, Thomas Gleixner wrote:
> --- a/arch/x86/power/cpu.c
> +++ b/arch/x86/power/cpu.c
> @@ -256,6 +256,7 @@ static void notrace __restore_processor_
> mtrr_bp_restore();
> perf_restore_debug_store();
> msr_restore_context(ctxt);
> + tsc_verify_tsc_adjust(true);
> }
Should we do that sooner, as in before calling
restore_sched_clock_state() ? Otherwise we recompute the sched_clock
deltas vs the wrecked TSC and then fix it up through the ADJUST,
wrecking our sched clock again.
next prev parent reply other threads:[~2016-12-13 13:23 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-12-13 13:14 [patch 0/2] tsc/adjust: Cure suspend/resume issues and prevent TSC deadline timer irq storm Thomas Gleixner
2016-12-13 13:14 ` [patch 2/2] x86/tsc: Force TSC_ADJUST register to value >= zero Thomas Gleixner
2016-12-13 13:43 ` Peter Zijlstra
2016-12-13 15:49 ` Thomas Gleixner
2016-12-15 10:53 ` [tip:x86/timers] " tip-bot for Thomas Gleixner
2016-12-16 11:46 ` [patch 2/2] " Thomas Gleixner
2016-12-16 11:52 ` Ingo Molnar
2016-12-16 11:53 ` Thomas Gleixner
2016-12-16 13:33 ` Thomas Gleixner
2016-12-13 13:14 ` [patch 1/2] x86/tsc: Validate TSC_ADJUST after resume Thomas Gleixner
2016-12-13 13:22 ` Peter Zijlstra [this message]
2016-12-13 13:23 ` Thomas Gleixner
2016-12-15 10:52 ` [tip:x86/timers] " tip-bot for Thomas Gleixner
2016-12-13 16:34 ` [patch 0/2] tsc/adjust: Cure suspend/resume issues and prevent TSC deadline timer irq storm Roland Scheidegger
2016-12-13 16:46 ` Thomas Gleixner
2016-12-14 1:36 ` Roland Scheidegger
2016-12-14 7:31 ` Thomas Gleixner
2016-12-14 20:59 ` Thomas Gleixner
2016-12-14 21:40 ` Thomas Gleixner
2016-12-14 22:54 ` Roland Scheidegger
2016-12-15 9:31 ` Thomas Gleixner
2017-01-26 23:40 ` Stanton, Kevin B
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