From: Segher Boessenkool <segher@kernel.crashing.org>
To: Christophe Leroy <christophe.leroy@c-s.fr>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>,
Paul Mackerras <paulus@samba.org>,
Michael Ellerman <mpe@ellerman.id.au>,
Scott Wood <oss@buserror.net>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org
Subject: Re: [RFC 1/2] powerpc/32: Unset MSR RI in exception epilogs
Date: Tue, 13 Dec 2016 13:15:14 -0600 [thread overview]
Message-ID: <20161213191514.GJ30845@gate.crashing.org> (raw)
In-Reply-To: <e6292c23163fac0865def3a385ff01d1497b005b.1481652710.git.christophe.leroy@c-s.fr>
On Tue, Dec 13, 2016 at 07:19:41PM +0100, Christophe Leroy wrote:
> At exception prologs, once SRR0 and SRR1 have been saved, MSR RI is
> set to mark the interrupt as recoverable.
>
> MSR RI has to be unset before writing into SRR0 and SRR1 at exception
> epilogs.
Why? What goes wrong without this? Etc.
Segher
next prev parent reply other threads:[~2016-12-13 19:39 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <cover.1481652710.git.christophe.leroy@c-s.fr>
2016-12-13 18:19 ` [RFC 1/2] powerpc/32: Unset MSR RI in exception epilogs Christophe Leroy
2016-12-13 19:15 ` Segher Boessenkool [this message]
2016-12-13 20:39 ` christophe leroy
2016-12-13 22:54 ` Segher Boessenkool
2016-12-14 8:40 ` Peter Zijlstra
2016-12-13 18:19 ` [RFC 2/2] powerpc/8xx: Perf events on PPC 8xx Christophe Leroy
2016-12-14 9:16 ` Peter Zijlstra
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