From: Segher Boessenkool <segher@kernel.crashing.org>
To: christophe leroy <christophe.leroy@c-s.fr>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>,
Paul Mackerras <paulus@samba.org>,
Michael Ellerman <mpe@ellerman.id.au>,
Scott Wood <oss@buserror.net>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org
Subject: Re: [RFC 1/2] powerpc/32: Unset MSR RI in exception epilogs
Date: Tue, 13 Dec 2016 16:54:30 -0600 [thread overview]
Message-ID: <20161213225430.GN30845@gate.crashing.org> (raw)
In-Reply-To: <1fbdc292-df1c-f6a8-efc4-019350209536@c-s.fr>
On Tue, Dec 13, 2016 at 09:39:55PM +0100, christophe leroy wrote:
> Le 13/12/2016 à 20:15, Segher Boessenkool a écrit :
> >On Tue, Dec 13, 2016 at 07:19:41PM +0100, Christophe Leroy wrote:
> >>At exception prologs, once SRR0 and SRR1 have been saved, MSR RI is
> >>set to mark the interrupt as recoverable.
> >>
> >>MSR RI has to be unset before writing into SRR0 and SRR1 at exception
> >>epilogs.
> >
> >Why? What goes wrong without this? Etc.
>
> The following patch implements perf instruction counting using the 8xx
> debug counters. When the counter reaches 0, it fires a debug exception.
> If that exception happens between the setting of srr0/srr1 and the rfi,
> values set to srr0/srr1 are lost and we end up with an Oops.
>
> To avoid that, MSR RI has to be unset. That way, because the debug
> counters mode is set to masked mode in register LCTRL2, no debug
> interrupt will happen during that critical phase.
Okay, so why then do you do an expensive sequence on all other processors?
Segher
next prev parent reply other threads:[~2016-12-13 22:56 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <cover.1481652710.git.christophe.leroy@c-s.fr>
2016-12-13 18:19 ` [RFC 1/2] powerpc/32: Unset MSR RI in exception epilogs Christophe Leroy
2016-12-13 19:15 ` Segher Boessenkool
2016-12-13 20:39 ` christophe leroy
2016-12-13 22:54 ` Segher Boessenkool [this message]
2016-12-14 8:40 ` Peter Zijlstra
2016-12-13 18:19 ` [RFC 2/2] powerpc/8xx: Perf events on PPC 8xx Christophe Leroy
2016-12-14 9:16 ` Peter Zijlstra
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