From: Christoffer Dall <christoffer.dall@linaro.org>
To: kvmarm@lists.cs.columbia.edu,
linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org
Cc: Marc Zyngier <marc.zyngier@arm.com>
Subject: Re: [RFC PATCH 0/7] KVM: arm/arm64: Optimize arch timer register handling
Date: Fri, 6 Jan 2017 11:01:47 +0100 [thread overview]
Message-ID: <20170106100147.GC21089@cbox> (raw)
In-Reply-To: <20161210204712.21830-1-christoffer.dall@linaro.org>
On Sat, Dec 10, 2016 at 09:47:05PM +0100, Christoffer Dall wrote:
> We currently spend around ~400 cycles on each entry/exit to the guest
> dealing with arch timer registers, even when the timer is not pending
> and not doing anything.
>
> We can do much better by moving the arch timer save/restore to the
> vcpu_load and vcpu_put functions, but this means that if we don't read
> back the timer state on every exit from the guest, then we have to be
> able to start taking timer interrupts for the virtual timer in KVM and
> handle that properly.
>
> That has a number of funny consequences, such as having to make sure we
> don't deadlock between any of the vgic code and interrupt injection
> happening from an ISR. On the plus side, being able to inject
> virtual interrupts corresponding to a physical interrupt directly from
> an ISR is probably a good system design change.
>
> We also have to change the use of the physical vs. virtual counter in
> the arm64 kernel to avoid having to save/restore the CNTVOFF_EL2
> register on every return to the hypervisor. The only reason I could
> find for using the virtual counter for the kernel on systems with access
> to the physical counter is to detect if firmware did not properly clear
> CNTVOFF_EL2, and this change has to weighed against the existing check
> (assuming I got this right).
>
> On a non-VHE system (AMD Seattle) I have measured this to improve the
> world-switch time by about ~100 cycles, but on an EL2 kernel (emulating
> VHE behavior on the same hardware) this gives us around ~250 cycles
> worth of improvement, because we can avoid the extra configuration of
> trapping accesses to the physical timer from EL1 on every switch.
>
> I'm not sure if the benefits outweigh the complexity of this patch set,
> nor am I sure if I'm missing an overall better approach, hence the RFC
> tag on the series.
>
> I'm looking forward to overall comments on the approach.
>
FYI for anyone looking at these patches, I found some issues with the
series and will respin shortly. Patch 5 has also been split to
hopefully simplify the review, as I realized it is horrible to look at
in its current form.
Thanks,
-Christoffer
WARNING: multiple messages have this Message-ID (diff)
From: christoffer.dall@linaro.org (Christoffer Dall)
To: linux-arm-kernel@lists.infradead.org
Subject: [RFC PATCH 0/7] KVM: arm/arm64: Optimize arch timer register handling
Date: Fri, 6 Jan 2017 11:01:47 +0100 [thread overview]
Message-ID: <20170106100147.GC21089@cbox> (raw)
In-Reply-To: <20161210204712.21830-1-christoffer.dall@linaro.org>
On Sat, Dec 10, 2016 at 09:47:05PM +0100, Christoffer Dall wrote:
> We currently spend around ~400 cycles on each entry/exit to the guest
> dealing with arch timer registers, even when the timer is not pending
> and not doing anything.
>
> We can do much better by moving the arch timer save/restore to the
> vcpu_load and vcpu_put functions, but this means that if we don't read
> back the timer state on every exit from the guest, then we have to be
> able to start taking timer interrupts for the virtual timer in KVM and
> handle that properly.
>
> That has a number of funny consequences, such as having to make sure we
> don't deadlock between any of the vgic code and interrupt injection
> happening from an ISR. On the plus side, being able to inject
> virtual interrupts corresponding to a physical interrupt directly from
> an ISR is probably a good system design change.
>
> We also have to change the use of the physical vs. virtual counter in
> the arm64 kernel to avoid having to save/restore the CNTVOFF_EL2
> register on every return to the hypervisor. The only reason I could
> find for using the virtual counter for the kernel on systems with access
> to the physical counter is to detect if firmware did not properly clear
> CNTVOFF_EL2, and this change has to weighed against the existing check
> (assuming I got this right).
>
> On a non-VHE system (AMD Seattle) I have measured this to improve the
> world-switch time by about ~100 cycles, but on an EL2 kernel (emulating
> VHE behavior on the same hardware) this gives us around ~250 cycles
> worth of improvement, because we can avoid the extra configuration of
> trapping accesses to the physical timer from EL1 on every switch.
>
> I'm not sure if the benefits outweigh the complexity of this patch set,
> nor am I sure if I'm missing an overall better approach, hence the RFC
> tag on the series.
>
> I'm looking forward to overall comments on the approach.
>
FYI for anyone looking at these patches, I found some issues with the
series and will respin shortly. Patch 5 has also been split to
hopefully simplify the review, as I realized it is horrible to look at
in its current form.
Thanks,
-Christoffer
next prev parent reply other threads:[~2017-01-06 10:00 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-12-10 20:47 [RFC PATCH 0/7] KVM: arm/arm64: Optimize arch timer register handling Christoffer Dall
2016-12-10 20:47 ` Christoffer Dall
2016-12-10 20:47 ` [RFC PATCH 1/7] arm64: Use physical counter for in-kernel reads Christoffer Dall
2016-12-10 20:47 ` Christoffer Dall
2017-01-05 18:11 ` Marc Zyngier
2017-01-05 18:11 ` Marc Zyngier
2017-01-06 10:00 ` Christoffer Dall
2017-01-06 10:00 ` Christoffer Dall
2017-01-06 10:38 ` Marc Zyngier
2017-01-06 10:38 ` Marc Zyngier
2017-01-06 10:53 ` Christoffer Dall
2017-01-06 10:53 ` Christoffer Dall
2017-01-06 15:16 ` Marc Zyngier
2017-01-06 15:16 ` Marc Zyngier
2017-01-09 11:29 ` Christoffer Dall
2017-01-09 11:29 ` Christoffer Dall
2016-12-10 20:47 ` [RFC PATCH 2/7] KVM: arm/arm64: Move kvm_vgic_flush_hwstate under disabled irq Christoffer Dall
2016-12-10 20:47 ` Christoffer Dall
2016-12-10 20:47 ` [RFC PATCH 3/7] KVM: arm/arm64: Support calling vgic_update_irq_pending from irq context Christoffer Dall
2016-12-10 20:47 ` Christoffer Dall
2016-12-10 20:47 ` [RFC PATCH 4/7] KVM: arm/arm64: Check that system supports split eoi/deactivate Christoffer Dall
2016-12-10 20:47 ` Christoffer Dall
2017-01-05 17:40 ` Marc Zyngier
2017-01-05 17:40 ` Marc Zyngier
2017-01-06 10:02 ` Christoffer Dall
2017-01-06 10:02 ` Christoffer Dall
2017-01-06 10:24 ` Marc Zyngier
2017-01-06 10:24 ` Marc Zyngier
2017-01-06 10:53 ` Christoffer Dall
2017-01-06 10:53 ` Christoffer Dall
2016-12-10 20:47 ` [RFC PATCH 5/7] KVM: arm/arm64: Move timer save/restore out of hyp code where possible Christoffer Dall
2016-12-10 20:47 ` Christoffer Dall
2016-12-10 20:47 ` [RFC PATCH 6/7] KVM: arm/arm64: Remove unnecessary timer BUG_ON operations Christoffer Dall
2016-12-10 20:47 ` Christoffer Dall
2016-12-10 20:47 ` [RFC PATCH 7/7] KVM: arm/arm64: Guard kvm_vgic_map_is_active against !vgic_initialized Christoffer Dall
2016-12-10 20:47 ` Christoffer Dall
2017-01-06 10:01 ` Christoffer Dall [this message]
2017-01-06 10:01 ` [RFC PATCH 0/7] KVM: arm/arm64: Optimize arch timer register handling Christoffer Dall
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