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From: Stephen Boyd <sboyd@codeaurora.org>
To: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: linux-arm-kernel@lists.infradead.org,
	Michael Turquette <mturquette@baylibre.com>,
	Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCHv4 1/5] clk: mvebu: support for 98DX3236 SoC
Date: Fri, 20 Jan 2017 16:48:19 -0800	[thread overview]
Message-ID: <20170121004819.GA8801@codeaurora.org> (raw)
In-Reply-To: <20170113091222.7132-2-chris.packham@alliedtelesis.co.nz>

On 01/13, Chris Packham wrote:
> @@ -158,6 +170,14 @@ static const struct coreclk_soc_desc axp_coreclks = {
>  	.num_ratios = ARRAY_SIZE(axp_coreclk_ratios),
>  };
>  
> +static const struct coreclk_soc_desc mv98dx3236_coreclks = {
> +	.get_tclk_freq = mv98dx3236_get_tclk_freq,
> +	.get_cpu_freq = mv98dx3236_get_cpu_freq,
> +	.get_clk_ratio = NULL,
> +	.ratios = NULL,
> +	.num_ratios = 0,

Are these intentionally initialized to 0 explicitly? Otherwise we
could leave them out and it's all the same.

> +};
> +
>  /*
>   * Clock Gating Control
>   */
[..]
> @@ -243,5 +245,30 @@ static void __init of_cpu_clk_setup(struct device_node *node)
>  	iounmap(clock_complex_base);
>  }
>  
> +/* Use this function to call the generic setup with the correct
> + * clock operation
> + */
> +static void __init of_cpu_clk_setup(struct device_node *node)
> +{
> +	_of_cpu_clk_setup(node, &cpu_ops);
> +}
> +
>  CLK_OF_DECLARE(armada_xp_cpu_clock, "marvell,armada-xp-cpu-clock",
>  					 of_cpu_clk_setup);
> +
> +/* Define the clock and operations for the mv98dx3236 - it cannot perform
> + * any operations.
> + */
> +static const struct clk_ops mv98dx3236_cpu_ops = {
> +	.recalc_rate = NULL,
> +	.round_rate = NULL,
> +	.set_rate = NULL,

But clk_set_rate() works silently? Why not just register a clk
provider that returns a NULL pointer? Then there isn't any
structure to maintain?

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

WARNING: multiple messages have this Message-ID (diff)
From: sboyd@codeaurora.org (Stephen Boyd)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCHv4 1/5] clk: mvebu: support for 98DX3236 SoC
Date: Fri, 20 Jan 2017 16:48:19 -0800	[thread overview]
Message-ID: <20170121004819.GA8801@codeaurora.org> (raw)
In-Reply-To: <20170113091222.7132-2-chris.packham@alliedtelesis.co.nz>

On 01/13, Chris Packham wrote:
> @@ -158,6 +170,14 @@ static const struct coreclk_soc_desc axp_coreclks = {
>  	.num_ratios = ARRAY_SIZE(axp_coreclk_ratios),
>  };
>  
> +static const struct coreclk_soc_desc mv98dx3236_coreclks = {
> +	.get_tclk_freq = mv98dx3236_get_tclk_freq,
> +	.get_cpu_freq = mv98dx3236_get_cpu_freq,
> +	.get_clk_ratio = NULL,
> +	.ratios = NULL,
> +	.num_ratios = 0,

Are these intentionally initialized to 0 explicitly? Otherwise we
could leave them out and it's all the same.

> +};
> +
>  /*
>   * Clock Gating Control
>   */
[..]
> @@ -243,5 +245,30 @@ static void __init of_cpu_clk_setup(struct device_node *node)
>  	iounmap(clock_complex_base);
>  }
>  
> +/* Use this function to call the generic setup with the correct
> + * clock operation
> + */
> +static void __init of_cpu_clk_setup(struct device_node *node)
> +{
> +	_of_cpu_clk_setup(node, &cpu_ops);
> +}
> +
>  CLK_OF_DECLARE(armada_xp_cpu_clock, "marvell,armada-xp-cpu-clock",
>  					 of_cpu_clk_setup);
> +
> +/* Define the clock and operations for the mv98dx3236 - it cannot perform
> + * any operations.
> + */
> +static const struct clk_ops mv98dx3236_cpu_ops = {
> +	.recalc_rate = NULL,
> +	.round_rate = NULL,
> +	.set_rate = NULL,

But clk_set_rate() works silently? Why not just register a clk
provider that returns a NULL pointer? Then there isn't any
structure to maintain?

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

WARNING: multiple messages have this Message-ID (diff)
From: Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
To: Chris Packham
	<chris.packham-6g8wRflRTwXFdCa3tKVlE6U/zSkkHjvu@public.gmane.org>
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	Michael Turquette
	<mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>,
	Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
	Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
	linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCHv4 1/5] clk: mvebu: support for 98DX3236 SoC
Date: Fri, 20 Jan 2017 16:48:19 -0800	[thread overview]
Message-ID: <20170121004819.GA8801@codeaurora.org> (raw)
In-Reply-To: <20170113091222.7132-2-chris.packham-6g8wRflRTwXFdCa3tKVlE6U/zSkkHjvu@public.gmane.org>

On 01/13, Chris Packham wrote:
> @@ -158,6 +170,14 @@ static const struct coreclk_soc_desc axp_coreclks = {
>  	.num_ratios = ARRAY_SIZE(axp_coreclk_ratios),
>  };
>  
> +static const struct coreclk_soc_desc mv98dx3236_coreclks = {
> +	.get_tclk_freq = mv98dx3236_get_tclk_freq,
> +	.get_cpu_freq = mv98dx3236_get_cpu_freq,
> +	.get_clk_ratio = NULL,
> +	.ratios = NULL,
> +	.num_ratios = 0,

Are these intentionally initialized to 0 explicitly? Otherwise we
could leave them out and it's all the same.

> +};
> +
>  /*
>   * Clock Gating Control
>   */
[..]
> @@ -243,5 +245,30 @@ static void __init of_cpu_clk_setup(struct device_node *node)
>  	iounmap(clock_complex_base);
>  }
>  
> +/* Use this function to call the generic setup with the correct
> + * clock operation
> + */
> +static void __init of_cpu_clk_setup(struct device_node *node)
> +{
> +	_of_cpu_clk_setup(node, &cpu_ops);
> +}
> +
>  CLK_OF_DECLARE(armada_xp_cpu_clock, "marvell,armada-xp-cpu-clock",
>  					 of_cpu_clk_setup);
> +
> +/* Define the clock and operations for the mv98dx3236 - it cannot perform
> + * any operations.
> + */
> +static const struct clk_ops mv98dx3236_cpu_ops = {
> +	.recalc_rate = NULL,
> +	.round_rate = NULL,
> +	.set_rate = NULL,

But clk_set_rate() works silently? Why not just register a clk
provider that returns a NULL pointer? Then there isn't any
structure to maintain?

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
--
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  parent reply	other threads:[~2017-01-21  0:48 UTC|newest]

Thread overview: 62+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-01-13  9:12 [PATCHv4 0/5] Support for Marvell switches with integrated CPUs Chris Packham
2017-01-13  9:12 ` Chris Packham
2017-01-13  9:12 ` Chris Packham
2017-01-13  9:12 ` [PATCHv4 1/5] clk: mvebu: support for 98DX3236 SoC Chris Packham
2017-01-13  9:12   ` Chris Packham
2017-01-18 22:25   ` Rob Herring
2017-01-18 22:25     ` Rob Herring
2017-01-19  3:24     ` Chris Packham
2017-01-19  3:24       ` Chris Packham
2017-01-19  3:24       ` Chris Packham
2017-01-19  3:24       ` Chris Packham
2017-01-21  0:48   ` Stephen Boyd [this message]
2017-01-21  0:48     ` Stephen Boyd
2017-01-21  0:48     ` Stephen Boyd
2017-01-23  7:53     ` Chris Packham
2017-01-23  7:53       ` Chris Packham
2017-01-23  7:53       ` Chris Packham
2017-01-23  7:53       ` Chris Packham
2017-01-23 23:53       ` Stephen Boyd
2017-01-23 23:53         ` Stephen Boyd
2017-01-13  9:12 ` [PATCHv4 2/5] arm: mvebu: support for SMP on 98DX3336 SoC Chris Packham
2017-01-13  9:12   ` Chris Packham
2017-01-13  9:12   ` Chris Packham
2017-01-19  0:47   ` Stephen Boyd
2017-01-19  0:47     ` Stephen Boyd
2017-01-19  3:23     ` Chris Packham
2017-01-19  3:23       ` Chris Packham
2017-01-19  3:23       ` Chris Packham
2017-01-13  9:12 ` [PATCHv4 3/5] pinctrl: mvebu: pinctrl driver for 98DX3236 SoC Chris Packham
2017-01-13  9:12   ` Chris Packham
2017-01-13  9:12   ` Chris Packham
2017-01-13  9:54   ` Sebastian Hesselbarth
2017-01-13  9:54     ` Sebastian Hesselbarth
2017-01-13  9:54     ` Sebastian Hesselbarth
2017-01-14  7:50     ` Chris Packham
2017-01-14  7:50       ` Chris Packham
2017-01-19 21:12       ` Chris Packham
2017-01-19 21:12         ` Chris Packham
2017-01-19 21:12         ` Chris Packham
     [not found]         ` <66c205acea6046978bf17e6d8fc1959f-5g7mGxlPNYb6GjIOKuZY+ItlCAj8ZROq@public.gmane.org>
2017-01-19 23:19           ` Sebastian Hesselbarth
2017-01-19 23:19             ` Sebastian Hesselbarth
2017-01-19 23:19             ` Sebastian Hesselbarth
2017-01-19 23:36             ` Chris Packham
2017-01-19 23:36               ` Chris Packham
2017-01-19 23:36               ` Chris Packham
     [not found]   ` <20170113091222.7132-4-chris.packham-6g8wRflRTwXFdCa3tKVlE6U/zSkkHjvu@public.gmane.org>
2017-01-19 10:02     ` Russell King - ARM Linux
2017-01-19 10:02       ` Russell King - ARM Linux
2017-01-19 10:02       ` Russell King - ARM Linux
2017-01-19 21:10       ` Chris Packham
2017-01-19 21:10         ` Chris Packham
2017-01-23  8:18         ` Chris Packham
2017-01-23  8:18           ` Chris Packham
2017-01-23  8:18           ` Chris Packham
2017-01-26 14:11           ` Linus Walleij
2017-01-26 14:11             ` Linus Walleij
2017-01-13  9:12 ` [PATCHv4 4/5] arm: mvebu: Add device tree for 98DX3236 SoCs Chris Packham
2017-01-13  9:12   ` Chris Packham
2017-01-13  9:12 ` [PATCHv4 5/5] arm: mvebu: Add device tree for db-dxbc2 and db-xc3-24g4xg boards Chris Packham
2017-01-13  9:12   ` Chris Packham
2017-01-26 15:17 ` [PATCHv4 0/5] Support for Marvell switches with integrated CPUs Gregory CLEMENT
2017-01-26 15:17   ` Gregory CLEMENT
2017-01-26 15:17   ` Gregory CLEMENT

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