[Qemu-devel] [RFC] Pointers for implementing AArch64 PMU instruction counter?

[Aaron Lindsay <alindsay@codeaurora.org>]

I am interested in implementing an instruction counter to augment the
ongoing (mostly cycle-counter) PMU work on AArch64. The icount
infrastructure seems like the logical source for the instruction counts,
but I have a couple of implementation-related questions:

1. It looks like cpu_get_icount_raw() can serve as a good source for
directly reading the current instruction count. Does it seem reasonable
to only enable the instruction counter in the PMU when icount is enabled
and are there any caveats I've missed with using icount for this
purpose?

2. Triggering interrupts on overflow seems like it will take more work.
Does it seem reasonable to add a QEMU_CLOCK_VIRTUAL for the PMU so that
tcg_get_icount_limit() will overflow at the appropriate time for the PMU
if an instruction counter overflow interrupt is set? TBH, I'm not sure
how well this would work since the timer code mostly seems to deal with
time (as you might expect), keeping the icount values somewhat hidden
away.

Thanks for any feedback!

-Aaron

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