From: Stephen Boyd <sboyd@codeaurora.org>
To: Heiko Stuebner <heiko@sntech.de>
Cc: linux-rockchip@lists.infradead.org,
linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org,
mturquette@baylibre.com
Subject: Re: [PATCH 0/4] rockchip: fix serial output on rk3036
Date: Mon, 27 Feb 2017 23:32:40 -0800 [thread overview]
Message-ID: <20170228073240.GJ25384@codeaurora.org> (raw)
In-Reply-To: <20170228051420.7214-1-heiko@sntech.de>
On 02/28, Heiko Stuebner wrote:
> Recent changes to the 8250-dw variant revealed issues concerning
> how the clock rates are handled on the rk3036 uart.
>
> For one, there was an error in the clock declaration, but also the
> shared uart-pll-select-mux also as default got supplied from the apll
> that also supplies the cpu and thus gets frequency scaled.
>
> The patches in this series remedy this and make the debug uart
> function again on 4.10 + current merge window.
>
What's the merge path? The last patch is sort of questionable
because it fixes a regression by changing assigned clocks in DT,
which doesn't really make sense from a DT perspective (it should
have been right already or can be configured from the clk driver
itself in software).
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
WARNING: multiple messages have this Message-ID (diff)
From: Stephen Boyd <sboyd@codeaurora.org>
To: Heiko Stuebner <heiko@sntech.de>
Cc: linux-rockchip@lists.infradead.org, mturquette@baylibre.com,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 0/4] rockchip: fix serial output on rk3036
Date: Mon, 27 Feb 2017 23:32:40 -0800 [thread overview]
Message-ID: <20170228073240.GJ25384@codeaurora.org> (raw)
In-Reply-To: <20170228051420.7214-1-heiko@sntech.de>
On 02/28, Heiko Stuebner wrote:
> Recent changes to the 8250-dw variant revealed issues concerning
> how the clock rates are handled on the rk3036 uart.
>
> For one, there was an error in the clock declaration, but also the
> shared uart-pll-select-mux also as default got supplied from the apll
> that also supplies the cpu and thus gets frequency scaled.
>
> The patches in this series remedy this and make the debug uart
> function again on 4.10 + current merge window.
>
What's the merge path? The last patch is sort of questionable
because it fixes a regression by changing assigned clocks in DT,
which doesn't really make sense from a DT perspective (it should
have been right already or can be configured from the clk driver
itself in software).
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
WARNING: multiple messages have this Message-ID (diff)
From: sboyd@codeaurora.org (Stephen Boyd)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 0/4] rockchip: fix serial output on rk3036
Date: Mon, 27 Feb 2017 23:32:40 -0800 [thread overview]
Message-ID: <20170228073240.GJ25384@codeaurora.org> (raw)
In-Reply-To: <20170228051420.7214-1-heiko@sntech.de>
On 02/28, Heiko Stuebner wrote:
> Recent changes to the 8250-dw variant revealed issues concerning
> how the clock rates are handled on the rk3036 uart.
>
> For one, there was an error in the clock declaration, but also the
> shared uart-pll-select-mux also as default got supplied from the apll
> that also supplies the cpu and thus gets frequency scaled.
>
> The patches in this series remedy this and make the debug uart
> function again on 4.10 + current merge window.
>
What's the merge path? The last patch is sort of questionable
because it fixes a regression by changing assigned clocks in DT,
which doesn't really make sense from a DT perspective (it should
have been right already or can be configured from the clk driver
itself in software).
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2017-02-28 7:32 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-28 5:14 [PATCH 0/4] rockchip: fix serial output on rk3036 Heiko Stuebner
2017-02-28 5:14 ` Heiko Stuebner
2017-02-28 5:14 ` Heiko Stuebner
2017-02-28 5:14 ` [PATCH 1/4] clk: rockchip: add "," to mux_pll_src_apll_dpll_gpll_usb480m_p " Heiko Stuebner
2017-02-28 5:14 ` [PATCH 1/4] clk: rockchip: add ", " " Heiko Stuebner
2017-02-28 5:14 ` Heiko Stuebner
2017-02-28 7:33 ` [PATCH 1/4] clk: rockchip: add "," " Stephen Boyd
2017-02-28 7:33 ` Stephen Boyd
2017-02-28 7:33 ` Stephen Boyd
2017-02-28 5:14 ` [PATCH 2/4] clk: rockchip: add SCLK_UARTPLL to rk3036 clock ids Heiko Stuebner
2017-02-28 5:14 ` Heiko Stuebner
2017-02-28 5:14 ` Heiko Stuebner
2017-02-28 5:14 ` [PATCH 3/4] clk: rockchip: assign the SCLK_UARTPLL clock id on rk3036 Heiko Stuebner
2017-02-28 5:14 ` Heiko Stuebner
2017-02-28 5:14 ` Heiko Stuebner
2017-02-28 5:14 ` [PATCH 4/4] ARM: dts: rockchip: Make uartpll a child of the gpll " Heiko Stuebner
2017-02-28 5:14 ` Heiko Stuebner
2017-02-28 5:14 ` Heiko Stuebner
2017-02-28 7:32 ` Stephen Boyd [this message]
2017-02-28 7:32 ` [PATCH 0/4] rockchip: fix serial output " Stephen Boyd
2017-02-28 7:32 ` Stephen Boyd
2017-02-28 17:25 ` Heiko Stuebner
2017-02-28 17:25 ` Heiko Stuebner
2017-02-28 17:25 ` Heiko Stuebner
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