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From: Stephen Boyd <sboyd@codeaurora.org>
To: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Chen-Yu Tsai <wens@csie.org>,
	Michael Turquette <mturquette@baylibre.com>,
	linux-clk <linux-clk@vger.kernel.org>,
	linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
	linux-kernel <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 4/5] clk: sunxi-ng: Add driver for A83T CCU
Date: Wed, 1 Mar 2017 11:17:05 -0800	[thread overview]
Message-ID: <20170301191705.GS25384@codeaurora.org> (raw)
In-Reply-To: <20170215094954.h3wyaxlqkeb342yu@lukather>

On 02/15, Maxime Ripard wrote:
> On Tue, Feb 14, 2017 at 06:26:39PM +0800, Chen-Yu Tsai wrote:
> > On Tue, Feb 14, 2017 at 5:58 PM, Maxime Ripard
> > <maxime.ripard@free-electrons.com> wrote:
> > > On Tue, Feb 14, 2017 at 11:35:25AM +0800, Chen-Yu Tsai wrote:
> > >> +/*
> > >> + * MMC2 supports what's called the "new timing mode". The CCU and the MMC
> > >> + * controller must be in sync about which mode is used. The new mode moves
> > >> + * the clock delay controls (and possibly the delay lines) into the MMC
> > >> + * block. Also, the output of the clock is divided by 2. The output and
> > >> + * sample phase clocks are unused under this mode.
> > >> + *
> > >> + * This new mode seems to be preferred. Hence we force this clock to the
> > >> + * new mode. And we don't add the phase clocks.
> > >> + */
> > >
> > > I'm sorry, but I said this several times, this isn't working. We
> > > should model it properly, and not hack this around in the clock
> > > driver.
> > >
> > > As you say in your comment, the MMC driver needs to be aware about
> > > which mode is used, in order to also set a bit in one of its registers
> > > accordingly, and modify its sampling behaviour.
> > >
> > > The new timing is preferred, but our previous clock implementations
> > > didn't hardcode it, so we can't even rely on that behaviour to always
> > > write it in our driver.
> > 
> > Correct. With the A83T there has never been a merged clock driver though.
> > I realize this is a one off thing.
> > 
> > > This is not something specific to the A83T, but is found in all the
> > > SoCs since the A23, so we need to come up with a good solution to
> > > address that.
> > >
> > > I'm not sure what a good solution would be though. One would be to
> > > just have a private function of our own to switch in the new mode (if
> > > relevant, because only the MMC2 controllers have it), but that would
> > > lead to troubles with !sunxi-ng. Not something we can't deal with, but
> > > some extra precautions should be taken (make sure to protect the call
> > > through an ifdef / IS_DEFINED, check that the sunxi-ng driver has been
> > > probed, etc.)
> > 
> > If the custom function route is acceptable, I'll come up with something.
> 
> I think it would be a great start yes. I'll try to discuss it with
> Mike and Stephen at ELC and see what they think about that.
> 

I didn't hear anything at ELC. Can someone explain what the issue
is? Could something like clk_get_phase() + clk_get_rate() tell us
if we're in one mode vs. the other?

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

WARNING: multiple messages have this Message-ID (diff)
From: sboyd@codeaurora.org (Stephen Boyd)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 4/5] clk: sunxi-ng: Add driver for A83T CCU
Date: Wed, 1 Mar 2017 11:17:05 -0800	[thread overview]
Message-ID: <20170301191705.GS25384@codeaurora.org> (raw)
In-Reply-To: <20170215094954.h3wyaxlqkeb342yu@lukather>

On 02/15, Maxime Ripard wrote:
> On Tue, Feb 14, 2017 at 06:26:39PM +0800, Chen-Yu Tsai wrote:
> > On Tue, Feb 14, 2017 at 5:58 PM, Maxime Ripard
> > <maxime.ripard@free-electrons.com> wrote:
> > > On Tue, Feb 14, 2017 at 11:35:25AM +0800, Chen-Yu Tsai wrote:
> > >> +/*
> > >> + * MMC2 supports what's called the "new timing mode". The CCU and the MMC
> > >> + * controller must be in sync about which mode is used. The new mode moves
> > >> + * the clock delay controls (and possibly the delay lines) into the MMC
> > >> + * block. Also, the output of the clock is divided by 2. The output and
> > >> + * sample phase clocks are unused under this mode.
> > >> + *
> > >> + * This new mode seems to be preferred. Hence we force this clock to the
> > >> + * new mode. And we don't add the phase clocks.
> > >> + */
> > >
> > > I'm sorry, but I said this several times, this isn't working. We
> > > should model it properly, and not hack this around in the clock
> > > driver.
> > >
> > > As you say in your comment, the MMC driver needs to be aware about
> > > which mode is used, in order to also set a bit in one of its registers
> > > accordingly, and modify its sampling behaviour.
> > >
> > > The new timing is preferred, but our previous clock implementations
> > > didn't hardcode it, so we can't even rely on that behaviour to always
> > > write it in our driver.
> > 
> > Correct. With the A83T there has never been a merged clock driver though.
> > I realize this is a one off thing.
> > 
> > > This is not something specific to the A83T, but is found in all the
> > > SoCs since the A23, so we need to come up with a good solution to
> > > address that.
> > >
> > > I'm not sure what a good solution would be though. One would be to
> > > just have a private function of our own to switch in the new mode (if
> > > relevant, because only the MMC2 controllers have it), but that would
> > > lead to troubles with !sunxi-ng. Not something we can't deal with, but
> > > some extra precautions should be taken (make sure to protect the call
> > > through an ifdef / IS_DEFINED, check that the sunxi-ng driver has been
> > > probed, etc.)
> > 
> > If the custom function route is acceptable, I'll come up with something.
> 
> I think it would be a great start yes. I'll try to discuss it with
> Mike and Stephen at ELC and see what they think about that.
> 

I didn't hear anything at ELC. Can someone explain what the issue
is? Could something like clk_get_phase() + clk_get_rate() tell us
if we're in one mode vs. the other?

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

  reply	other threads:[~2017-03-01 19:17 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-02-14  3:35 [PATCH 0/5] clk: sunxi-ng: Add support for A83T CCU Chen-Yu Tsai
2017-02-14  3:35 ` Chen-Yu Tsai
2017-02-14  3:35 ` [PATCH 1/5] clk: sunxi-ng: mp: Adjust parent rate for pre-dividers Chen-Yu Tsai
2017-02-14  3:35   ` Chen-Yu Tsai
2017-02-14  9:34   ` Maxime Ripard
2017-02-14  9:34     ` Maxime Ripard
2017-02-14  3:35 ` [PATCH 2/5] clk: sunxi-ng: gate: Support common pre-dividers Chen-Yu Tsai
2017-02-14  3:35   ` Chen-Yu Tsai
2017-02-14  9:39   ` Maxime Ripard
2017-02-14  9:39     ` Maxime Ripard
2017-02-14  3:35 ` [PATCH 3/5] clk: sunxi-ng: Add compatible string for A83T CCU to bindings Chen-Yu Tsai
2017-02-14  3:35   ` Chen-Yu Tsai
2017-02-14  3:35 ` [PATCH 4/5] clk: sunxi-ng: Add driver for A83T CCU Chen-Yu Tsai
2017-02-14  3:35   ` Chen-Yu Tsai
2017-02-14  9:58   ` Maxime Ripard
2017-02-14  9:58     ` Maxime Ripard
2017-02-14 10:26     ` Chen-Yu Tsai
2017-02-14 10:26       ` Chen-Yu Tsai
2017-02-15  9:49       ` Maxime Ripard
2017-02-15  9:49         ` Maxime Ripard
2017-03-01 19:17         ` Stephen Boyd [this message]
2017-03-01 19:17           ` Stephen Boyd
2017-03-03  9:53           ` Maxime Ripard
2017-03-03  9:53             ` Maxime Ripard
2017-03-03 23:56             ` Stephen Boyd
2017-03-03 23:56               ` Stephen Boyd
2017-03-07 14:58               ` Maxime Ripard
2017-03-07 14:58                 ` Maxime Ripard
2017-03-22  6:50         ` Chen-Yu Tsai
2017-03-22  6:50           ` Chen-Yu Tsai
2017-03-26 20:51           ` Maxime Ripard
2017-03-26 20:51             ` Maxime Ripard
2017-03-27  8:53             ` Chen-Yu Tsai
2017-03-27  8:53               ` Chen-Yu Tsai
2017-04-03  7:53               ` Maxime Ripard
2017-04-03  7:53                 ` Maxime Ripard
2017-02-14  3:35 ` [PATCH 5/5] ARM: dts: sun8i-a83t: Add CCU device nodes Chen-Yu Tsai
2017-02-14  3:35   ` Chen-Yu Tsai

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