From: Yi Sun <yi.y.sun@linux.intel.com>
To: Jan Beulich <JBeulich@suse.com>
Cc: kevin.tian@intel.com, wei.liu2@citrix.com,
he.chen@linux.intel.com, andrew.cooper3@citrix.com,
dario.faggioli@citrix.com, ian.jackson@eu.citrix.com,
mengxu@cis.upenn.edu, xen-devel@lists.xenproject.org,
chao.p.peng@linux.intel.com
Subject: Re: [PATCH v8 08/24] x86: refactor psr: set value: implement framework.
Date: Wed, 15 Mar 2017 16:18:37 +0800 [thread overview]
Message-ID: <20170315081837.GV17458@yi.y.sun> (raw)
In-Reply-To: <58C8FDE60200007800143266@prv-mh.provo.novell.com>
On 17-03-15 01:40:06, Jan Beulich wrote:
> >>> On 15.03.17 at 03:52, <yi.y.sun@linux.intel.com> wrote:
> > Sorry, I may not fully understand your meaning. My thoughts are below.
> > 1. We set 'd->arch.psr_cos_ids[socket] = cos;' in 'psr_set_val';
> >
> > 2. After that, we get valid cpumask through cpupool_domain_cpumask();
> >
> > 3. If the actual valid cpumask changed after that, the new cpu is valid so
> > that the context switch happens. Then 'psr_ctxt_switch_to' is called to
> > update the new cpu's ASSOC register with the new COS ID which has been
> > set in step 1.
> >
> > 4. Send IPI to all cpus on cpumask got in step 2. They will update their
> > ASSOC registers according to their domains psr_cos_ids[].
> >
> > So I think this flow can cover all cpus which ASSOC registers need be
> > updated.
>
> You writing it down this way makes me realize that the IPI approach
> can't work this way at all: It leaves a time window (between 1 and 2)
> where the domain may have vCPU-s running with the wrong COS ID.
> I think pausing the vCPU is unavoidable, unless it can be explained
> that running with the wrong COS ID for a brief period of time is not
> really a problem. I do realize that the pausing approach has its own
> difficulty wrt Dom0, but I think that's solvable (e.g. by doing the
> actual work in a tasklet instead of in the context of a Dom0 vCPU).
>
I have below thoughts.
1. We can use domain_pause for all domains except Dom0 to update COS ID.
2. PSR features are to set cache capacity for a domain. The setting to
cache is progressively effective. When the cache setting becomes really
effective, the time slice to schedule a domain may have passed. Moreover,
even a wrong COS ID is used to set ASSOC, only another CBM be effective
for a short time. In next Dom0 schedule, the correct CBM will take effect.
So can we just leave Dom0 setting as current implementation?
Thanks,
Sun Yi
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next prev parent reply other threads:[~2017-03-15 8:18 UTC|newest]
Thread overview: 122+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-15 8:49 [PATCH v8 00/24] Enable L2 Cache Allocation Technology & Refactor psr.c Yi Sun
2017-02-15 8:49 ` [PATCH v8 01/24] docs: create Cache Allocation Technology (CAT) and Code and Data Prioritization (CDP) feature document Yi Sun
2017-02-15 16:49 ` Konrad Rzeszutek Wilk
2017-02-26 17:40 ` Wei Liu
2017-02-15 8:49 ` [PATCH v8 02/24] x86: refactor psr: remove L3 CAT/CDP codes Yi Sun
2017-02-26 17:40 ` Wei Liu
2017-02-15 8:49 ` [PATCH v8 03/24] x86: refactor psr: implement main data structures Yi Sun
2017-02-28 11:58 ` Roger Pau Monné
2017-03-01 5:10 ` Yi Sun
2017-03-01 8:17 ` Jan Beulich
2017-03-01 8:28 ` Yi Sun
2017-03-01 8:39 ` Jan Beulich
2017-03-01 8:49 ` Roger Pau Monn�
2017-03-01 8:54 ` Jan Beulich
2017-03-01 9:00 ` Roger Pau Monn�
2017-02-15 8:49 ` [PATCH v8 04/24] x86: refactor psr: implement CPU init and free flow Yi Sun
2017-02-26 17:41 ` Wei Liu
2017-02-27 6:42 ` Yi Sun
2017-02-27 11:45 ` Wei Liu
2017-02-27 8:41 ` Jan Beulich
2017-03-08 14:56 ` Jan Beulich
2017-03-10 1:32 ` Yi Sun
2017-03-10 8:56 ` Jan Beulich
2017-03-13 2:18 ` Yi Sun
2017-02-15 8:49 ` [PATCH v8 05/24] x86: refactor psr: implement Domain init/free and schedule flows Yi Sun
2017-02-26 17:41 ` Wei Liu
2017-03-08 15:04 ` Jan Beulich
2017-02-15 8:49 ` [PATCH v8 06/24] x86: refactor psr: implement get hw info flow Yi Sun
2017-02-26 17:41 ` Wei Liu
2017-02-28 12:34 ` Roger Pau Monné
2017-03-08 15:15 ` Jan Beulich
2017-03-10 1:43 ` Yi Sun
2017-03-10 8:57 ` Jan Beulich
2017-03-10 9:01 ` Yi Sun
2017-02-15 8:49 ` [PATCH v8 07/24] x86: refactor psr: implement get value flow Yi Sun
2017-02-28 12:44 ` Roger Pau Monné
2017-03-01 5:21 ` Yi Sun
2017-03-08 15:35 ` Jan Beulich
2017-03-10 1:50 ` Yi Sun
2017-03-10 9:05 ` Jan Beulich
2017-02-15 8:49 ` [PATCH v8 08/24] x86: refactor psr: set value: implement framework Yi Sun
2017-02-26 17:41 ` Wei Liu
2017-02-27 7:06 ` Yi Sun
2017-02-27 10:55 ` Jan Beulich
2017-02-28 13:58 ` Roger Pau Monné
2017-03-01 6:23 ` Yi Sun
2017-03-08 16:07 ` Jan Beulich
2017-03-10 2:54 ` Yi Sun
2017-03-10 9:09 ` Jan Beulich
2017-03-13 2:36 ` Yi Sun
2017-03-13 12:35 ` Jan Beulich
2017-03-14 2:43 ` Yi Sun
2017-03-14 6:29 ` Jan Beulich
2017-03-14 9:21 ` Yi Sun
2017-03-14 10:24 ` Jan Beulich
2017-03-15 2:52 ` Yi Sun
2017-03-15 7:40 ` Jan Beulich
2017-03-15 8:18 ` Yi Sun [this message]
2017-03-15 8:32 ` Jan Beulich
2017-03-10 7:46 ` Yi Sun
2017-03-10 9:10 ` Jan Beulich
2017-02-15 8:49 ` [PATCH v8 09/24] x86: refactor psr: set value: assemble features value array Yi Sun
2017-02-26 17:43 ` Wei Liu
2017-02-27 7:11 ` Yi Sun
2017-02-27 11:45 ` Wei Liu
2017-03-08 16:54 ` Jan Beulich
2017-03-10 3:21 ` Yi Sun
2017-03-10 9:15 ` Jan Beulich
2017-03-13 2:43 ` Yi Sun
2017-03-13 12:37 ` Jan Beulich
2017-03-14 2:20 ` Yi Sun
2017-03-14 6:32 ` Jan Beulich
2017-02-15 8:49 ` [PATCH v8 10/24] x86: refactor psr: set value: implement cos finding flow Yi Sun
2017-02-26 17:43 ` Wei Liu
2017-02-27 7:16 ` Yi Sun
2017-03-08 17:03 ` Jan Beulich
2017-03-10 5:35 ` Yi Sun
2017-03-10 9:21 ` Jan Beulich
2017-02-15 8:49 ` [PATCH v8 11/24] x86: refactor psr: set value: implement cos id picking flow Yi Sun
2017-02-26 17:43 ` Wei Liu
2017-03-09 14:10 ` Jan Beulich
2017-03-10 5:40 ` Yi Sun
2017-03-10 9:24 ` Jan Beulich
2017-02-15 8:49 ` [PATCH v8 12/24] x86: refactor psr: set value: implement write msr flow Yi Sun
2017-02-15 8:49 ` [PATCH v8 13/24] x86: refactor psr: implement CPU init and free flow for CDP Yi Sun
2017-02-28 14:52 ` Roger Pau Monné
2017-03-09 14:53 ` Jan Beulich
2017-03-10 5:50 ` Yi Sun
2017-02-15 8:49 ` [PATCH v8 14/24] x86: refactor psr: implement get hw info " Yi Sun
2017-02-26 17:43 ` Wei Liu
2017-02-28 14:54 ` Roger Pau Monné
2017-02-15 8:49 ` [PATCH v8 15/24] x86: refactor psr: implement get value " Yi Sun
2017-02-28 14:59 ` Roger Pau Monné
2017-02-15 8:49 ` [PATCH v8 16/24] x86: refactor psr: implement set value callback functions " Yi Sun
2017-02-26 17:43 ` Wei Liu
2017-02-27 7:19 ` Yi Sun
2017-02-15 8:49 ` [PATCH v8 17/24] x86: L2 CAT: implement CPU init and free flow Yi Sun
2017-02-28 15:15 ` Roger Pau Monné
2017-03-01 6:35 ` Yi Sun
2017-03-09 15:04 ` Jan Beulich
2017-03-10 5:52 ` Yi Sun
2017-02-15 8:49 ` [PATCH v8 18/24] x86: L2 CAT: implement get hw info flow Yi Sun
2017-02-28 15:18 ` Roger Pau Monné
2017-03-09 15:13 ` Jan Beulich
2017-03-10 5:57 ` Yi Sun
2017-03-10 9:26 ` Jan Beulich
2017-02-15 8:49 ` [PATCH v8 19/24] x86: L2 CAT: implement get value flow Yi Sun
2017-02-28 15:20 ` Roger Pau Monné
2017-02-15 8:49 ` [PATCH v8 20/24] x86: L2 CAT: implement set " Yi Sun
2017-02-28 15:25 ` Roger Pau Monné
2017-03-01 6:59 ` Yi Sun
2017-03-01 11:31 ` Dario Faggioli
2017-02-15 8:49 ` [PATCH v8 21/24] tools: L2 CAT: support get HW info for L2 CAT Yi Sun
2017-02-15 8:49 ` [PATCH v8 22/24] tools: L2 CAT: support show cbm " Yi Sun
2017-02-15 8:49 ` [PATCH v8 23/24] tools: L2 CAT: support set " Yi Sun
2017-02-15 8:49 ` [PATCH v8 24/24] docs: add L2 CAT description in docs Yi Sun
2017-02-15 16:14 ` [PATCH v8 00/24] Enable L2 Cache Allocation Technology & Refactor psr.c Konrad Rzeszutek Wilk
2017-02-26 18:00 ` Wei Liu
2017-02-28 11:02 ` Roger Pau Monné
2017-03-01 4:54 ` Yi Sun
2017-03-01 8:35 ` Roger Pau Monn�
2017-03-01 8:40 ` Yi Sun
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