* [PATCH 0/2] STM32F4 clock fixes @ 2017-03-15 14:27 ` gabriel.fernandez at st.com 0 siblings, 0 replies; 10+ messages in thread From: gabriel.fernandez @ 2017-03-15 14:27 UTC (permalink / raw) To: Michael Turquette, Stephen Boyd, Maxime Coquelin, Alexandre Torgue, Nicolas Pitre, Arnd Bergmann, daniel.thompson, andrea.merello, radoslaw.pietrzyk Cc: linux-clk, linux-arm-kernel, linux-kernel, gabriel.fernandez From: Gabriel Fernandez <gabriel.fernandez@st.com> This patch-set contains 2 fixes. One concerning exclusion of wrong values for PLLQ (0 & 1) And the second is a fix about timeout management of PLL and LSE/LSI clocks. Gabriel Fernandez (2): clk: stm32f4: fix: exclude values 0 and 1 for PLLQ clk: stm32f4: fix timeout management for pll and ready gate drivers/clk/clk-stm32f4.c | 56 +++++++++++++++++++++++++++++++++-------------- 1 file changed, 39 insertions(+), 17 deletions(-) -- 1.9.1 ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 0/2] STM32F4 clock fixes @ 2017-03-15 14:27 ` gabriel.fernandez at st.com 0 siblings, 0 replies; 10+ messages in thread From: gabriel.fernandez at st.com @ 2017-03-15 14:27 UTC (permalink / raw) To: linux-arm-kernel From: Gabriel Fernandez <gabriel.fernandez@st.com> This patch-set contains 2 fixes. One concerning exclusion of wrong values for PLLQ (0 & 1) And the second is a fix about timeout management of PLL and LSE/LSI clocks. Gabriel Fernandez (2): clk: stm32f4: fix: exclude values 0 and 1 for PLLQ clk: stm32f4: fix timeout management for pll and ready gate drivers/clk/clk-stm32f4.c | 56 +++++++++++++++++++++++++++++++++-------------- 1 file changed, 39 insertions(+), 17 deletions(-) -- 1.9.1 ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 1/2] clk: stm32f4: fix: exclude values 0 and 1 for PLLQ 2017-03-15 14:27 ` gabriel.fernandez at st.com @ 2017-03-15 14:27 ` gabriel.fernandez at st.com -1 siblings, 0 replies; 10+ messages in thread From: gabriel.fernandez @ 2017-03-15 14:27 UTC (permalink / raw) To: Michael Turquette, Stephen Boyd, Maxime Coquelin, Alexandre Torgue, Nicolas Pitre, Arnd Bergmann, daniel.thompson, andrea.merello, radoslaw.pietrzyk Cc: linux-clk, linux-arm-kernel, linux-kernel, gabriel.fernandez From: Gabriel Fernandez <gabriel.fernandez@st.com> 0000: PLLQ = 0, wrong configuration 0001: PLLQ = 1, wrong configuration ... 0010: PLLQ = 2 0011: PLLQ = 3 0100: PLLQ = 4 ... 1111: PLLQ = 1 Use divider table to exclude 0 and 1 values. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> --- drivers/clk/clk-stm32f4.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c index ab609a7..cf9449b3 100644 --- a/drivers/clk/clk-stm32f4.c +++ b/drivers/clk/clk-stm32f4.c @@ -429,6 +429,13 @@ enum { { 0, 2 }, { 1, 4 }, { 2, 6 }, { 3, 8 }, { 0 } }; +static const struct clk_div_table pll_divq_table[] = { + { 2, 2 }, { 3, 3 }, { 4, 4 }, { 5, 5 }, { 6, 6 }, { 7, 7 }, + { 8, 8 }, { 9, 9 }, { 10, 10 }, { 11, 11 }, { 12, 12 }, { 13, 13 }, + { 14, 14 }, { 15, 15 }, + { 0 } +}; + static const struct clk_div_table pll_divr_table[] = { { 2, 2 }, { 3, 3 }, { 4, 4 }, { 5, 5 }, { 6, 6 }, { 7, 7 }, { 0 } }; @@ -496,9 +503,9 @@ struct stm32f4_div_data { #define MAX_PLL_DIV 3 static const struct stm32f4_div_data div_data[MAX_PLL_DIV] = { - { 16, 2, 0, pll_divp_table }, - { 24, 4, CLK_DIVIDER_ONE_BASED, NULL }, - { 28, 3, 0, pll_divr_table }, + { 16, 2, 0, pll_divp_table }, + { 24, 4, 0, pll_divq_table }, + { 28, 3, 0, pll_divr_table }, }; struct stm32f4_pll_data { -- 1.9.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 1/2] clk: stm32f4: fix: exclude values 0 and 1 for PLLQ @ 2017-03-15 14:27 ` gabriel.fernandez at st.com 0 siblings, 0 replies; 10+ messages in thread From: gabriel.fernandez at st.com @ 2017-03-15 14:27 UTC (permalink / raw) To: linux-arm-kernel From: Gabriel Fernandez <gabriel.fernandez@st.com> 0000: PLLQ = 0, wrong configuration 0001: PLLQ = 1, wrong configuration ... 0010: PLLQ = 2 0011: PLLQ = 3 0100: PLLQ = 4 ... 1111: PLLQ = 1 Use divider table to exclude 0 and 1 values. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> --- drivers/clk/clk-stm32f4.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c index ab609a7..cf9449b3 100644 --- a/drivers/clk/clk-stm32f4.c +++ b/drivers/clk/clk-stm32f4.c @@ -429,6 +429,13 @@ enum { { 0, 2 }, { 1, 4 }, { 2, 6 }, { 3, 8 }, { 0 } }; +static const struct clk_div_table pll_divq_table[] = { + { 2, 2 }, { 3, 3 }, { 4, 4 }, { 5, 5 }, { 6, 6 }, { 7, 7 }, + { 8, 8 }, { 9, 9 }, { 10, 10 }, { 11, 11 }, { 12, 12 }, { 13, 13 }, + { 14, 14 }, { 15, 15 }, + { 0 } +}; + static const struct clk_div_table pll_divr_table[] = { { 2, 2 }, { 3, 3 }, { 4, 4 }, { 5, 5 }, { 6, 6 }, { 7, 7 }, { 0 } }; @@ -496,9 +503,9 @@ struct stm32f4_div_data { #define MAX_PLL_DIV 3 static const struct stm32f4_div_data div_data[MAX_PLL_DIV] = { - { 16, 2, 0, pll_divp_table }, - { 24, 4, CLK_DIVIDER_ONE_BASED, NULL }, - { 28, 3, 0, pll_divr_table }, + { 16, 2, 0, pll_divp_table }, + { 24, 4, 0, pll_divq_table }, + { 28, 3, 0, pll_divr_table }, }; struct stm32f4_pll_data { -- 1.9.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/2] clk: stm32f4: fix timeout management for pll and ready gate 2017-03-15 14:27 ` gabriel.fernandez at st.com @ 2017-03-15 14:27 ` gabriel.fernandez at st.com -1 siblings, 0 replies; 10+ messages in thread From: gabriel.fernandez @ 2017-03-15 14:27 UTC (permalink / raw) To: Michael Turquette, Stephen Boyd, Maxime Coquelin, Alexandre Torgue, Nicolas Pitre, Arnd Bergmann, daniel.thompson, andrea.merello, radoslaw.pietrzyk Cc: linux-clk, linux-arm-kernel, linux-kernel, gabriel.fernandez From: Gabriel Fernandez <gabriel.fernandez@st.com> Use a classic polling to test bit ready. And the shift of the bit ready of LSE & LSI were wrongs. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> --- drivers/clk/clk-stm32f4.c | 43 +++++++++++++++++++++++++++++-------------- 1 file changed, 29 insertions(+), 14 deletions(-) diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c index cf9449b3..68e2a4e 100644 --- a/drivers/clk/clk-stm32f4.c +++ b/drivers/clk/clk-stm32f4.c @@ -531,19 +531,26 @@ static int stm32f4_pll_is_enabled(struct clk_hw *hw) return clk_gate_ops.is_enabled(hw); } +#define PLL_TIMEOUT 10000 + static int stm32f4_pll_enable(struct clk_hw *hw) { struct clk_gate *gate = to_clk_gate(hw); struct stm32f4_pll *pll = to_stm32f4_pll(gate); - int ret = 0; - unsigned long reg; + int bit_status; + unsigned int timeout = PLL_TIMEOUT; - ret = clk_gate_ops.enable(hw); + if (clk_gate_ops.is_enabled(hw)) + return 0; + + clk_gate_ops.enable(hw); - ret = readl_relaxed_poll_timeout_atomic(base + STM32F4_RCC_CR, reg, - reg & (1 << pll->bit_rdy_idx), 0, 10000); + do { + bit_status = !(readl(gate->reg) & BIT(pll->bit_rdy_idx)); - return ret; + } while (bit_status && --timeout); + + return bit_status; } static void stm32f4_pll_disable(struct clk_hw *hw) @@ -834,24 +841,32 @@ struct stm32_rgate { u8 bit_rdy_idx; }; -#define RTC_TIMEOUT 1000000 +#define RGATE_TIMEOUT 50000 static int rgclk_enable(struct clk_hw *hw) { struct clk_gate *gate = to_clk_gate(hw); struct stm32_rgate *rgate = to_rgclk(gate); - u32 reg; - int ret; + int bit_status; + unsigned int timeout = RGATE_TIMEOUT; + + if (clk_gate_ops.is_enabled(hw)) + return 0; disable_power_domain_write_protection(); clk_gate_ops.enable(hw); - ret = readl_relaxed_poll_timeout_atomic(gate->reg, reg, - reg & rgate->bit_rdy_idx, 1000, RTC_TIMEOUT); + do { + bit_status = !(readl(gate->reg) & BIT(rgate->bit_rdy_idx)); + if (bit_status) + udelay(100); + + } while (bit_status && --timeout); enable_power_domain_write_protection(); - return ret; + + return bit_status; } static void rgclk_disable(struct clk_hw *hw) @@ -1533,7 +1548,7 @@ static void __init stm32f4_rcc_init(struct device_node *np) } clks[CLK_LSI] = clk_register_rgate(NULL, "lsi", "clk-lsi", 0, - base + STM32F4_RCC_CSR, 0, 2, 0, &stm32f4_clk_lock); + base + STM32F4_RCC_CSR, 0, 1, 0, &stm32f4_clk_lock); if (IS_ERR(clks[CLK_LSI])) { pr_err("Unable to register lsi clock\n"); @@ -1541,7 +1556,7 @@ static void __init stm32f4_rcc_init(struct device_node *np) } clks[CLK_LSE] = clk_register_rgate(NULL, "lse", "clk-lse", 0, - base + STM32F4_RCC_BDCR, 0, 2, 0, &stm32f4_clk_lock); + base + STM32F4_RCC_BDCR, 0, 1, 0, &stm32f4_clk_lock); if (IS_ERR(clks[CLK_LSE])) { pr_err("Unable to register lse clock\n"); -- 1.9.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/2] clk: stm32f4: fix timeout management for pll and ready gate @ 2017-03-15 14:27 ` gabriel.fernandez at st.com 0 siblings, 0 replies; 10+ messages in thread From: gabriel.fernandez at st.com @ 2017-03-15 14:27 UTC (permalink / raw) To: linux-arm-kernel From: Gabriel Fernandez <gabriel.fernandez@st.com> Use a classic polling to test bit ready. And the shift of the bit ready of LSE & LSI were wrongs. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> --- drivers/clk/clk-stm32f4.c | 43 +++++++++++++++++++++++++++++-------------- 1 file changed, 29 insertions(+), 14 deletions(-) diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c index cf9449b3..68e2a4e 100644 --- a/drivers/clk/clk-stm32f4.c +++ b/drivers/clk/clk-stm32f4.c @@ -531,19 +531,26 @@ static int stm32f4_pll_is_enabled(struct clk_hw *hw) return clk_gate_ops.is_enabled(hw); } +#define PLL_TIMEOUT 10000 + static int stm32f4_pll_enable(struct clk_hw *hw) { struct clk_gate *gate = to_clk_gate(hw); struct stm32f4_pll *pll = to_stm32f4_pll(gate); - int ret = 0; - unsigned long reg; + int bit_status; + unsigned int timeout = PLL_TIMEOUT; - ret = clk_gate_ops.enable(hw); + if (clk_gate_ops.is_enabled(hw)) + return 0; + + clk_gate_ops.enable(hw); - ret = readl_relaxed_poll_timeout_atomic(base + STM32F4_RCC_CR, reg, - reg & (1 << pll->bit_rdy_idx), 0, 10000); + do { + bit_status = !(readl(gate->reg) & BIT(pll->bit_rdy_idx)); - return ret; + } while (bit_status && --timeout); + + return bit_status; } static void stm32f4_pll_disable(struct clk_hw *hw) @@ -834,24 +841,32 @@ struct stm32_rgate { u8 bit_rdy_idx; }; -#define RTC_TIMEOUT 1000000 +#define RGATE_TIMEOUT 50000 static int rgclk_enable(struct clk_hw *hw) { struct clk_gate *gate = to_clk_gate(hw); struct stm32_rgate *rgate = to_rgclk(gate); - u32 reg; - int ret; + int bit_status; + unsigned int timeout = RGATE_TIMEOUT; + + if (clk_gate_ops.is_enabled(hw)) + return 0; disable_power_domain_write_protection(); clk_gate_ops.enable(hw); - ret = readl_relaxed_poll_timeout_atomic(gate->reg, reg, - reg & rgate->bit_rdy_idx, 1000, RTC_TIMEOUT); + do { + bit_status = !(readl(gate->reg) & BIT(rgate->bit_rdy_idx)); + if (bit_status) + udelay(100); + + } while (bit_status && --timeout); enable_power_domain_write_protection(); - return ret; + + return bit_status; } static void rgclk_disable(struct clk_hw *hw) @@ -1533,7 +1548,7 @@ static void __init stm32f4_rcc_init(struct device_node *np) } clks[CLK_LSI] = clk_register_rgate(NULL, "lsi", "clk-lsi", 0, - base + STM32F4_RCC_CSR, 0, 2, 0, &stm32f4_clk_lock); + base + STM32F4_RCC_CSR, 0, 1, 0, &stm32f4_clk_lock); if (IS_ERR(clks[CLK_LSI])) { pr_err("Unable to register lsi clock\n"); @@ -1541,7 +1556,7 @@ static void __init stm32f4_rcc_init(struct device_node *np) } clks[CLK_LSE] = clk_register_rgate(NULL, "lse", "clk-lse", 0, - base + STM32F4_RCC_BDCR, 0, 2, 0, &stm32f4_clk_lock); + base + STM32F4_RCC_BDCR, 0, 1, 0, &stm32f4_clk_lock); if (IS_ERR(clks[CLK_LSE])) { pr_err("Unable to register lse clock\n"); -- 1.9.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 0/2] STM32F4 clock fixes 2017-03-15 14:27 ` gabriel.fernandez at st.com @ 2017-03-15 20:43 ` Stephen Boyd -1 siblings, 0 replies; 10+ messages in thread From: Stephen Boyd @ 2017-03-15 20:43 UTC (permalink / raw) To: gabriel.fernandez Cc: Michael Turquette, Maxime Coquelin, Alexandre Torgue, Nicolas Pitre, Arnd Bergmann, daniel.thompson, andrea.merello, radoslaw.pietrzyk, linux-clk, linux-arm-kernel, linux-kernel On 03/15, gabriel.fernandez@st.com wrote: > From: Gabriel Fernandez <gabriel.fernandez@st.com> > > This patch-set contains 2 fixes. > One concerning exclusion of wrong values for PLLQ (0 & 1) > And the second is a fix about timeout management of PLL and LSE/LSI clocks. But neither of the patches have a "Fixes" tag. Can you please indicate what commits they're fixing? -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 0/2] STM32F4 clock fixes @ 2017-03-15 20:43 ` Stephen Boyd 0 siblings, 0 replies; 10+ messages in thread From: Stephen Boyd @ 2017-03-15 20:43 UTC (permalink / raw) To: linux-arm-kernel On 03/15, gabriel.fernandez at st.com wrote: > From: Gabriel Fernandez <gabriel.fernandez@st.com> > > This patch-set contains 2 fixes. > One concerning exclusion of wrong values for PLLQ (0 & 1) > And the second is a fix about timeout management of PLL and LSE/LSI clocks. But neither of the patches have a "Fixes" tag. Can you please indicate what commits they're fixing? -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 0/2] STM32F4 clock fixes 2017-03-15 20:43 ` Stephen Boyd @ 2017-03-16 8:04 ` Gabriel Fernandez -1 siblings, 0 replies; 10+ messages in thread From: Gabriel Fernandez @ 2017-03-16 8:04 UTC (permalink / raw) To: Stephen Boyd Cc: Michael Turquette, Maxime Coquelin, Alexandre Torgue, Nicolas Pitre, Arnd Bergmann, daniel.thompson, andrea.merello, radoslaw.pietrzyk, linux-clk, linux-arm-kernel, linux-kernel Hi Stephen, On 03/15/2017 09:43 PM, Stephen Boyd wrote: > On 03/15, gabriel.fernandez@st.com wrote: >> From: Gabriel Fernandez <gabriel.fernandez@st.com> >> >> This patch-set contains 2 fixes. >> One concerning exclusion of wrong values for PLLQ (0 & 1) >> And the second is a fix about timeout management of PLL and LSE/LSI clocks. > But neither of the patches have a "Fixes" tag. Can you please > indicate what commits they're fixing? > Okay i will send a v2 with "Fixes" tags BR Gabriel ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 0/2] STM32F4 clock fixes @ 2017-03-16 8:04 ` Gabriel Fernandez 0 siblings, 0 replies; 10+ messages in thread From: Gabriel Fernandez @ 2017-03-16 8:04 UTC (permalink / raw) To: linux-arm-kernel Hi Stephen, On 03/15/2017 09:43 PM, Stephen Boyd wrote: > On 03/15, gabriel.fernandez at st.com wrote: >> From: Gabriel Fernandez <gabriel.fernandez@st.com> >> >> This patch-set contains 2 fixes. >> One concerning exclusion of wrong values for PLLQ (0 & 1) >> And the second is a fix about timeout management of PLL and LSE/LSI clocks. > But neither of the patches have a "Fixes" tag. Can you please > indicate what commits they're fixing? > Okay i will send a v2 with "Fixes" tags BR Gabriel ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2017-03-16 8:04 UTC | newest] Thread overview: 10+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2017-03-15 14:27 [PATCH 0/2] STM32F4 clock fixes gabriel.fernandez 2017-03-15 14:27 ` gabriel.fernandez at st.com 2017-03-15 14:27 ` [PATCH 1/2] clk: stm32f4: fix: exclude values 0 and 1 for PLLQ gabriel.fernandez 2017-03-15 14:27 ` gabriel.fernandez at st.com 2017-03-15 14:27 ` [PATCH 2/2] clk: stm32f4: fix timeout management for pll and ready gate gabriel.fernandez 2017-03-15 14:27 ` gabriel.fernandez at st.com 2017-03-15 20:43 ` [PATCH 0/2] STM32F4 clock fixes Stephen Boyd 2017-03-15 20:43 ` Stephen Boyd 2017-03-16 8:04 ` Gabriel Fernandez 2017-03-16 8:04 ` Gabriel Fernandez
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.