From: Jan Glauber <jan.glauber@caviumnetworks.com>
To: Boris Brezillon <boris.brezillon@free-electrons.com>
Cc: Richard Weinberger <richard@nod.at>,
David Woodhouse <dwmw2@infradead.org>,
Brian Norris <computersforpeace@gmail.com>,
Marek Vasut <marek.vasut@gmail.com>,
Cyrille Pitchen <cyrille.pitchen@atmel.com>,
Mark Rutland <mark.rutland@arm.com>,
devicetree@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
linux-mtd@lists.infradead.org
Subject: Re: [RFC PATCH 1/2] dt-bindings: mtd: Add Cavium SOCs NAND bindings
Date: Tue, 28 Mar 2017 23:30:13 +0200 [thread overview]
Message-ID: <20170328213013.GA2972@hardcore> (raw)
In-Reply-To: <20170328222035.29f4ed31@bbrezillon>
On Tue, Mar 28, 2017 at 10:20:35PM +0200, Boris Brezillon wrote:
> Hi Jan,
>
> On Mon, 27 Mar 2017 18:05:23 +0200
> Jan Glauber <jglauber@cavium.com> wrote:
>
> > Add device tree binding description for Cavium SOC nand flash controller.
> >
> > CC: Rob Herring <robh+dt@kernel.org>
> > CC: Mark Rutland <mark.rutland@arm.com>
> > CC: devicetree@vger.kernel.org
> >
> > Signed-off-by: Jan Glauber <jglauber@cavium.com>
> > ---
> > .../devicetree/bindings/mtd/cavium_nand.txt | 32 ++++++++++++++++++++++
> > 1 file changed, 32 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/mtd/cavium_nand.txt
> >
> > diff --git a/Documentation/devicetree/bindings/mtd/cavium_nand.txt b/Documentation/devicetree/bindings/mtd/cavium_nand.txt
> > new file mode 100644
> > index 0000000..4698d1f
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/mtd/cavium_nand.txt
> > @@ -0,0 +1,32 @@
> > +* Cavium NAND controller
> > +
> > +Required properties:
> > +
> > +- compatible: should be "cavium,cn8xxx-nand"
> > +- reg: PCI devfn
> > +- clocks: must contain system clock
> > +- #address-cells: <1>
> > +- #size-cells: <0>
> > +
> > +The nand flash controller may contain up to 8 subnodes representing
> > +NAND flash chips. Their properties are as follows.
> > +
> > +Required properties:
> > +- compatible: should be "cavium,nandcs"
>
> Why do you need a compatible here? All sub-nodes should be representing
> NAND devices connected to the NAND controller. If you need an extra
> subnode to represent something that is not a NAND device, then it should
> not have a reg property, so testing if reg is present to detect if the
> subnode is reprensenting a NAND device should be enough.
>
> Am I missing something?
Hi Boris,
You're right. We don't need or check this compatible. The chip type
which would make more sense than what I used above is detected via ONFI,
so I can just remove the compatible string.
> > +- reg: a single integer representing the chip-select number
> > +- nand-ecc-mode: see nand.txt
> > +
> > +Example:
> > +
> > +nfc: nand@b,0 {
>
> ^ nand-controller@xxx
OK.
> > + compatible = "cavium,cn8xxx-nand";
> > + reg = <0x5800 0 0 0 0>;
> > + clocks = <&sclk>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + nand@1 {
> > + compatible = "cavium,nandcs";
> > + reg = <1>;
> > + nand-ecc-mode = "on-die";
> > +};
WARNING: multiple messages have this Message-ID (diff)
From: Jan Glauber <jan.glauber-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>
To: Boris Brezillon
<boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Cc: Richard Weinberger <richard-/L3Ra7n9ekc@public.gmane.org>,
David Woodhouse <dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org>,
Brian Norris
<computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
Marek Vasut <marek.vasut-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
Cyrille Pitchen
<cyrille.pitchen-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>,
Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Subject: Re: [RFC PATCH 1/2] dt-bindings: mtd: Add Cavium SOCs NAND bindings
Date: Tue, 28 Mar 2017 23:30:13 +0200 [thread overview]
Message-ID: <20170328213013.GA2972@hardcore> (raw)
In-Reply-To: <20170328222035.29f4ed31@bbrezillon>
On Tue, Mar 28, 2017 at 10:20:35PM +0200, Boris Brezillon wrote:
> Hi Jan,
>
> On Mon, 27 Mar 2017 18:05:23 +0200
> Jan Glauber <jglauber-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org> wrote:
>
> > Add device tree binding description for Cavium SOC nand flash controller.
> >
> > CC: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> > CC: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> > CC: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> >
> > Signed-off-by: Jan Glauber <jglauber-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>
> > ---
> > .../devicetree/bindings/mtd/cavium_nand.txt | 32 ++++++++++++++++++++++
> > 1 file changed, 32 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/mtd/cavium_nand.txt
> >
> > diff --git a/Documentation/devicetree/bindings/mtd/cavium_nand.txt b/Documentation/devicetree/bindings/mtd/cavium_nand.txt
> > new file mode 100644
> > index 0000000..4698d1f
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/mtd/cavium_nand.txt
> > @@ -0,0 +1,32 @@
> > +* Cavium NAND controller
> > +
> > +Required properties:
> > +
> > +- compatible: should be "cavium,cn8xxx-nand"
> > +- reg: PCI devfn
> > +- clocks: must contain system clock
> > +- #address-cells: <1>
> > +- #size-cells: <0>
> > +
> > +The nand flash controller may contain up to 8 subnodes representing
> > +NAND flash chips. Their properties are as follows.
> > +
> > +Required properties:
> > +- compatible: should be "cavium,nandcs"
>
> Why do you need a compatible here? All sub-nodes should be representing
> NAND devices connected to the NAND controller. If you need an extra
> subnode to represent something that is not a NAND device, then it should
> not have a reg property, so testing if reg is present to detect if the
> subnode is reprensenting a NAND device should be enough.
>
> Am I missing something?
Hi Boris,
You're right. We don't need or check this compatible. The chip type
which would make more sense than what I used above is detected via ONFI,
so I can just remove the compatible string.
> > +- reg: a single integer representing the chip-select number
> > +- nand-ecc-mode: see nand.txt
> > +
> > +Example:
> > +
> > +nfc: nand@b,0 {
>
> ^ nand-controller@xxx
OK.
> > + compatible = "cavium,cn8xxx-nand";
> > + reg = <0x5800 0 0 0 0>;
> > + clocks = <&sclk>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + nand@1 {
> > + compatible = "cavium,nandcs";
> > + reg = <1>;
> > + nand-ecc-mode = "on-die";
> > +};
--
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next prev parent reply other threads:[~2017-03-28 21:30 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-27 16:05 [RFC PATCH 0/2] Cavium NAND flash driver Jan Glauber
2017-03-27 16:05 ` [RFC PATCH 1/2] dt-bindings: mtd: Add Cavium SOCs NAND bindings Jan Glauber
2017-03-27 16:05 ` Jan Glauber
2017-03-28 20:20 ` Boris Brezillon
2017-03-28 20:20 ` Boris Brezillon
2017-03-28 21:30 ` Jan Glauber [this message]
2017-03-28 21:30 ` Jan Glauber
2017-04-03 13:29 ` Rob Herring
2017-04-03 13:29 ` Rob Herring
2017-04-03 14:38 ` Jan Glauber
2017-04-03 14:38 ` Jan Glauber
2017-04-03 14:47 ` Rob Herring
2017-04-03 14:47 ` Rob Herring
2017-04-03 16:18 ` Jan Glauber
2017-04-03 16:18 ` Jan Glauber
2017-03-27 16:05 ` [RFC PATCH 2/2] nand: cavium: Nand flash controller for Cavium ARM64 SOCs Jan Glauber
2017-03-29 9:29 ` Boris Brezillon
2017-03-29 10:02 ` Jan Glauber
2017-03-29 13:59 ` Boris Brezillon
2017-04-25 11:26 ` Jan Glauber
2017-04-30 13:01 ` Boris Brezillon
2017-05-15 12:33 ` Boris Brezillon
2017-05-15 12:35 ` Boris Brezillon
2017-05-19 7:51 ` Boris Brezillon
2017-05-22 11:35 ` Jan Glauber
2017-05-22 11:53 ` Boris Brezillon
2017-05-22 11:44 ` Boris Brezillon
2017-07-20 20:25 ` [RFC PATCH 0/2] Cavium NAND flash driver Karl Beldan
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