From: Stephen Boyd <sboyd@codeaurora.org>
To: Shawn Guo <shawnguo@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
Jun Nie <jun.nie@linaro.org>, Baoyou Xie <xie.baoyou@zte.com.cn>,
Xin Zhou <zhou.xin8@zte.com.cn>, Shawn Guo <shawn.guo@linaro.org>
Subject: Re: [PATCH 2/3] zte: clk: pd_bit is not 0 on zx296718
Date: Fri, 7 Apr 2017 12:22:13 -0700 [thread overview]
Message-ID: <20170407192213.GZ7065@codeaurora.org> (raw)
In-Reply-To: <1490085503-15713-3-git-send-email-shawnguo@kernel.org>
On 03/21, Shawn Guo wrote:
> From: Shawn Guo <shawn.guo@linaro.org>
>
> The bit 0 of PLL_CFG0 register is not powerdown on zx296718, but part of
> of postdiv2 field. The consequence is that functions like hw_to_idx()
> and zx_pll_enable() will end up tampering the postdiv2 of the PLL.
>
> Let's fix it by defining pd_bit 0xff which is obviously invalid for a
> bit position and having PLL driver check the validity before operating
> on the bit.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
WARNING: multiple messages have this Message-ID (diff)
From: sboyd@codeaurora.org (Stephen Boyd)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/3] zte: clk: pd_bit is not 0 on zx296718
Date: Fri, 7 Apr 2017 12:22:13 -0700 [thread overview]
Message-ID: <20170407192213.GZ7065@codeaurora.org> (raw)
In-Reply-To: <1490085503-15713-3-git-send-email-shawnguo@kernel.org>
On 03/21, Shawn Guo wrote:
> From: Shawn Guo <shawn.guo@linaro.org>
>
> The bit 0 of PLL_CFG0 register is not powerdown on zx296718, but part of
> of postdiv2 field. The consequence is that functions like hw_to_idx()
> and zx_pll_enable() will end up tampering the postdiv2 of the PLL.
>
> Let's fix it by defining pd_bit 0xff which is obviously invalid for a
> bit position and having PLL driver check the validity before operating
> on the bit.
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2017-04-07 19:22 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-21 8:38 [PATCH 0/3] ZX296718 clock update for VGA support Shawn Guo
2017-03-21 8:38 ` Shawn Guo
2017-03-21 8:38 ` [PATCH 1/3] clk: zte: set CLK_SET_RATE_PARENT for a few zx296718 clocks Shawn Guo
2017-03-21 8:38 ` Shawn Guo
2017-03-23 1:37 ` Jun Nie
2017-03-23 1:37 ` Jun Nie
2017-04-07 19:22 ` Stephen Boyd
2017-04-07 19:22 ` Stephen Boyd
2017-03-21 8:38 ` [PATCH 2/3] zte: clk: pd_bit is not 0 on zx296718 Shawn Guo
2017-03-21 8:38 ` Shawn Guo
2017-03-23 1:34 ` Jun Nie
2017-03-23 1:34 ` Jun Nie
2017-04-07 19:22 ` Stephen Boyd [this message]
2017-04-07 19:22 ` Stephen Boyd
2017-03-21 8:38 ` [PATCH 3/3] clk: zte: add pll_vga clock for zx296718 Shawn Guo
2017-03-21 8:38 ` Shawn Guo
2017-03-23 1:36 ` Jun Nie
2017-03-23 1:36 ` Jun Nie
2017-04-07 19:22 ` Stephen Boyd
2017-04-07 19:22 ` Stephen Boyd
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