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From: Yi Sun <yi.y.sun@linux.intel.com>
To: Jan Beulich <JBeulich@suse.com>
Cc: kevin.tian@intel.com, wei.liu2@citrix.com,
	he.chen@linux.intel.com, andrew.cooper3@citrix.com,
	dario.faggioli@citrix.com, ian.jackson@eu.citrix.com,
	mengxu@cis.upenn.edu, xen-devel@lists.xenproject.org,
	chao.p.peng@linux.intel.com, roger.pau@citrix.com
Subject: Re: [PATCH v10 09/25] x86: refactor psr: L3 CAT: set value: implement framework.
Date: Wed, 19 Apr 2017 16:22:42 +0800	[thread overview]
Message-ID: <20170419082241.GL17458@yi.y.sun> (raw)
In-Reply-To: <58F618C302000078001518AB@prv-mh.provo.novell.com>

On 17-04-18 05:46:43, Jan Beulich wrote:
> >>> On 18.04.17 at 12:55, <yi.y.sun@linux.intel.com> wrote:
> > I made a test patch based on v10 and attached it in mail. Could you please
> > help to check it? Thanks!
> 
> This looks reasonable at the first glance, albeit I continue to be
> unconvinced that this is the only (reasonable) way of solving the
> problem. After all we don't have to go through similar hoops for
> any other of the register state associated with a vCPU. There

Sorry, I do not understand your meaning clearly.
1. DYM the ASSOC register which is set in 'psr_ctxt_switch_to'? In this patch,
   we check 'dom_ids' array to know if the domain's cos id has not been set but
   its 'psr_cos_ids[socket]' already has a non zero value. This case means the
   socket offline has happened so that we have to restore the domain's
   'psr_cos_ids[socket]' to default value 0 which points to default COS MSR.
   I think we have discussed this in previous mails and achieved agreement on
   such logic. 
2. DYM the COS MSRs? We have discussed this before. Per your comments, when
   socket is online, the registers values may be modified by FW and others.
   So, we have to restore them to default value which is being done in
   'cat_init_feature'.

So, what is your exactly meaning here? Thanks!

> are a number of cosmetic issues, but commenting on an attached
> (rather than inlined) patch is a little difficult.
> 
Sorry for that, I will directly send patch out next time.

> One remark regarding the locking though: Acquiring a lock in the
> context switch path should be made as low risk of long stalls as
> possible. Therefore you will want to consider using r/w locks
> instead of spin locks here, which would allow parallelism on all
> cores of a socket as long as COS IDs aren't being updated.
> 
In 'psr_ctxt_switch_to', I use the lock only to protect 'write' actions.
So, I do not understand why read-write lock is better? Anything I don't
consider? Please help to point out. Thanks!

> Jan

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  reply	other threads:[~2017-04-19  8:22 UTC|newest]

Thread overview: 114+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-04-01 13:53 [PATCH v10 00/25] Enable L2 Cache Allocation Technology & Refactor psr.c Yi Sun
2017-04-01 13:53 ` [PATCH v10 01/25] docs: create Cache Allocation Technology (CAT) and Code and Data Prioritization (CDP) feature document Yi Sun
2017-04-01 13:53 ` [PATCH v10 02/25] x86: refactor psr: remove L3 CAT/CDP codes Yi Sun
2017-04-01 13:53 ` [PATCH v10 03/25] x86: refactor psr: implement main data structures Yi Sun
2017-04-03 15:50   ` Jan Beulich
2017-04-05  3:12     ` Yi Sun
2017-04-05  8:20       ` Jan Beulich
2017-04-05  8:45         ` Yi Sun
2017-04-01 13:53 ` [PATCH v10 04/25] x86: move cpuid_count_leaf from cpuid.c to processor.h Yi Sun
2017-04-01 13:53 ` [PATCH v10 05/25] x86: refactor psr: L3 CAT: implement CPU init and free flow Yi Sun
2017-04-05 15:10   ` Jan Beulich
2017-04-06  5:49     ` Yi Sun
2017-04-06  8:32       ` Jan Beulich
2017-04-06  9:22         ` Yi Sun
2017-04-06  9:34           ` Jan Beulich
2017-04-06 10:02             ` Yi Sun
2017-04-06 14:02               ` Jan Beulich
2017-04-07  5:17                 ` Yi Sun
2017-04-07  8:48                   ` Jan Beulich
2017-04-07  9:08                     ` Yi Sun
2017-04-07  9:46                       ` Jan Beulich
2017-04-10  3:27                         ` Yi Sun
2017-04-10 12:43                           ` Yi Sun
2017-04-01 13:53 ` [PATCH v10 06/25] x86: refactor psr: L3 CAT: implement Domain init/free and schedule flows Yi Sun
2017-04-05 15:23   ` Jan Beulich
2017-04-06  6:01     ` Yi Sun
2017-04-06  8:34       ` Jan Beulich
2017-04-01 13:53 ` [PATCH v10 07/25] x86: refactor psr: L3 CAT: implement get hw info flow Yi Sun
2017-04-05 15:37   ` Jan Beulich
2017-04-06  6:05     ` Yi Sun
2017-04-06  8:36       ` Jan Beulich
2017-04-06 11:16         ` Yi Sun
2017-04-06 14:04           ` Jan Beulich
2017-04-07  5:39             ` Yi Sun
2017-04-01 13:53 ` [PATCH v10 08/25] x86: refactor psr: L3 CAT: implement get value flow Yi Sun
2017-04-05 15:51   ` Jan Beulich
2017-04-06  6:10     ` Yi Sun
2017-04-06  8:40       ` Jan Beulich
2017-04-06 11:13         ` Yi Sun
2017-04-06 14:08           ` Jan Beulich
2017-04-07  5:40             ` Yi Sun
2017-04-01 13:53 ` [PATCH v10 09/25] x86: refactor psr: L3 CAT: set value: implement framework Yi Sun
2017-04-11 15:01   ` Jan Beulich
2017-04-12  5:53     ` Yi Sun
2017-04-12  9:09       ` Jan Beulich
2017-04-12 12:23         ` Yi Sun
2017-04-12 12:42           ` Jan Beulich
2017-04-13  8:11             ` Yi Sun
2017-04-13  9:41               ` Jan Beulich
2017-04-13 10:49                 ` Yi Sun
2017-04-13 10:58                   ` Jan Beulich
2017-04-13 11:11                     ` Yi Sun
2017-04-13 11:26                       ` Yi Sun
2017-04-13 11:31                       ` Jan Beulich
2017-04-13 11:44                         ` Yi Sun
2017-04-13 11:50                           ` Jan Beulich
2017-04-18 10:55                             ` Yi Sun
2017-04-18 11:46                               ` Jan Beulich
2017-04-19  8:22                                 ` Yi Sun [this message]
2017-04-19  9:00                                   ` Jan Beulich
2017-04-20  2:14                                     ` Yi Sun
2017-04-20  9:43                                       ` Jan Beulich
2017-04-20 13:02                                         ` Lars Kurth
2017-04-20 13:21                                           ` Jan Beulich
2017-04-20 16:52                                             ` Lars Kurth
2017-04-21  6:11                                               ` Jan Beulich
2017-04-21  1:13                                             ` Konrad Rzeszutek Wilk
2017-04-21  6:18                                       ` Jan Beulich
2017-04-24  6:40                                         ` Yi Sun
2017-04-24  6:55                                           ` Jan Beulich
2017-04-25  7:15                                             ` Yi Sun
2017-04-25  8:24                                               ` Jan Beulich
2017-04-25  8:40                                                 ` Yi Sun
2017-04-20  5:38   ` [PATCH] dom_ids array implementation Yi Sun
2017-04-26 10:04     ` Jan Beulich
2017-04-27  2:38       ` Yi Sun
2017-04-27  6:48         ` Jan Beulich
2017-04-27  9:30           ` Yi Sun
2017-04-27  9:39             ` Jan Beulich
2017-04-27 12:03               ` Yi Sun
2017-04-01 13:53 ` [PATCH v10 10/25] x86: refactor psr: L3 CAT: set value: assemble features value array Yi Sun
2017-04-11 15:11   ` Jan Beulich
2017-04-12  5:55     ` Yi Sun
2017-04-12  9:13       ` Jan Beulich
2017-04-12 12:26         ` Yi Sun
2017-04-01 13:53 ` [PATCH v10 11/25] x86: refactor psr: L3 CAT: set value: implement cos finding flow Yi Sun
2017-04-11 15:17   ` Jan Beulich
2017-04-01 13:53 ` [PATCH v10 12/25] x86: refactor psr: L3 CAT: set value: implement cos id picking flow Yi Sun
2017-04-11 15:20   ` Jan Beulich
2017-04-01 13:53 ` [PATCH v10 13/25] x86: refactor psr: L3 CAT: set value: implement write msr flow Yi Sun
2017-04-11 15:25   ` Jan Beulich
2017-04-12  6:04     ` Yi Sun
2017-04-01 13:53 ` [PATCH v10 14/25] x86: refactor psr: CDP: implement CPU init and free flow Yi Sun
2017-04-01 13:53 ` [PATCH v10 15/25] x86: refactor psr: CDP: implement get hw info flow Yi Sun
2017-04-01 13:53 ` [PATCH v10 16/25] x86: refactor psr: CDP: implement get value flow Yi Sun
2017-04-11 15:39   ` Jan Beulich
2017-04-12  6:05     ` Yi Sun
2017-04-12  9:14       ` Jan Beulich
2017-04-01 13:53 ` [PATCH v10 17/25] x86: refactor psr: CDP: implement set value callback functions Yi Sun
2017-04-11 16:03   ` Jan Beulich
2017-04-12  6:14     ` Yi Sun
2017-04-01 13:53 ` [PATCH v10 18/25] x86: L2 CAT: implement CPU init and free flow Yi Sun
2017-04-12 15:18   ` Jan Beulich
2017-04-13  8:12     ` Yi Sun
2017-04-13  8:16       ` Jan Beulich
2017-04-01 13:53 ` [PATCH v10 19/25] x86: L2 CAT: implement get hw info flow Yi Sun
2017-04-01 13:53 ` [PATCH v10 20/25] x86: L2 CAT: implement get value flow Yi Sun
2017-04-01 13:53 ` [PATCH v10 21/25] x86: L2 CAT: implement set " Yi Sun
2017-04-12 15:23   ` Jan Beulich
2017-04-01 13:53 ` [PATCH v10 22/25] tools: L2 CAT: support get HW info for L2 CAT Yi Sun
2017-04-12 15:24   ` Jan Beulich
2017-04-01 13:53 ` [PATCH v10 23/25] tools: L2 CAT: support show cbm " Yi Sun
2017-04-01 13:53 ` [PATCH v10 24/25] tools: L2 CAT: support set " Yi Sun
2017-04-01 13:53 ` [PATCH v10 25/25] docs: add L2 CAT description in docs Yi Sun

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