From: Stephen Boyd <sboyd@codeaurora.org>
To: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>,
Michael Turquette <mturquette@baylibre.com>,
Thierry Reding <thierry.reding@gmail.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] clk: tegra: fix SS control on PLL enable/disable
Date: Fri, 21 Apr 2017 19:38:48 -0700 [thread overview]
Message-ID: <20170422023848.GJ7065@codeaurora.org> (raw)
In-Reply-To: <1492691989-30539-1-git-send-email-pdeschrijver@nvidia.com>
On 04/20, Peter De Schrijver wrote:
> PLL SS was only controlled when setting the PLL rate, not when the PLL
> itself is enabled or disabled. This means that if the PLL rate was set
> before the PLL is enabled, SS will not be enabled, even when configured.
>
> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Fixes tag? Or this isn't a problem right now, just future fix?
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2017-04-22 2:38 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-04-20 12:39 [PATCH] clk: tegra: fix SS control on PLL enable/disable Peter De Schrijver
2017-04-20 12:39 ` Peter De Schrijver
2017-04-22 2:38 ` Stephen Boyd [this message]
2017-05-04 7:42 ` Peter De Schrijver
2017-05-04 7:42 ` Peter De Schrijver
-- strict thread matches above, loose matches on Subject: below --
2017-04-13 13:21 Peter De Schrijver
2017-04-13 13:21 ` Peter De Schrijver
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