* [PATCH] clk: tegra: fix SS control on PLL enable/disable
@ 2017-04-20 12:39 ` Peter De Schrijver
0 siblings, 0 replies; 7+ messages in thread
From: Peter De Schrijver @ 2017-04-20 12:39 UTC (permalink / raw)
To: Peter De Schrijver, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Thierry Reding, Jonathan Hunter, linux-clk,
linux-tegra, linux-kernel
PLL SS was only controlled when setting the PLL rate, not when the PLL
itself is enabled or disabled. This means that if the PLL rate was set
before the PLL is enabled, SS will not be enabled, even when configured.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
drivers/clk/tegra/clk-pll.c | 44 ++++++++++++++++++++++++--------------------
1 file changed, 24 insertions(+), 20 deletions(-)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 159a854..e9bdb16 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -418,6 +418,26 @@ static void _clk_pll_disable(struct clk_hw *hw)
}
}
+static void pll_clk_start_ss(struct tegra_clk_pll *pll)
+{
+ if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
+ u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
+
+ val |= pll->params->ssc_ctrl_en_mask;
+ pll_writel(val, pll->params->ssc_ctrl_reg, pll);
+ }
+}
+
+static void pll_clk_stop_ss(struct tegra_clk_pll *pll)
+{
+ if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
+ u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
+
+ val &= ~pll->params->ssc_ctrl_en_mask;
+ pll_writel(val, pll->params->ssc_ctrl_reg, pll);
+ }
+}
+
static int clk_pll_enable(struct clk_hw *hw)
{
struct tegra_clk_pll *pll = to_clk_pll(hw);
@@ -431,6 +451,8 @@ static int clk_pll_enable(struct clk_hw *hw)
ret = clk_pll_wait_for_lock(pll);
+ pll_clk_start_ss(pll);
+
if (pll->lock)
spin_unlock_irqrestore(pll->lock, flags);
@@ -445,6 +467,8 @@ static void clk_pll_disable(struct clk_hw *hw)
if (pll->lock)
spin_lock_irqsave(pll->lock, flags);
+ pll_clk_stop_ss(pll);
+
_clk_pll_disable(hw);
if (pll->lock)
@@ -716,26 +740,6 @@ static void _update_pll_cpcon(struct tegra_clk_pll *pll,
pll_writel_misc(val, pll);
}
-static void pll_clk_start_ss(struct tegra_clk_pll *pll)
-{
- if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
- u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
-
- val |= pll->params->ssc_ctrl_en_mask;
- pll_writel(val, pll->params->ssc_ctrl_reg, pll);
- }
-}
-
-static void pll_clk_stop_ss(struct tegra_clk_pll *pll)
-{
- if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
- u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
-
- val &= ~pll->params->ssc_ctrl_en_mask;
- pll_writel(val, pll->params->ssc_ctrl_reg, pll);
- }
-}
-
static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
unsigned long rate)
{
--
1.9.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH] clk: tegra: fix SS control on PLL enable/disable
@ 2017-04-20 12:39 ` Peter De Schrijver
0 siblings, 0 replies; 7+ messages in thread
From: Peter De Schrijver @ 2017-04-20 12:39 UTC (permalink / raw)
To: Peter De Schrijver, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Thierry Reding, Jonathan Hunter, linux-clk,
linux-tegra, linux-kernel
PLL SS was only controlled when setting the PLL rate, not when the PLL
itself is enabled or disabled. This means that if the PLL rate was set
before the PLL is enabled, SS will not be enabled, even when configured.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
drivers/clk/tegra/clk-pll.c | 44 ++++++++++++++++++++++++--------------------
1 file changed, 24 insertions(+), 20 deletions(-)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 159a854..e9bdb16 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -418,6 +418,26 @@ static void _clk_pll_disable(struct clk_hw *hw)
}
}
+static void pll_clk_start_ss(struct tegra_clk_pll *pll)
+{
+ if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
+ u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
+
+ val |= pll->params->ssc_ctrl_en_mask;
+ pll_writel(val, pll->params->ssc_ctrl_reg, pll);
+ }
+}
+
+static void pll_clk_stop_ss(struct tegra_clk_pll *pll)
+{
+ if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
+ u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
+
+ val &= ~pll->params->ssc_ctrl_en_mask;
+ pll_writel(val, pll->params->ssc_ctrl_reg, pll);
+ }
+}
+
static int clk_pll_enable(struct clk_hw *hw)
{
struct tegra_clk_pll *pll = to_clk_pll(hw);
@@ -431,6 +451,8 @@ static int clk_pll_enable(struct clk_hw *hw)
ret = clk_pll_wait_for_lock(pll);
+ pll_clk_start_ss(pll);
+
if (pll->lock)
spin_unlock_irqrestore(pll->lock, flags);
@@ -445,6 +467,8 @@ static void clk_pll_disable(struct clk_hw *hw)
if (pll->lock)
spin_lock_irqsave(pll->lock, flags);
+ pll_clk_stop_ss(pll);
+
_clk_pll_disable(hw);
if (pll->lock)
@@ -716,26 +740,6 @@ static void _update_pll_cpcon(struct tegra_clk_pll *pll,
pll_writel_misc(val, pll);
}
-static void pll_clk_start_ss(struct tegra_clk_pll *pll)
-{
- if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
- u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
-
- val |= pll->params->ssc_ctrl_en_mask;
- pll_writel(val, pll->params->ssc_ctrl_reg, pll);
- }
-}
-
-static void pll_clk_stop_ss(struct tegra_clk_pll *pll)
-{
- if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
- u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
-
- val &= ~pll->params->ssc_ctrl_en_mask;
- pll_writel(val, pll->params->ssc_ctrl_reg, pll);
- }
-}
-
static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
unsigned long rate)
{
--
1.9.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH] clk: tegra: fix SS control on PLL enable/disable
2017-04-20 12:39 ` Peter De Schrijver
(?)
@ 2017-04-22 2:38 ` Stephen Boyd
2017-05-04 7:42 ` Peter De Schrijver
-1 siblings, 1 reply; 7+ messages in thread
From: Stephen Boyd @ 2017-04-22 2:38 UTC (permalink / raw)
To: Peter De Schrijver
Cc: Prashant Gaikwad, Michael Turquette, Thierry Reding,
Jonathan Hunter, linux-clk, linux-tegra, linux-kernel
On 04/20, Peter De Schrijver wrote:
> PLL SS was only controlled when setting the PLL rate, not when the PLL
> itself is enabled or disabled. This means that if the PLL rate was set
> before the PLL is enabled, SS will not be enabled, even when configured.
>
> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Fixes tag? Or this isn't a problem right now, just future fix?
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] clk: tegra: fix SS control on PLL enable/disable
@ 2017-05-04 7:42 ` Peter De Schrijver
0 siblings, 0 replies; 7+ messages in thread
From: Peter De Schrijver @ 2017-05-04 7:42 UTC (permalink / raw)
To: Stephen Boyd
Cc: Prashant Gaikwad, Michael Turquette, Thierry Reding,
Jonathan Hunter, linux-clk, linux-tegra, linux-kernel
On Fri, Apr 21, 2017 at 07:38:48PM -0700, Stephen Boyd wrote:
> On 04/20, Peter De Schrijver wrote:
> > PLL SS was only controlled when setting the PLL rate, not when the PLL
> > itself is enabled or disabled. This means that if the PLL rate was set
> > before the PLL is enabled, SS will not be enabled, even when configured.
> >
> > Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
>
> Fixes tag? Or this isn't a problem right now, just future fix?
>
This isn't a problem right now, at least noone complained about it.
Peter.
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] clk: tegra: fix SS control on PLL enable/disable
@ 2017-05-04 7:42 ` Peter De Schrijver
0 siblings, 0 replies; 7+ messages in thread
From: Peter De Schrijver @ 2017-05-04 7:42 UTC (permalink / raw)
To: Stephen Boyd
Cc: Prashant Gaikwad, Michael Turquette, Thierry Reding,
Jonathan Hunter, linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
On Fri, Apr 21, 2017 at 07:38:48PM -0700, Stephen Boyd wrote:
> On 04/20, Peter De Schrijver wrote:
> > PLL SS was only controlled when setting the PLL rate, not when the PLL
> > itself is enabled or disabled. This means that if the PLL rate was set
> > before the PLL is enabled, SS will not be enabled, even when configured.
> >
> > Signed-off-by: Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>
> Fixes tag? Or this isn't a problem right now, just future fix?
>
This isn't a problem right now, at least noone complained about it.
Peter.
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH] clk: tegra: fix SS control on PLL enable/disable
@ 2017-04-13 13:21 ` Peter De Schrijver
0 siblings, 0 replies; 7+ messages in thread
From: Peter De Schrijver @ 2017-04-13 13:21 UTC (permalink / raw)
To: Peter De Schrijver, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Thierry Reding, Jonathan Hunter, linux-clk,
linux-tegra, linux-kernel
PLL SS was only controlled when setting the PLL rate, not when the PLL
itself is enabled or disabled. This means that if the PLL rate was set
before the PLL is enabled, SS will not be enabled, even when configured.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
drivers/clk/tegra/clk-pll.c | 44 ++++++++++++++++++++++++--------------------
1 file changed, 24 insertions(+), 20 deletions(-)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 159a854..e9bdb16 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -418,6 +418,26 @@ static void _clk_pll_disable(struct clk_hw *hw)
}
}
+static void pll_clk_start_ss(struct tegra_clk_pll *pll)
+{
+ if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
+ u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
+
+ val |= pll->params->ssc_ctrl_en_mask;
+ pll_writel(val, pll->params->ssc_ctrl_reg, pll);
+ }
+}
+
+static void pll_clk_stop_ss(struct tegra_clk_pll *pll)
+{
+ if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
+ u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
+
+ val &= ~pll->params->ssc_ctrl_en_mask;
+ pll_writel(val, pll->params->ssc_ctrl_reg, pll);
+ }
+}
+
static int clk_pll_enable(struct clk_hw *hw)
{
struct tegra_clk_pll *pll = to_clk_pll(hw);
@@ -431,6 +451,8 @@ static int clk_pll_enable(struct clk_hw *hw)
ret = clk_pll_wait_for_lock(pll);
+ pll_clk_start_ss(pll);
+
if (pll->lock)
spin_unlock_irqrestore(pll->lock, flags);
@@ -445,6 +467,8 @@ static void clk_pll_disable(struct clk_hw *hw)
if (pll->lock)
spin_lock_irqsave(pll->lock, flags);
+ pll_clk_stop_ss(pll);
+
_clk_pll_disable(hw);
if (pll->lock)
@@ -716,26 +740,6 @@ static void _update_pll_cpcon(struct tegra_clk_pll *pll,
pll_writel_misc(val, pll);
}
-static void pll_clk_start_ss(struct tegra_clk_pll *pll)
-{
- if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
- u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
-
- val |= pll->params->ssc_ctrl_en_mask;
- pll_writel(val, pll->params->ssc_ctrl_reg, pll);
- }
-}
-
-static void pll_clk_stop_ss(struct tegra_clk_pll *pll)
-{
- if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
- u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
-
- val &= ~pll->params->ssc_ctrl_en_mask;
- pll_writel(val, pll->params->ssc_ctrl_reg, pll);
- }
-}
-
static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
unsigned long rate)
{
--
1.9.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH] clk: tegra: fix SS control on PLL enable/disable
@ 2017-04-13 13:21 ` Peter De Schrijver
0 siblings, 0 replies; 7+ messages in thread
From: Peter De Schrijver @ 2017-04-13 13:21 UTC (permalink / raw)
To: Peter De Schrijver, Prashant Gaikwad, Michael Turquette,
Stephen Boyd, Thierry Reding, Jonathan Hunter,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
PLL SS was only controlled when setting the PLL rate, not when the PLL
itself is enabled or disabled. This means that if the PLL rate was set
before the PLL is enabled, SS will not be enabled, even when configured.
Signed-off-by: Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
drivers/clk/tegra/clk-pll.c | 44 ++++++++++++++++++++++++--------------------
1 file changed, 24 insertions(+), 20 deletions(-)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 159a854..e9bdb16 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -418,6 +418,26 @@ static void _clk_pll_disable(struct clk_hw *hw)
}
}
+static void pll_clk_start_ss(struct tegra_clk_pll *pll)
+{
+ if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
+ u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
+
+ val |= pll->params->ssc_ctrl_en_mask;
+ pll_writel(val, pll->params->ssc_ctrl_reg, pll);
+ }
+}
+
+static void pll_clk_stop_ss(struct tegra_clk_pll *pll)
+{
+ if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
+ u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
+
+ val &= ~pll->params->ssc_ctrl_en_mask;
+ pll_writel(val, pll->params->ssc_ctrl_reg, pll);
+ }
+}
+
static int clk_pll_enable(struct clk_hw *hw)
{
struct tegra_clk_pll *pll = to_clk_pll(hw);
@@ -431,6 +451,8 @@ static int clk_pll_enable(struct clk_hw *hw)
ret = clk_pll_wait_for_lock(pll);
+ pll_clk_start_ss(pll);
+
if (pll->lock)
spin_unlock_irqrestore(pll->lock, flags);
@@ -445,6 +467,8 @@ static void clk_pll_disable(struct clk_hw *hw)
if (pll->lock)
spin_lock_irqsave(pll->lock, flags);
+ pll_clk_stop_ss(pll);
+
_clk_pll_disable(hw);
if (pll->lock)
@@ -716,26 +740,6 @@ static void _update_pll_cpcon(struct tegra_clk_pll *pll,
pll_writel_misc(val, pll);
}
-static void pll_clk_start_ss(struct tegra_clk_pll *pll)
-{
- if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
- u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
-
- val |= pll->params->ssc_ctrl_en_mask;
- pll_writel(val, pll->params->ssc_ctrl_reg, pll);
- }
-}
-
-static void pll_clk_stop_ss(struct tegra_clk_pll *pll)
-{
- if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
- u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
-
- val &= ~pll->params->ssc_ctrl_en_mask;
- pll_writel(val, pll->params->ssc_ctrl_reg, pll);
- }
-}
-
static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
unsigned long rate)
{
--
1.9.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
end of thread, other threads:[~2017-05-04 7:42 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2017-04-20 12:39 [PATCH] clk: tegra: fix SS control on PLL enable/disable Peter De Schrijver
2017-04-20 12:39 ` Peter De Schrijver
2017-04-22 2:38 ` Stephen Boyd
2017-05-04 7:42 ` Peter De Schrijver
2017-05-04 7:42 ` Peter De Schrijver
-- strict thread matches above, loose matches on Subject: below --
2017-04-13 13:21 Peter De Schrijver
2017-04-13 13:21 ` Peter De Schrijver
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.