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From: "Michael S. Tsirkin" <mst@redhat.com>
To: Peter Xu <peterx@redhat.com>
Cc: qemu-devel@nongnu.org, Paolo Bonzini <pbonzini@redhat.com>
Subject: Re: [Qemu-devel] [PATCH v2 2/3] msix: trace control bit write op
Date: Wed, 10 May 2017 21:30:42 +0300	[thread overview]
Message-ID: <20170510213037-mutt-send-email-mst@kernel.org> (raw)
In-Reply-To: <1494309644-18743-3-git-send-email-peterx@redhat.com>

On Tue, May 09, 2017 at 02:00:43PM +0800, Peter Xu wrote:
> Meanwhile, abstract a function to detect msix masked bit.
> 
> Signed-off-by: Peter Xu <peterx@redhat.com>

Reviewed-by: Michael S. Tsirkin <mst@redhat.com>

> ---
>  hw/pci/msix.c       | 11 +++++++++--
>  hw/pci/trace-events |  3 +++
>  2 files changed, 12 insertions(+), 2 deletions(-)
> 
> diff --git a/hw/pci/msix.c b/hw/pci/msix.c
> index bb54e8b..fc5fe51 100644
> --- a/hw/pci/msix.c
> +++ b/hw/pci/msix.c
> @@ -22,6 +22,7 @@
>  #include "hw/xen/xen.h"
>  #include "qemu/range.h"
>  #include "qapi/error.h"
> +#include "trace.h"
>  
>  #define MSIX_CAP_LENGTH 12
>  
> @@ -130,10 +131,14 @@ static void msix_handle_mask_update(PCIDevice *dev, int vector, bool was_masked)
>      }
>  }
>  
> +static bool msix_masked(PCIDevice *dev)
> +{
> +    return dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & MSIX_MASKALL_MASK;
> +}
> +
>  static void msix_update_function_masked(PCIDevice *dev)
>  {
> -    dev->msix_function_masked = !msix_enabled(dev) ||
> -        (dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & MSIX_MASKALL_MASK);
> +    dev->msix_function_masked = !msix_enabled(dev) || msix_masked(dev);
>  }
>  
>  /* Handle MSI-X capability config write. */
> @@ -148,6 +153,8 @@ void msix_write_config(PCIDevice *dev, uint32_t addr,
>          return;
>      }
>  
> +    trace_msix_write_config(dev->name, msix_enabled(dev), msix_masked(dev));
> +
>      was_masked = dev->msix_function_masked;
>      msix_update_function_masked(dev);
>  
> diff --git a/hw/pci/trace-events b/hw/pci/trace-events
> index 2b9cf24..83c8f5a 100644
> --- a/hw/pci/trace-events
> +++ b/hw/pci/trace-events
> @@ -7,3 +7,6 @@ pci_update_mappings_add(void *d, uint32_t bus, uint32_t slot, uint32_t func, int
>  # hw/pci/pci_host.c
>  pci_cfg_read(const char *dev, unsigned devid, unsigned fnid, unsigned offs, unsigned val) "%s %02u:%u @0x%x -> 0x%x"
>  pci_cfg_write(const char *dev, unsigned devid, unsigned fnid, unsigned offs, unsigned val) "%s %02u:%u @0x%x <- 0x%x"
> +
> +# hw/pci/msix.c
> +msix_write_config(char *name, bool enabled, bool masked) "dev %s enabled %d masked %d"
> -- 
> 2.7.4

  parent reply	other threads:[~2017-05-10 18:30 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-05-09  6:00 [Qemu-devel] [PATCH v2 0/3] kvm: irqchip: skip msi update when msi disabled Peter Xu
2017-05-09  6:00 ` [Qemu-devel] [PATCH v2 1/3] kvm: irqchip: trace changes on msi add/remove Peter Xu
2017-05-10 10:45   ` Philippe Mathieu-Daudé
2017-05-09  6:00 ` [Qemu-devel] [PATCH v2 2/3] msix: trace control bit write op Peter Xu
2017-05-10 10:44   ` Philippe Mathieu-Daudé
2017-05-10 18:30   ` Michael S. Tsirkin
2017-05-10 18:30   ` Michael S. Tsirkin [this message]
2017-05-09  6:00 ` [Qemu-devel] [PATCH v2 3/3] kvm: irqchip: skip update msi when disabled Peter Xu
2017-05-11  2:56   ` Peter Xu
2017-05-11  7:48     ` Paolo Bonzini
2017-05-11  7:54       ` Peter Xu
2017-05-10 15:32 ` [Qemu-devel] [PATCH v2 0/3] kvm: irqchip: skip msi update when msi disabled Paolo Bonzini

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