[PATCH 00/18] Vega10 S3 following up

[PATCH 00/18] Vega10 S3 following up

[Huang Rui]

Hi all,

These patches refines gfxhub/mmhub programming sequence to make them clear and
readable. And actually, gfxhub + mmhub = GMCv9 for vega10, we don't need
specific gfxhub and mmhub ip blocks, and meanwhile, they have different resume
sequence during gfxhub, mmhub, and gmc. That will make thing confused and easily
miss some register configrations. So remove gfxhub and mmhub ip block here, and
merge them into GMC v9.

Patch 1 -> 8: refine gfxhub/mmhub programming sequence
Patch 9: fix missed invalidation at resume
Patch 10 -> 15: remove gfxhub/mmhub ip blocks
Patch 16 -> 17: add prints to make ip_block mask clear.
Patch 18: fix gart table cleared and other BOs cleared issue which blocked S3.
	(Extend stollen memory for VBIOS)

Huang Rui (18):
  drm/amdgpu: abstract gart table initialization for gfxhub/mmhub
  drm/amdgpu: abstract gart aperture initialization for gfxhub/mmhub
  drm/amdgpu: abstract system aperture initialization for gfxhub/mmhub
  drm/amdgpu: abstract TLB initialization for gfxhub/mmhub
  drm/amdgpu: abstract cache initialization for gfxhub/mmhub
  drm/amdgpu: abstract system domain enablement for gfxhub/mmhub
  drm/amdgpu: abstract disable identity aperture for gfxhub/mmhub
  drm/amdgpu: abstract setup vmid config for gfxhub/mmhub
  drm/amdgpu: fix to miss program invalidation at resume
  drm/amdgpu: export gfxhub sw_init into gmc
  drm/amdgpu: export mmhub sw_init into gmc
  drm/amdgpu: export mmhub set clockgating into gmc
  drm/amdgpu: export mmhub get clockgating into gmc
  drm/amdgpu: remove gfxhub ip
  drm/amdgpu: remove mmhub ip
  drm/amdgpu: add ip name print for selecting ips with ip_block_mask
  drm/amdgpu: add ip block number prints
  drm/amdgpu: fix the gart table cleared issue for S3

 drivers/gpu/drm/amd/amdgpu/amdgpu.h        |   1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |   8 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c    |   2 +-
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c   | 361 +++++++++++-----------------
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h   |   1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c      |   2 +
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c      |   2 +
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c      |   2 +
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c      |  18 +-
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c    | 373 ++++++++++++-----------------
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h    |   4 +
 drivers/gpu/drm/amd/amdgpu/soc15.c         |   2 -
 drivers/gpu/drm/amd/include/amd_shared.h   |   2 -
 13 files changed, 330 insertions(+), 448 deletions(-)

-- 
2.7.4

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[PATCH 01/18] drm/amdgpu: abstract gart table initialization for gfxhub/mmhub

[Huang Rui]

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 33 +++++++++++++++++++-------------
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 33 +++++++++++++++++++-------------
 2 files changed, 40 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index 7c430c4..8cf30b7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -31,6 +31,24 @@
 
 #include "soc15_common.h"
 
+static void gfxhub_v1_0_init_pt_regs(struct amdgpu_device *adev)
+{
+	uint64_t value;
+
+	BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
+	value = adev->gart.table_addr - adev->mc.vram_start
+		+ adev->vm_manager.vram_base_offset;
+	value &= 0x0000FFFFFFFFF000ULL;
+	value |= 0x1; /*valid bit*/
+
+	WREG32(SOC15_REG_OFFSET(GC, 0,
+				mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),
+		(u32)value);
+	WREG32(SOC15_REG_OFFSET(GC, 0,
+				mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),
+		(u32)(value >> 32));
+}
+
 int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
 {
 	u32 tmp;
@@ -38,6 +56,8 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
 	u32 i;
 
 	/* Program MC. */
+	gfxhub_v1_0_init_pt_regs(adev);
+
 	/* Update configuration */
 	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR),
 		adev->mc.vram_start >> 18);
@@ -154,19 +174,6 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
 				mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
 		(u32)(adev->mc.gtt_end >> 44));
 
-	BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
-	value = adev->gart.table_addr - adev->mc.vram_start
-		+ adev->vm_manager.vram_base_offset;
-	value &= 0x0000FFFFFFFFF000ULL;
-	value |= 0x1; /*valid bit*/
-
-	WREG32(SOC15_REG_OFFSET(GC, 0,
-				mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),
-		(u32)value);
-	WREG32(SOC15_REG_OFFSET(GC, 0,
-				mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),
-		(u32)(value >> 32));
-
 	WREG32(SOC15_REG_OFFSET(GC, 0,
 				mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),
 		(u32)(adev->dummy_page.addr >> 12));
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index afd9d85..84eb3a3 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -44,6 +44,24 @@ u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev)
 	return base;
 }
 
+static void mmhub_v1_0_init_pt_regs(struct amdgpu_device *adev)
+{
+	uint64_t value;
+
+	BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
+	value = adev->gart.table_addr - adev->mc.vram_start +
+		adev->vm_manager.vram_base_offset;
+	value &= 0x0000FFFFFFFFF000ULL;
+	value |= 0x1; /* valid bit */
+
+	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
+				mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),
+		(u32)value);
+	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
+				mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),
+		(u32)(value >> 32));
+}
+
 int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
 {
 	u32 tmp;
@@ -52,6 +70,8 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
 	u32 i;
 
 	/* Program MC. */
+	mmhub_v1_0_init_pt_regs(adev);
+
 	/* Update configuration */
 	DRM_INFO("%s -- in\n", __func__);
 	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR),
@@ -168,19 +188,6 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
 				mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
 		(u32)(adev->mc.gtt_end >> 44));
 
-	BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
-	value = adev->gart.table_addr - adev->mc.vram_start +
-		adev->vm_manager.vram_base_offset;
-	value &= 0x0000FFFFFFFFF000ULL;
-	value |= 0x1; /* valid bit */
-
-	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
-				mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),
-		(u32)value);
-	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
-				mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),
-		(u32)(value >> 32));
-
 	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
 				mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),
 		(u32)(adev->dummy_page.addr >> 12));
-- 
2.7.4

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RE: [PATCH 01/18] drm/amdgpu: abstract gart table initialization for gfxhub/mmhub

[Deucher, Alexander]

> -----Original Message-----
> From: Huang Rui [mailto:ray.huang@amd.com]
> Sent: Wednesday, May 31, 2017 12:15 PM
> To: amd-gfx@lists.freedesktop.org; Deucher, Alexander; Koenig, Christian
> Cc: Wang, Ken; Huan, Alvin; Huang, Ray
> Subject: [PATCH 01/18] drm/amdgpu: abstract gart table initialization for
> gfxhub/mmhub
> 
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 33
> +++++++++++++++++++-------------
>  drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 33
> +++++++++++++++++++-------------
>  2 files changed, 40 insertions(+), 26 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> index 7c430c4..8cf30b7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> @@ -31,6 +31,24 @@
> 
>  #include "soc15_common.h"
> 
> +static void gfxhub_v1_0_init_pt_regs(struct amdgpu_device *adev)

Name this function gfxhub_v1_0_init_gart_pt_regs() for consistency.

Alex

> +{
> +	uint64_t value;
> +
> +	BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
> +	value = adev->gart.table_addr - adev->mc.vram_start
> +		+ adev->vm_manager.vram_base_offset;
> +	value &= 0x0000FFFFFFFFF000ULL;
> +	value |= 0x1; /*valid bit*/
> +
> +	WREG32(SOC15_REG_OFFSET(GC, 0,
> +
> 	mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),
> +		(u32)value);
> +	WREG32(SOC15_REG_OFFSET(GC, 0,
> +
> 	mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),
> +		(u32)(value >> 32));
> +}
> +
>  int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
>  {
>  	u32 tmp;
> @@ -38,6 +56,8 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device
> *adev)
>  	u32 i;
> 
>  	/* Program MC. */
> +	gfxhub_v1_0_init_pt_regs(adev);
> +
>  	/* Update configuration */
>  	WREG32(SOC15_REG_OFFSET(GC, 0,
> mmMC_VM_SYSTEM_APERTURE_LOW_ADDR),
>  		adev->mc.vram_start >> 18);
> @@ -154,19 +174,6 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device
> *adev)
> 
> 	mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
>  		(u32)(adev->mc.gtt_end >> 44));
> 
> -	BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
> -	value = adev->gart.table_addr - adev->mc.vram_start
> -		+ adev->vm_manager.vram_base_offset;
> -	value &= 0x0000FFFFFFFFF000ULL;
> -	value |= 0x1; /*valid bit*/
> -
> -	WREG32(SOC15_REG_OFFSET(GC, 0,
> -
> 	mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),
> -		(u32)value);
> -	WREG32(SOC15_REG_OFFSET(GC, 0,
> -
> 	mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),
> -		(u32)(value >> 32));
> -
>  	WREG32(SOC15_REG_OFFSET(GC, 0,
> 
> 	mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),
>  		(u32)(adev->dummy_page.addr >> 12));
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> index afd9d85..84eb3a3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> @@ -44,6 +44,24 @@ u64 mmhub_v1_0_get_fb_location(struct
> amdgpu_device *adev)
>  	return base;
>  }
> 
> +static void mmhub_v1_0_init_pt_regs(struct amdgpu_device *adev)
> +{
> +	uint64_t value;
> +
> +	BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
> +	value = adev->gart.table_addr - adev->mc.vram_start +
> +		adev->vm_manager.vram_base_offset;
> +	value &= 0x0000FFFFFFFFF000ULL;
> +	value |= 0x1; /* valid bit */
> +
> +	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> +
> 	mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),
> +		(u32)value);
> +	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> +
> 	mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),
> +		(u32)(value >> 32));
> +}
> +
>  int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
>  {
>  	u32 tmp;
> @@ -52,6 +70,8 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device
> *adev)
>  	u32 i;
> 
>  	/* Program MC. */
> +	mmhub_v1_0_init_pt_regs(adev);
> +
>  	/* Update configuration */
>  	DRM_INFO("%s -- in\n", __func__);
>  	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> mmMC_VM_SYSTEM_APERTURE_LOW_ADDR),
> @@ -168,19 +188,6 @@ int mmhub_v1_0_gart_enable(struct
> amdgpu_device *adev)
> 
> 	mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
>  		(u32)(adev->mc.gtt_end >> 44));
> 
> -	BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
> -	value = adev->gart.table_addr - adev->mc.vram_start +
> -		adev->vm_manager.vram_base_offset;
> -	value &= 0x0000FFFFFFFFF000ULL;
> -	value |= 0x1; /* valid bit */
> -
> -	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> -
> 	mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),
> -		(u32)value);
> -	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> -
> 	mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),
> -		(u32)(value >> 32));
> -
>  	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> 
> 	mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),
>  		(u32)(adev->dummy_page.addr >> 12));
> --
> 2.7.4

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Re: [PATCH 01/18] drm/amdgpu: abstract gart table initialization for gfxhub/mmhub

[Christian König]

Am 31.05.2017 um 18:14 schrieb Huang Rui:
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 33 +++++++++++++++++++-------------
>   drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 33 +++++++++++++++++++-------------
>   2 files changed, 40 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> index 7c430c4..8cf30b7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> @@ -31,6 +31,24 @@
>   
>   #include "soc15_common.h"
>   
> +static void gfxhub_v1_0_init_pt_regs(struct amdgpu_device *adev)
> +{
> +	uint64_t value;
> +
> +	BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
> +	value = adev->gart.table_addr - adev->mc.vram_start
> +		+ adev->vm_manager.vram_base_offset;
> +	value &= 0x0000FFFFFFFFF000ULL;
> +	value |= 0x1; /*valid bit*/
> +
> +	WREG32(SOC15_REG_OFFSET(GC, 0,
> +				mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),
> +		(u32)value);
> +	WREG32(SOC15_REG_OFFSET(GC, 0,
> +				mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),
> +		(u32)(value >> 32));
> +}
> +
>   int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
>   {
>   	u32 tmp;
> @@ -38,6 +56,8 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
>   	u32 i;
>   
>   	/* Program MC. */
> +	gfxhub_v1_0_init_pt_regs(adev);
> +
>   	/* Update configuration */
>   	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR),
>   		adev->mc.vram_start >> 18);
> @@ -154,19 +174,6 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
>   				mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
>   		(u32)(adev->mc.gtt_end >> 44));
>   
> -	BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
> -	value = adev->gart.table_addr - adev->mc.vram_start
> -		+ adev->vm_manager.vram_base_offset;
> -	value &= 0x0000FFFFFFFFF000ULL;
> -	value |= 0x1; /*valid bit*/
> -
> -	WREG32(SOC15_REG_OFFSET(GC, 0,
> -				mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),
> -		(u32)value);
> -	WREG32(SOC15_REG_OFFSET(GC, 0,
> -				mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),
> -		(u32)(value >> 32));
> -
>   	WREG32(SOC15_REG_OFFSET(GC, 0,
>   				mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),
>   		(u32)(adev->dummy_page.addr >> 12));
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> index afd9d85..84eb3a3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> @@ -44,6 +44,24 @@ u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev)
>   	return base;
>   }
>   
> +static void mmhub_v1_0_init_pt_regs(struct amdgpu_device *adev)
> +{
> +	uint64_t value;
> +
> +	BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
> +	value = adev->gart.table_addr - adev->mc.vram_start +
> +		adev->vm_manager.vram_base_offset;
> +	value &= 0x0000FFFFFFFFF000ULL;
> +	value |= 0x1; /* valid bit */
> +
> +	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> +				mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),
> +		(u32)value);
> +	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> +				mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),
> +		(u32)(value >> 32));

While at it please use the upper_32_bits() and lower_32_bits() macros 
for this.

Additional to that since you cleanup the code anyway (which is very 
appreciated!) please use the WREG32_SOC15() macro instead.

Regards,
Christian.

> +}
> +
>   int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
>   {
>   	u32 tmp;
> @@ -52,6 +70,8 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
>   	u32 i;
>   
>   	/* Program MC. */
> +	mmhub_v1_0_init_pt_regs(adev);
> +
>   	/* Update configuration */
>   	DRM_INFO("%s -- in\n", __func__);
>   	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR),
> @@ -168,19 +188,6 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
>   				mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
>   		(u32)(adev->mc.gtt_end >> 44));
>   
> -	BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
> -	value = adev->gart.table_addr - adev->mc.vram_start +
> -		adev->vm_manager.vram_base_offset;
> -	value &= 0x0000FFFFFFFFF000ULL;
> -	value |= 0x1; /* valid bit */
> -
> -	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> -				mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),
> -		(u32)value);
> -	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> -				mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),
> -		(u32)(value >> 32));
> -
>   	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
>   				mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),
>   		(u32)(adev->dummy_page.addr >> 12));


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Re: [PATCH 01/18] drm/amdgpu: abstract gart table initialization for gfxhub/mmhub

[Huang Rui]

On Thu, Jun 01, 2017 at 01:02:18AM +0800, Koenig, Christian wrote:
> Am 31.05.2017 um 18:14 schrieb Huang Rui:
> > Signed-off-by: Huang Rui <ray.huang@amd.com>
> > ---
> >   drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 33
> +++++++++++++++++++-------------
> >   drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 33
> +++++++++++++++++++-------------
> >   2 files changed, 40 insertions(+), 26 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/
> amdgpu/gfxhub_v1_0.c
> > index 7c430c4..8cf30b7 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> > @@ -31,6 +31,24 @@
> >  
> >   #include "soc15_common.h"
> >  
> > +static void gfxhub_v1_0_init_pt_regs(struct amdgpu_device *adev)
> > +{
> > +     uint64_t value;
> > +
> > +     BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
> > +     value = adev->gart.table_addr - adev->mc.vram_start
> > +             + adev->vm_manager.vram_base_offset;
> > +     value &= 0x0000FFFFFFFFF000ULL;
> > +     value |= 0x1; /*valid bit*/
> > +
> > +     WREG32(SOC15_REG_OFFSET(GC, 0,
> > +                             mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),
> > +             (u32)value);
> > +     WREG32(SOC15_REG_OFFSET(GC, 0,
> > +                             mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),
> > +             (u32)(value >> 32));
> > +}
> > +
> >   int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
> >   {
> >        u32 tmp;
> > @@ -38,6 +56,8 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
> >        u32 i;
> >  
> >        /* Program MC. */
> > +     gfxhub_v1_0_init_pt_regs(adev);
> > +
> >        /* Update configuration */
> >        WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR),
> >                adev->mc.vram_start >> 18);
> > @@ -154,19 +174,6 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
> >                                mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
> >                (u32)(adev->mc.gtt_end >> 44));
> >  
> > -     BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
> > -     value = adev->gart.table_addr - adev->mc.vram_start
> > -             + adev->vm_manager.vram_base_offset;
> > -     value &= 0x0000FFFFFFFFF000ULL;
> > -     value |= 0x1; /*valid bit*/
> > -
> > -     WREG32(SOC15_REG_OFFSET(GC, 0,
> > -                             mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),
> > -             (u32)value);
> > -     WREG32(SOC15_REG_OFFSET(GC, 0,
> > -                             mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),
> > -             (u32)(value >> 32));
> > -
> >        WREG32(SOC15_REG_OFFSET(GC, 0,
> >                                mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),
> >                (u32)(adev->dummy_page.addr >> 12));
> > diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/
> amdgpu/mmhub_v1_0.c
> > index afd9d85..84eb3a3 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> > @@ -44,6 +44,24 @@ u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev)
> >        return base;
> >   }
> >  
> > +static void mmhub_v1_0_init_pt_regs(struct amdgpu_device *adev)
> > +{
> > +     uint64_t value;
> > +
> > +     BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
> > +     value = adev->gart.table_addr - adev->mc.vram_start +
> > +             adev->vm_manager.vram_base_offset;
> > +     value &= 0x0000FFFFFFFFF000ULL;
> > +     value |= 0x1; /* valid bit */
> > +
> > +     WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> > +                             mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),
> > +             (u32)value);
> > +     WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> > +                             mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),
> > +             (u32)(value >> 32));
> 
> While at it please use the upper_32_bits() and lower_32_bits() macros
> for this.
> 
> Additional to that since you cleanup the code anyway (which is very
> appreciated!) please use the WREG32_SOC15() macro instead.
> 

My pleasure. I found original mmhub/gfxhub programming sequence was really
hard to read when I was debugging S3 issue. So I have to break it down to
make it clearly. 

Could I add one more patches at top of patch set to use
WREG32_SOC15/REG32_SOC15 instead for the whole GMC, GFXHUB, and MMHUB
blocks.

Thanks,
Ray
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Re: [PATCH 01/18] drm/amdgpu: abstract gart table initialization for gfxhub/mmhub

[zhoucm1]

On 2017年06月01日 00:14, Huang Rui wrote:
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 33 +++++++++++++++++++-------------
>   drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 33 +++++++++++++++++++-------------
>   2 files changed, 40 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> index 7c430c4..8cf30b7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> @@ -31,6 +31,24 @@
>   
>   #include "soc15_common.h"
>   
> +static void gfxhub_v1_0_init_pt_regs(struct amdgpu_device *adev)
> +{
> +	uint64_t value;
> +
> +	BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
> +	value = adev->gart.table_addr - adev->mc.vram_start
> +		+ adev->vm_manager.vram_base_offset;
> +	value &= 0x0000FFFFFFFFF000ULL;
> +	value |= 0x1; /*valid bit*/
> +
> +	WREG32(SOC15_REG_OFFSET(GC, 0,
> +				mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),
> +		(u32)value);
> +	WREG32(SOC15_REG_OFFSET(GC, 0,
> +				mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),
> +		(u32)(value >> 32));
> +}
> +
>   int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
>   {
>   	u32 tmp;
> @@ -38,6 +56,8 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
>   	u32 i;
>   
>   	/* Program MC. */
> +	gfxhub_v1_0_init_pt_regs(adev);
> +
abstraction is fine, but why you change code location?

Regards,
David Zhou
>   	/* Update configuration */
>   	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR),
>   		adev->mc.vram_start >> 18);
> @@ -154,19 +174,6 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
>   				mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
>   		(u32)(adev->mc.gtt_end >> 44));
>   
> -	BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
> -	value = adev->gart.table_addr - adev->mc.vram_start
> -		+ adev->vm_manager.vram_base_offset;
> -	value &= 0x0000FFFFFFFFF000ULL;
> -	value |= 0x1; /*valid bit*/
> -
> -	WREG32(SOC15_REG_OFFSET(GC, 0,
> -				mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),
> -		(u32)value);
> -	WREG32(SOC15_REG_OFFSET(GC, 0,
> -				mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),
> -		(u32)(value >> 32));
> -
>   	WREG32(SOC15_REG_OFFSET(GC, 0,
>   				mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),
>   		(u32)(adev->dummy_page.addr >> 12));
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> index afd9d85..84eb3a3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> @@ -44,6 +44,24 @@ u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev)
>   	return base;
>   }
>   
> +static void mmhub_v1_0_init_pt_regs(struct amdgpu_device *adev)
> +{
> +	uint64_t value;
> +
> +	BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
> +	value = adev->gart.table_addr - adev->mc.vram_start +
> +		adev->vm_manager.vram_base_offset;
> +	value &= 0x0000FFFFFFFFF000ULL;
> +	value |= 0x1; /* valid bit */
> +
> +	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> +				mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),
> +		(u32)value);
> +	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> +				mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),
> +		(u32)(value >> 32));
> +}
> +
>   int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
>   {
>   	u32 tmp;
> @@ -52,6 +70,8 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
>   	u32 i;
>   
>   	/* Program MC. */
> +	mmhub_v1_0_init_pt_regs(adev);
> +
>   	/* Update configuration */
>   	DRM_INFO("%s -- in\n", __func__);
>   	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR),
> @@ -168,19 +188,6 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
>   				mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
>   		(u32)(adev->mc.gtt_end >> 44));
>   
> -	BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
> -	value = adev->gart.table_addr - adev->mc.vram_start +
> -		adev->vm_manager.vram_base_offset;
> -	value &= 0x0000FFFFFFFFF000ULL;
> -	value |= 0x1; /* valid bit */
> -
> -	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> -				mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),
> -		(u32)value);
> -	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> -				mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),
> -		(u32)(value >> 32));
> -
>   	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
>   				mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),
>   		(u32)(adev->dummy_page.addr >> 12));

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Re: [PATCH 01/18] drm/amdgpu: abstract gart table initialization for gfxhub/mmhub

[Huang Rui]

On Thu, Jun 01, 2017 at 12:19:19PM +0800, zhoucm1 wrote:
> 
> 
> On 2017年06月01日 00:14, Huang Rui wrote:
> >Signed-off-by: Huang Rui <ray.huang@amd.com>
> >---
> >  drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 33 +++++++++++++++++++-------------
> >  drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 33 +++++++++++++++++++-------------
> >  2 files changed, 40 insertions(+), 26 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> >index 7c430c4..8cf30b7 100644
> >--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> >+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> >@@ -31,6 +31,24 @@
> >  #include "soc15_common.h"
> >+static void gfxhub_v1_0_init_pt_regs(struct amdgpu_device *adev)
> >+{
> >+	uint64_t value;
> >+
> >+	BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
> >+	value = adev->gart.table_addr - adev->mc.vram_start
> >+		+ adev->vm_manager.vram_base_offset;
> >+	value &= 0x0000FFFFFFFFF000ULL;
> >+	value |= 0x1; /*valid bit*/
> >+
> >+	WREG32(SOC15_REG_OFFSET(GC, 0,
> >+				mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),
> >+		(u32)value);
> >+	WREG32(SOC15_REG_OFFSET(GC, 0,
> >+				mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),
> >+		(u32)(value >> 32));
> >+}
> >+
> >  int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
> >  {
> >  	u32 tmp;
> >@@ -38,6 +56,8 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
> >  	u32 i;
> >  	/* Program MC. */
> >+	gfxhub_v1_0_init_pt_regs(adev);
> >+
> abstraction is fine, but why you change code location?
> 

Because we would better to align the programming sequence with windows
part. That's helpful to debug in future.

Thanks,
Ray
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Re: [PATCH 01/18] drm/amdgpu: abstract gart table initialization for gfxhub/mmhub

[zhoucm1]

On 2017年06月01日 13:29, Huang Rui wrote:
> On Thu, Jun 01, 2017 at 12:19:19PM +0800, zhoucm1 wrote:
>>
>> On 2017年06月01日 00:14, Huang Rui wrote:
>>> Signed-off-by: Huang Rui <ray.huang@amd.com>
>>> ---
>>>   drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 33 +++++++++++++++++++-------------
>>>   drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 33 +++++++++++++++++++-------------
>>>   2 files changed, 40 insertions(+), 26 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>>> index 7c430c4..8cf30b7 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>>> @@ -31,6 +31,24 @@
>>>   #include "soc15_common.h"
>>> +static void gfxhub_v1_0_init_pt_regs(struct amdgpu_device *adev)
>>> +{
>>> +	uint64_t value;
>>> +
>>> +	BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
>>> +	value = adev->gart.table_addr - adev->mc.vram_start
>>> +		+ adev->vm_manager.vram_base_offset;
>>> +	value &= 0x0000FFFFFFFFF000ULL;
>>> +	value |= 0x1; /*valid bit*/
>>> +
>>> +	WREG32(SOC15_REG_OFFSET(GC, 0,
>>> +				mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),
>>> +		(u32)value);
>>> +	WREG32(SOC15_REG_OFFSET(GC, 0,
>>> +				mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),
>>> +		(u32)(value >> 32));
>>> +}
>>> +
>>>   int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
>>>   {
>>>   	u32 tmp;
>>> @@ -38,6 +56,8 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
>>>   	u32 i;
>>>   	/* Program MC. */
>>> +	gfxhub_v1_0_init_pt_regs(adev);
>>> +
>> abstraction is fine, but why you change code location?
>>
> Because we would better to align the programming sequence with windows
> part.
If you make sure it aligns with windows, then that's good. Otherwise we 
should keep same with previous.

Regards,
David Zhou
> That's helpful to debug in future.
>
> Thanks,
> Ray

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[PATCH 02/18] drm/amdgpu: abstract gart aperture initialization for gfxhub/mmhub

[Huang Rui]

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 34 +++++++++++++++++---------------
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 33 +++++++++++++++++--------------
 2 files changed, 36 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index 8cf30b7..b21607c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -49,6 +49,23 @@ static void gfxhub_v1_0_init_pt_regs(struct amdgpu_device *adev)
 		(u32)(value >> 32));
 }
 
+static void gfxhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
+{
+	WREG32(SOC15_REG_OFFSET(GC, 0,
+				mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),
+		(u32)(adev->mc.gtt_start >> 12));
+	WREG32(SOC15_REG_OFFSET(GC, 0,
+				mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),
+		(u32)(adev->mc.gtt_start >> 44));
+
+	WREG32(SOC15_REG_OFFSET(GC, 0,
+				mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),
+		(u32)(adev->mc.gtt_end >> 12));
+	WREG32(SOC15_REG_OFFSET(GC, 0,
+				mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
+		(u32)(adev->mc.gtt_end >> 44));
+}
+
 int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
 {
 	u32 tmp;
@@ -57,8 +74,8 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
 
 	/* Program MC. */
 	gfxhub_v1_0_init_pt_regs(adev);
+	gfxhub_v1_0_init_gart_aperture_regs(adev);
 
-	/* Update configuration */
 	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR),
 		adev->mc.vram_start >> 18);
 	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR),
@@ -159,21 +176,6 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
 			    0);
 	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL4), tmp);
 
-	/* setup context0 */
-	WREG32(SOC15_REG_OFFSET(GC, 0,
-				mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),
-		(u32)(adev->mc.gtt_start >> 12));
-	WREG32(SOC15_REG_OFFSET(GC, 0,
-				mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),
-		(u32)(adev->mc.gtt_start >> 44));
-
-	WREG32(SOC15_REG_OFFSET(GC, 0,
-				mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),
-		(u32)(adev->mc.gtt_end >> 12));
-	WREG32(SOC15_REG_OFFSET(GC, 0,
-				mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
-		(u32)(adev->mc.gtt_end >> 44));
-
 	WREG32(SOC15_REG_OFFSET(GC, 0,
 				mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),
 		(u32)(adev->dummy_page.addr >> 12));
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index 84eb3a3..84cdca2 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -62,6 +62,23 @@ static void mmhub_v1_0_init_pt_regs(struct amdgpu_device *adev)
 		(u32)(value >> 32));
 }
 
+static void mmhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
+{
+	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
+				mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),
+		(u32)(adev->mc.gtt_start >> 12));
+	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
+				mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),
+		(u32)(adev->mc.gtt_start >> 44));
+
+	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
+				mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),
+		(u32)(adev->mc.gtt_end >> 12));
+	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
+				mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
+		(u32)(adev->mc.gtt_end >> 44));
+}
+
 int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
 {
 	u32 tmp;
@@ -71,6 +88,7 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
 
 	/* Program MC. */
 	mmhub_v1_0_init_pt_regs(adev);
+	mmhub_v1_0_init_gart_aperture_regs(adev);
 
 	/* Update configuration */
 	DRM_INFO("%s -- in\n", __func__);
@@ -173,21 +191,6 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
 			    0);
 	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL4), tmp);
 
-	/* setup context0 */
-	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
-				mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),
-		(u32)(adev->mc.gtt_start >> 12));
-	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
-				mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),
-		(u32)(adev->mc.gtt_start >> 44));
-
-	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
-				mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),
-		(u32)(adev->mc.gtt_end >> 12));
-	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
-				mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
-		(u32)(adev->mc.gtt_end >> 44));
-
 	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
 				mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),
 		(u32)(adev->dummy_page.addr >> 12));
-- 
2.7.4

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RE: [PATCH 02/18] drm/amdgpu: abstract gart aperture initialization for gfxhub/mmhub

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Huang Rui
> Sent: Wednesday, May 31, 2017 12:15 PM
> To: amd-gfx@lists.freedesktop.org; Deucher, Alexander; Koenig, Christian
> Cc: Wang, Ken; Huang, Ray; Huan, Alvin
> Subject: [PATCH 02/18] drm/amdgpu: abstract gart aperture initialization for
> gfxhub/mmhub
> 
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 34 +++++++++++++++++--
> -------------
>  drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 33 +++++++++++++++++-
> -------------
>  2 files changed, 36 insertions(+), 31 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> index 8cf30b7..b21607c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> @@ -49,6 +49,23 @@ static void gfxhub_v1_0_init_pt_regs(struct
> amdgpu_device *adev)
>  		(u32)(value >> 32));
>  }
> 
> +static void gfxhub_v1_0_init_gart_aperture_regs(struct amdgpu_device
> *adev)

I think we can merge code from patch 1 into this function as well rather than having two functions since the page table base is technically part of the gart aperture.  Same for mmhub.

Alex

> +{
> +	WREG32(SOC15_REG_OFFSET(GC, 0,
> +
> 	mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),
> +		(u32)(adev->mc.gtt_start >> 12));
> +	WREG32(SOC15_REG_OFFSET(GC, 0,
> +
> 	mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),
> +		(u32)(adev->mc.gtt_start >> 44));
> +
> +	WREG32(SOC15_REG_OFFSET(GC, 0,
> +
> 	mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),
> +		(u32)(adev->mc.gtt_end >> 12));
> +	WREG32(SOC15_REG_OFFSET(GC, 0,
> +
> 	mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
> +		(u32)(adev->mc.gtt_end >> 44));
> +}
> +
>  int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
>  {
>  	u32 tmp;
> @@ -57,8 +74,8 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device
> *adev)
> 
>  	/* Program MC. */
>  	gfxhub_v1_0_init_pt_regs(adev);
> +	gfxhub_v1_0_init_gart_aperture_regs(adev);
> 
> -	/* Update configuration */
>  	WREG32(SOC15_REG_OFFSET(GC, 0,
> mmMC_VM_SYSTEM_APERTURE_LOW_ADDR),
>  		adev->mc.vram_start >> 18);
>  	WREG32(SOC15_REG_OFFSET(GC, 0,
> mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR),
> @@ -159,21 +176,6 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device
> *adev)
>  			    0);
>  	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL4), tmp);
> 
> -	/* setup context0 */
> -	WREG32(SOC15_REG_OFFSET(GC, 0,
> -
> 	mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),
> -		(u32)(adev->mc.gtt_start >> 12));
> -	WREG32(SOC15_REG_OFFSET(GC, 0,
> -
> 	mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),
> -		(u32)(adev->mc.gtt_start >> 44));
> -
> -	WREG32(SOC15_REG_OFFSET(GC, 0,
> -
> 	mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),
> -		(u32)(adev->mc.gtt_end >> 12));
> -	WREG32(SOC15_REG_OFFSET(GC, 0,
> -
> 	mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
> -		(u32)(adev->mc.gtt_end >> 44));
> -
>  	WREG32(SOC15_REG_OFFSET(GC, 0,
> 
> 	mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),
>  		(u32)(adev->dummy_page.addr >> 12));
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> index 84eb3a3..84cdca2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> @@ -62,6 +62,23 @@ static void mmhub_v1_0_init_pt_regs(struct
> amdgpu_device *adev)
>  		(u32)(value >> 32));
>  }
> 
> +static void mmhub_v1_0_init_gart_aperture_regs(struct amdgpu_device
> *adev)
> +{
> +	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> +
> 	mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),
> +		(u32)(adev->mc.gtt_start >> 12));
> +	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> +
> 	mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),
> +		(u32)(adev->mc.gtt_start >> 44));
> +
> +	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> +
> 	mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),
> +		(u32)(adev->mc.gtt_end >> 12));
> +	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> +
> 	mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
> +		(u32)(adev->mc.gtt_end >> 44));
> +}
> +
>  int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
>  {
>  	u32 tmp;
> @@ -71,6 +88,7 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device
> *adev)
> 
>  	/* Program MC. */
>  	mmhub_v1_0_init_pt_regs(adev);
> +	mmhub_v1_0_init_gart_aperture_regs(adev);
> 
>  	/* Update configuration */
>  	DRM_INFO("%s -- in\n", __func__);
> @@ -173,21 +191,6 @@ int mmhub_v1_0_gart_enable(struct
> amdgpu_device *adev)
>  			    0);
>  	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL4), tmp);
> 
> -	/* setup context0 */
> -	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> -
> 	mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),
> -		(u32)(adev->mc.gtt_start >> 12));
> -	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> -
> 	mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),
> -		(u32)(adev->mc.gtt_start >> 44));
> -
> -	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> -
> 	mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),
> -		(u32)(adev->mc.gtt_end >> 12));
> -	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> -
> 	mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
> -		(u32)(adev->mc.gtt_end >> 44));
> -
>  	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> 
> 	mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),
>  		(u32)(adev->dummy_page.addr >> 12));
> --
> 2.7.4
> 
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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[PATCH 03/18] drm/amdgpu: abstract system aperture initialization for gfxhub/mmhub

[Huang Rui]

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c |  61 ++++++++++---------
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 101 ++++++++++++++-----------------
 2 files changed, 81 insertions(+), 81 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index b21607c..523a769 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -66,30 +66,52 @@ static void gfxhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
 		(u32)(adev->mc.gtt_end >> 44));
 }
 
-int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
+static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
 {
-	u32 tmp;
-	u64 value;
-	u32 i;
+	uint64_t value;
+	uint32_t tmp;
 
-	/* Program MC. */
-	gfxhub_v1_0_init_pt_regs(adev);
-	gfxhub_v1_0_init_gart_aperture_regs(adev);
+	/* Disable AGP. */
+	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_BASE), 0);
+	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_TOP), 0);
+	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_BOT), 0xFFFFFFFF);
 
+	/* Program the system aperture low logical page number. */
 	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR),
 		adev->mc.vram_start >> 18);
 	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR),
 		adev->mc.vram_end >> 18);
 
+	/* Set default page address. */
 	value = adev->vram_scratch.gpu_addr - adev->mc.vram_start
 		+ adev->vm_manager.vram_base_offset;
 	WREG32(SOC15_REG_OFFSET(GC, 0,
 				mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB),
-				(u32)(value >> 12));
+	       (u32)(value >> 12));
 	WREG32(SOC15_REG_OFFSET(GC, 0,
 				mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),
-				(u32)(value >> 44));
+	       (u32)(value >> 44));
 
+	/* Program "protection fault". */
+	WREG32(SOC15_REG_OFFSET(GC, 0,
+				mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),
+	       (u32)(adev->dummy_page.addr >> 12));
+	WREG32(SOC15_REG_OFFSET(GC, 0,
+				mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),
+	       (u32)((u64)adev->dummy_page.addr >> 44));
+
+	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL2));
+	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
+			    ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
+	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL2), tmp);
+}
+
+int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
+{
+	u32 tmp;
+	u32 i;
+
+	DRM_INFO("%s -- in\n", __func__);
 	if (amdgpu_sriov_vf(adev)) {
 		/* MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are VF copy registers so
 		vbios post doesn't program them, for SRIOV driver need to program them */
@@ -99,12 +121,10 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
 				adev->mc.vram_end >> 24);
 	}
 
-	/* Disable AGP. */
-	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_BASE), 0);
-	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_TOP), 0);
-	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_BOT), 0xFFFFFFFF);
-
 	/* GART Enable. */
+	gfxhub_v1_0_init_pt_regs(adev);
+	gfxhub_v1_0_init_gart_aperture_regs(adev);
+	gfxhub_v1_0_init_system_aperture_regs(adev);
 
 	/* Setup TLB control */
 	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL));
@@ -176,19 +196,6 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
 			    0);
 	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL4), tmp);
 
-	WREG32(SOC15_REG_OFFSET(GC, 0,
-				mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),
-		(u32)(adev->dummy_page.addr >> 12));
-	WREG32(SOC15_REG_OFFSET(GC, 0,
-				mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),
-		(u32)((u64)adev->dummy_page.addr >> 44));
-
-	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL2));
-	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
-			    ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY,
-			    1);
-	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL2), tmp);
-
 	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL));
 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index 84cdca2..df49f32 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -79,32 +79,53 @@ static void mmhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
 		(u32)(adev->mc.gtt_end >> 44));
 }
 
-int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
+static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
 {
-	u32 tmp;
-	u64 value;
-	uint64_t addr;
-	u32 i;
+	uint64_t value;
+	uint32_t tmp;
 
-	/* Program MC. */
-	mmhub_v1_0_init_pt_regs(adev);
-	mmhub_v1_0_init_gart_aperture_regs(adev);
+	/* Disable AGP. */
+	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_AGP_BASE), 0);
+	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_AGP_TOP), 0);
+	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_AGP_BOT), 0x00FFFFFF);
 
-	/* Update configuration */
-	DRM_INFO("%s -- in\n", __func__);
+	/* Program the system aperture low logical page number. */
 	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR),
 		adev->mc.vram_start >> 18);
 	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR),
 		adev->mc.vram_end >> 18);
+
+	/* Set default page address. */
 	value = adev->vram_scratch.gpu_addr - adev->mc.vram_start +
 		adev->vm_manager.vram_base_offset;
 	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
 				mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB),
-				(u32)(value >> 12));
+	       (u32)(value >> 12));
 	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
 				mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),
-				(u32)(value >> 44));
+	       (u32)(value >> 44));
 
+	/* Program "protection fault". */
+	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
+				mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),
+	       (u32)(adev->dummy_page.addr >> 12));
+	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
+				mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),
+	       (u32)((u64)adev->dummy_page.addr >> 44));
+
+	tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2));
+	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
+			    ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
+	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2), tmp);
+}
+
+int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
+{
+	u32 tmp;
+	uint64_t addr;
+	u32 i;
+
+	DRM_INFO("%s -- in\n", __func__);
 	if (amdgpu_sriov_vf(adev)) {
 		/* MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are VF copy registers so
 		vbios post doesn't program them, for SRIOV driver need to program them */
@@ -114,40 +135,25 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
 			adev->mc.vram_end >> 24);
 	}
 
-	/* Disable AGP. */
-	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_AGP_BASE), 0);
-	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_AGP_TOP), 0);
-	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_AGP_BOT), 0x00FFFFFF);
-
 	/* GART Enable. */
+	mmhub_v1_0_init_pt_regs(adev);
+	mmhub_v1_0_init_gart_aperture_regs(adev);
+	mmhub_v1_0_init_system_aperture_regs(adev);
 
 	/* Setup TLB control */
 	tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL));
+
 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
-	tmp = REG_SET_FIELD(tmp,
-				MC_VM_MX_L1_TLB_CNTL,
-				SYSTEM_ACCESS_MODE,
-				3);
-	tmp = REG_SET_FIELD(tmp,
-				MC_VM_MX_L1_TLB_CNTL,
-				ENABLE_ADVANCED_DRIVER_MODEL,
-				1);
-	tmp = REG_SET_FIELD(tmp,
-				MC_VM_MX_L1_TLB_CNTL,
-				SYSTEM_APERTURE_UNMAPPED_ACCESS,
-				0);
-	tmp = REG_SET_FIELD(tmp,
-				MC_VM_MX_L1_TLB_CNTL,
-				ECO_BITS,
-				0);
-	tmp = REG_SET_FIELD(tmp,
-				MC_VM_MX_L1_TLB_CNTL,
-				MTYPE,
-				MTYPE_UC);/* XXX for emulation. */
-	tmp = REG_SET_FIELD(tmp,
-				MC_VM_MX_L1_TLB_CNTL,
-				ATC_EN,
-				1);
+	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
+	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
+			    ENABLE_ADVANCED_DRIVER_MODEL, 1);
+	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
+			    SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
+	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
+	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
+			    MTYPE, MTYPE_UC);/* XXX for emulation. */
+	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
+
 	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp);
 
 	/* Setup L2 cache */
@@ -191,19 +197,6 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
 			    0);
 	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL4), tmp);
 
-	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
-				mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),
-		(u32)(adev->dummy_page.addr >> 12));
-	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
-				mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),
-		(u32)((u64)adev->dummy_page.addr >> 44));
-
-	tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2));
-	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
-			    ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY,
-			    1);
-	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2), tmp);
-
 	addr = SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL);
 	tmp = RREG32(addr);
 
-- 
2.7.4

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[PATCH 04/18] drm/amdgpu: abstract TLB initialization for gfxhub/mmhub

[Huang Rui]

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 51 ++++++++++++++------------------
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 22 ++++++++++++++
 2 files changed, 44 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index 523a769..b92fa63 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -106,6 +106,27 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
 	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL2), tmp);
 }
 
+static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)
+{
+	uint32_t tmp;
+
+	/* Setup TLB control */
+	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL));
+
+	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
+	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
+	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
+			    ENABLE_ADVANCED_DRIVER_MODEL, 1);
+	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
+			    SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
+	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
+	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
+			    MTYPE, MTYPE_UC);/* XXX for emulation. */
+	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
+
+	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp);
+}
+
 int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
 {
 	u32 tmp;
@@ -125,35 +146,7 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
 	gfxhub_v1_0_init_pt_regs(adev);
 	gfxhub_v1_0_init_gart_aperture_regs(adev);
 	gfxhub_v1_0_init_system_aperture_regs(adev);
-
-	/* Setup TLB control */
-	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL));
-	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
-	tmp = REG_SET_FIELD(tmp,
-				MC_VM_MX_L1_TLB_CNTL,
-				SYSTEM_ACCESS_MODE,
-				3);
-	tmp = REG_SET_FIELD(tmp,
-				MC_VM_MX_L1_TLB_CNTL,
-				ENABLE_ADVANCED_DRIVER_MODEL,
-				1);
-	tmp = REG_SET_FIELD(tmp,
-				MC_VM_MX_L1_TLB_CNTL,
-				SYSTEM_APERTURE_UNMAPPED_ACCESS,
-				0);
-	tmp = REG_SET_FIELD(tmp,
-				MC_VM_MX_L1_TLB_CNTL,
-				ECO_BITS,
-				0);
-	tmp = REG_SET_FIELD(tmp,
-				MC_VM_MX_L1_TLB_CNTL,
-				MTYPE,
-				MTYPE_UC);/* XXX for emulation. */
-	tmp = REG_SET_FIELD(tmp,
-				MC_VM_MX_L1_TLB_CNTL,
-				ATC_EN,
-				1);
-	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp);
+	gfxhub_v1_0_init_tlb_regs(adev);
 
 	/* Setup L2 cache */
 	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL));
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index df49f32..a148d6e 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -119,6 +119,27 @@ static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
 	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2), tmp);
 }
 
+static void mmhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)
+{
+	uint32_t tmp;
+
+	/* Setup TLB control */
+	tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL));
+
+	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
+	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
+	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
+			    ENABLE_ADVANCED_DRIVER_MODEL, 1);
+	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
+			    SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
+	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
+	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
+			    MTYPE, MTYPE_UC);/* XXX for emulation. */
+	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
+
+	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp);
+}
+
 int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
 {
 	u32 tmp;
@@ -139,6 +160,7 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
 	mmhub_v1_0_init_pt_regs(adev);
 	mmhub_v1_0_init_gart_aperture_regs(adev);
 	mmhub_v1_0_init_system_aperture_regs(adev);
+	mmhub_v1_0_init_tlb_regs(adev);
 
 	/* Setup TLB control */
 	tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL));
-- 
2.7.4

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[PATCH 05/18] drm/amdgpu: abstract cache initialization for gfxhub/mmhub

[Huang Rui]

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 72 +++++++++++---------------
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 88 +++++++++++---------------------
 2 files changed, 62 insertions(+), 98 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index b92fa63..8212ad3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -127,6 +127,36 @@ static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)
 	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp);
 }
 
+static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
+{
+	uint32_t tmp;
+
+	/* Setup L2 cache */
+	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL));
+	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
+	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
+	/* XXX for emulation, Refer to closed source code.*/
+	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
+			    0);
+	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
+	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
+	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
+	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL), tmp);
+
+	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL2));
+	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
+	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
+	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL2), tmp);
+
+	tmp = mmVM_L2_CNTL3_DEFAULT;
+	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL3), tmp);
+
+	tmp = mmVM_L2_CNTL4_DEFAULT;
+	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
+	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
+	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL4), tmp);
+}
+
 int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
 {
 	u32 tmp;
@@ -147,47 +177,7 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
 	gfxhub_v1_0_init_gart_aperture_regs(adev);
 	gfxhub_v1_0_init_system_aperture_regs(adev);
 	gfxhub_v1_0_init_tlb_regs(adev);
-
-	/* Setup L2 cache */
-	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL));
-	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
-	tmp = REG_SET_FIELD(tmp,
-				VM_L2_CNTL,
-				ENABLE_L2_FRAGMENT_PROCESSING,
-				0);
-	tmp = REG_SET_FIELD(tmp,
-				VM_L2_CNTL,
-				L2_PDE0_CACHE_TAG_GENERATION_MODE,
-				0);/* XXX for emulation, Refer to closed source code.*/
-	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
-	tmp = REG_SET_FIELD(tmp,
-				VM_L2_CNTL,
-				CONTEXT1_IDENTITY_ACCESS_MODE,
-				1);
-	tmp = REG_SET_FIELD(tmp,
-				VM_L2_CNTL,
-				IDENTITY_MODE_FRAGMENT_SIZE,
-				0);
-	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL), tmp);
-
-	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL2));
-	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
-	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
-	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL2), tmp);
-
-	tmp = mmVM_L2_CNTL3_DEFAULT;
-	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL3), tmp);
-
-	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL4));
-	tmp = REG_SET_FIELD(tmp,
-			    VM_L2_CNTL4,
-			    VMC_TAP_PDE_REQUEST_PHYSICAL,
-			    0);
-	tmp = REG_SET_FIELD(tmp,
-			    VM_L2_CNTL4,
-			    VMC_TAP_PTE_REQUEST_PHYSICAL,
-			    0);
-	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL4), tmp);
+	gfxhub_v1_0_init_cache_regs(adev);
 
 	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL));
 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index a148d6e..c63c6a9 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -140,6 +140,36 @@ static void mmhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)
 	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp);
 }
 
+static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
+{
+	uint32_t tmp;
+
+	/* Setup L2 cache */
+	tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL));
+	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
+	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
+	/* XXX for emulation, Refer to closed source code.*/
+	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
+			    0);
+	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
+	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
+	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
+	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL), tmp);
+
+	tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL2));
+	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
+	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
+	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL2), tmp);
+
+	tmp = mmVM_L2_CNTL3_DEFAULT;
+	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL3), tmp);
+
+	tmp = mmVM_L2_CNTL4_DEFAULT;
+	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
+	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
+	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL4), tmp);
+}
+
 int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
 {
 	u32 tmp;
@@ -161,63 +191,7 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
 	mmhub_v1_0_init_gart_aperture_regs(adev);
 	mmhub_v1_0_init_system_aperture_regs(adev);
 	mmhub_v1_0_init_tlb_regs(adev);
-
-	/* Setup TLB control */
-	tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL));
-
-	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
-	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
-	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
-			    ENABLE_ADVANCED_DRIVER_MODEL, 1);
-	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
-			    SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
-	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
-	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
-			    MTYPE, MTYPE_UC);/* XXX for emulation. */
-	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
-
-	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp);
-
-	/* Setup L2 cache */
-	tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL));
-	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
-	tmp = REG_SET_FIELD(tmp,
-				VM_L2_CNTL,
-				ENABLE_L2_FRAGMENT_PROCESSING,
-				0);
-	tmp = REG_SET_FIELD(tmp,
-				VM_L2_CNTL,
-				L2_PDE0_CACHE_TAG_GENERATION_MODE,
-				0);/* XXX for emulation, Refer to closed source code.*/
-	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
-	tmp = REG_SET_FIELD(tmp,
-				VM_L2_CNTL,
-				CONTEXT1_IDENTITY_ACCESS_MODE,
-				1);
-	tmp = REG_SET_FIELD(tmp,
-				VM_L2_CNTL,
-				IDENTITY_MODE_FRAGMENT_SIZE,
-				0);
-	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL), tmp);
-
-	tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL2));
-	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
-	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
-	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL2), tmp);
-
-	tmp = mmVM_L2_CNTL3_DEFAULT;
-	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL3), tmp);
-
-	tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL4));
-	tmp = REG_SET_FIELD(tmp,
-			    VM_L2_CNTL4,
-			    VMC_TAP_PDE_REQUEST_PHYSICAL,
-			    0);
-	tmp = REG_SET_FIELD(tmp,
-			    VM_L2_CNTL4,
-			    VMC_TAP_PTE_REQUEST_PHYSICAL,
-			    0);
-	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL4), tmp);
+	mmhub_v1_0_init_cache_regs(adev);
 
 	addr = SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL);
 	tmp = RREG32(addr);
-- 
2.7.4

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[PATCH 06/18] drm/amdgpu: abstract system domain enablement for gfxhub/mmhub

[Huang Rui]

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 22 ++++++++++++++++------
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 27 ++++++++++++++++-----------
 2 files changed, 32 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index 8212ad3..fbabd11 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -157,6 +157,16 @@ static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
 	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL4), tmp);
 }
 
+static void gfxhub_v1_0_enable_system_domain(struct amdgpu_device *adev)
+{
+	uint32_t tmp;
+
+	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL));
+	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
+	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
+	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL), tmp);
+}
+
 int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
 {
 	u32 tmp;
@@ -164,8 +174,11 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
 
 	DRM_INFO("%s -- in\n", __func__);
 	if (amdgpu_sriov_vf(adev)) {
-		/* MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are VF copy registers so
-		vbios post doesn't program them, for SRIOV driver need to program them */
+		/*
+		 * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
+		 * VF copy registers so vbios post doesn't program them, for
+		 * SRIOV driver need to program them
+		 */
 		WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_BASE),
 				adev->mc.vram_start >> 24);
 		WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_TOP),
@@ -179,10 +192,7 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
 	gfxhub_v1_0_init_tlb_regs(adev);
 	gfxhub_v1_0_init_cache_regs(adev);
 
-	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL));
-	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
-	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
-	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL), tmp);
+	gfxhub_v1_0_enable_system_domain(adev);
 
 	/* Disable identity aperture.*/
 	WREG32(SOC15_REG_OFFSET(GC, 0,
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index c63c6a9..888ce7f 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -170,16 +170,28 @@ static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
 	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL4), tmp);
 }
 
+static void mmhub_v1_0_enable_system_domain(struct amdgpu_device *adev)
+{
+	uint32_t tmp;
+
+	tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL));
+	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
+	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
+	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL), tmp);
+}
+
 int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
 {
 	u32 tmp;
-	uint64_t addr;
 	u32 i;
 
 	DRM_INFO("%s -- in\n", __func__);
 	if (amdgpu_sriov_vf(adev)) {
-		/* MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are VF copy registers so
-		vbios post doesn't program them, for SRIOV driver need to program them */
+		/*
+		 * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
+		 * VF copy registers so vbios post doesn't program them, for
+		 * SRIOV driver need to program them
+		 */
 		WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE),
 			adev->mc.vram_start >> 24);
 		WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP),
@@ -193,14 +205,7 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
 	mmhub_v1_0_init_tlb_regs(adev);
 	mmhub_v1_0_init_cache_regs(adev);
 
-	addr = SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL);
-	tmp = RREG32(addr);
-
-	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
-	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
-	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL), tmp);
-
-	tmp = RREG32(addr);
+	mmhub_v1_0_enable_system_domain(adev);
 
 	/* Disable identity aperture.*/
 	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
-- 
2.7.4

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[PATCH 07/18] drm/amdgpu: abstract disable identity aperture for gfxhub/mmhub

[Huang Rui]

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 37 ++++++++++++++++++--------------
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 36 +++++++++++++++++--------------
 2 files changed, 41 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index fbabd11..5fdc9be 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -167,6 +167,26 @@ static void gfxhub_v1_0_enable_system_domain(struct amdgpu_device *adev)
 	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL), tmp);
 }
 
+static void gfxhub_v1_0_dis_identity_aperture(struct amdgpu_device *adev)
+{
+	WREG32(SOC15_REG_OFFSET(GC, 0,
+				mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32),
+	       0XFFFFFFFF);
+	WREG32(SOC15_REG_OFFSET(GC, 0,
+		mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32), 0x0000000F);
+
+	WREG32(SOC15_REG_OFFSET(GC, 0,
+		mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32), 0);
+	WREG32(SOC15_REG_OFFSET(GC, 0,
+		mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32), 0);
+
+	WREG32(SOC15_REG_OFFSET(GC, 0,
+		mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32), 0);
+	WREG32(SOC15_REG_OFFSET(GC, 0,
+		mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32), 0);
+
+}
+
 int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
 {
 	u32 tmp;
@@ -193,22 +213,7 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
 	gfxhub_v1_0_init_cache_regs(adev);
 
 	gfxhub_v1_0_enable_system_domain(adev);
-
-	/* Disable identity aperture.*/
-	WREG32(SOC15_REG_OFFSET(GC, 0,
-		mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32), 0XFFFFFFFF);
-	WREG32(SOC15_REG_OFFSET(GC, 0,
-		mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32), 0x0000000F);
-
-	WREG32(SOC15_REG_OFFSET(GC, 0,
-		mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32), 0);
-	WREG32(SOC15_REG_OFFSET(GC, 0,
-		mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32), 0);
-
-	WREG32(SOC15_REG_OFFSET(GC, 0,
-		mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32), 0);
-	WREG32(SOC15_REG_OFFSET(GC, 0,
-		mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32), 0);
+	gfxhub_v1_0_dis_identity_aperture(adev);
 
 	for (i = 0; i <= 14; i++) {
 		tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL) + i);
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index 888ce7f..84148578 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -180,6 +180,25 @@ static void mmhub_v1_0_enable_system_domain(struct amdgpu_device *adev)
 	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL), tmp);
 }
 
+static void mmhub_v1_0_dis_identity_aperture(struct amdgpu_device *adev)
+{
+	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
+				mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32),
+	       0XFFFFFFFF);
+	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
+		mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32), 0x0000000F);
+
+	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
+		mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32), 0);
+	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
+		mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32), 0);
+
+	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
+		mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32), 0);
+	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
+		mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32), 0);
+}
+
 int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
 {
 	u32 tmp;
@@ -206,22 +225,7 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
 	mmhub_v1_0_init_cache_regs(adev);
 
 	mmhub_v1_0_enable_system_domain(adev);
-
-	/* Disable identity aperture.*/
-	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
-		mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32), 0XFFFFFFFF);
-	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
-		mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32), 0x0000000F);
-
-	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
-		mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32), 0);
-	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
-		mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32), 0);
-
-	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
-		mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32), 0);
-	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
-		mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32), 0);
+	mmhub_v1_0_dis_identity_aperture(adev);
 
 	for (i = 0; i <= 14; i++) {
 		tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL)
-- 
2.7.4

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RE: [PATCH 07/18] drm/amdgpu: abstract disable identity aperture for gfxhub/mmhub

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Huang Rui
> Sent: Wednesday, May 31, 2017 12:15 PM
> To: amd-gfx@lists.freedesktop.org; Deucher, Alexander; Koenig, Christian
> Cc: Wang, Ken; Huang, Ray; Huan, Alvin
> Subject: [PATCH 07/18] drm/amdgpu: abstract disable identity aperture for
> gfxhub/mmhub
> 
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 37 ++++++++++++++++++-
> -------------
>  drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 36 +++++++++++++++++-
> -------------
>  2 files changed, 41 insertions(+), 32 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> index fbabd11..5fdc9be 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> @@ -167,6 +167,26 @@ static void
> gfxhub_v1_0_enable_system_domain(struct amdgpu_device *adev)
>  	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL),
> tmp);
>  }
> 
> +static void gfxhub_v1_0_dis_identity_aperture(struct amdgpu_device
> *adev)

Call this function gfxhub_v1_0_disable_identity_aperture() for consistency with the other newly abstracted functions.  Same for mmhub.

Alex

> +{
> +	WREG32(SOC15_REG_OFFSET(GC, 0,
> +
> 	mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32),
> +	       0XFFFFFFFF);
> +	WREG32(SOC15_REG_OFFSET(GC, 0,
> +
> 	mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32),
> 0x0000000F);
> +
> +	WREG32(SOC15_REG_OFFSET(GC, 0,
> +
> 	mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32),
> 0);
> +	WREG32(SOC15_REG_OFFSET(GC, 0,
> +
> 	mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32), 0);
> +
> +	WREG32(SOC15_REG_OFFSET(GC, 0,
> +		mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32),
> 0);
> +	WREG32(SOC15_REG_OFFSET(GC, 0,
> +		mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32),
> 0);
> +
> +}
> +
>  int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
>  {
>  	u32 tmp;
> @@ -193,22 +213,7 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device
> *adev)
>  	gfxhub_v1_0_init_cache_regs(adev);
> 
>  	gfxhub_v1_0_enable_system_domain(adev);
> -
> -	/* Disable identity aperture.*/
> -	WREG32(SOC15_REG_OFFSET(GC, 0,
> -
> 	mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32),
> 0XFFFFFFFF);
> -	WREG32(SOC15_REG_OFFSET(GC, 0,
> -
> 	mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32),
> 0x0000000F);
> -
> -	WREG32(SOC15_REG_OFFSET(GC, 0,
> -
> 	mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32),
> 0);
> -	WREG32(SOC15_REG_OFFSET(GC, 0,
> -
> 	mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32), 0);
> -
> -	WREG32(SOC15_REG_OFFSET(GC, 0,
> -		mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32),
> 0);
> -	WREG32(SOC15_REG_OFFSET(GC, 0,
> -		mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32),
> 0);
> +	gfxhub_v1_0_dis_identity_aperture(adev);
> 
>  	for (i = 0; i <= 14; i++) {
>  		tmp = RREG32(SOC15_REG_OFFSET(GC, 0,
> mmVM_CONTEXT1_CNTL) + i);
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> index 888ce7f..84148578 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> @@ -180,6 +180,25 @@ static void
> mmhub_v1_0_enable_system_domain(struct amdgpu_device *adev)
>  	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> mmVM_CONTEXT0_CNTL), tmp);
>  }
> 
> +static void mmhub_v1_0_dis_identity_aperture(struct amdgpu_device
> *adev)
> +{
> +	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> +
> 	mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32),
> +	       0XFFFFFFFF);
> +	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> +
> 	mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32),
> 0x0000000F);
> +
> +	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> +
> 	mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32),
> 0);
> +	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> +
> 	mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32), 0);
> +
> +	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> +		mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32),
> 0);
> +	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> +		mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32),
> 0);
> +}
> +
>  int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
>  {
>  	u32 tmp;
> @@ -206,22 +225,7 @@ int mmhub_v1_0_gart_enable(struct
> amdgpu_device *adev)
>  	mmhub_v1_0_init_cache_regs(adev);
> 
>  	mmhub_v1_0_enable_system_domain(adev);
> -
> -	/* Disable identity aperture.*/
> -	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> -
> 	mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32),
> 0XFFFFFFFF);
> -	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> -
> 	mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32),
> 0x0000000F);
> -
> -	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> -
> 	mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32),
> 0);
> -	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> -
> 	mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32), 0);
> -
> -	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> -		mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32),
> 0);
> -	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
> -		mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32),
> 0);
> +	mmhub_v1_0_dis_identity_aperture(adev);
> 
>  	for (i = 0; i <= 14; i++) {
>  		tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0,
> mmVM_CONTEXT1_CNTL)
> --
> 2.7.4
> 
> _______________________________________________
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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[PATCH 08/18] drm/amdgpu: abstract setup vmid config for gfxhub/mmhub

[Huang Rui]

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 55 ++++++++++++++++---------------
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 56 +++++++++++++++++---------------
 2 files changed, 59 insertions(+), 52 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index 5fdc9be..7b3447a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -187,33 +187,10 @@ static void gfxhub_v1_0_dis_identity_aperture(struct amdgpu_device *adev)
 
 }
 
-int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
+static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
 {
-	u32 tmp;
-	u32 i;
-
-	DRM_INFO("%s -- in\n", __func__);
-	if (amdgpu_sriov_vf(adev)) {
-		/*
-		 * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
-		 * VF copy registers so vbios post doesn't program them, for
-		 * SRIOV driver need to program them
-		 */
-		WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_BASE),
-				adev->mc.vram_start >> 24);
-		WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_TOP),
-				adev->mc.vram_end >> 24);
-	}
-
-	/* GART Enable. */
-	gfxhub_v1_0_init_pt_regs(adev);
-	gfxhub_v1_0_init_gart_aperture_regs(adev);
-	gfxhub_v1_0_init_system_aperture_regs(adev);
-	gfxhub_v1_0_init_tlb_regs(adev);
-	gfxhub_v1_0_init_cache_regs(adev);
-
-	gfxhub_v1_0_enable_system_domain(adev);
-	gfxhub_v1_0_dis_identity_aperture(adev);
+	int i;
+	uint32_t tmp;
 
 	for (i = 0; i <= 14; i++) {
 		tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL) + i);
@@ -248,7 +225,33 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
 		WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32) + i*2,
 			upper_32_bits(adev->vm_manager.max_pfn - 1));
 	}
+}
+
+int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
+{
+	DRM_INFO("%s -- in\n", __func__);
+	if (amdgpu_sriov_vf(adev)) {
+		/*
+		 * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
+		 * VF copy registers so vbios post doesn't program them, for
+		 * SRIOV driver need to program them
+		 */
+		WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_BASE),
+				adev->mc.vram_start >> 24);
+		WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_TOP),
+				adev->mc.vram_end >> 24);
+	}
 
+	/* GART Enable. */
+	gfxhub_v1_0_init_pt_regs(adev);
+	gfxhub_v1_0_init_gart_aperture_regs(adev);
+	gfxhub_v1_0_init_system_aperture_regs(adev);
+	gfxhub_v1_0_init_tlb_regs(adev);
+	gfxhub_v1_0_init_cache_regs(adev);
+
+	gfxhub_v1_0_enable_system_domain(adev);
+	gfxhub_v1_0_dis_identity_aperture(adev);
+	gfxhub_v1_0_setup_vmid_config(adev);
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index 84148578..536aa86 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -199,33 +199,10 @@ static void mmhub_v1_0_dis_identity_aperture(struct amdgpu_device *adev)
 		mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32), 0);
 }
 
-int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
+static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
 {
-	u32 tmp;
-	u32 i;
-
-	DRM_INFO("%s -- in\n", __func__);
-	if (amdgpu_sriov_vf(adev)) {
-		/*
-		 * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
-		 * VF copy registers so vbios post doesn't program them, for
-		 * SRIOV driver need to program them
-		 */
-		WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE),
-			adev->mc.vram_start >> 24);
-		WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP),
-			adev->mc.vram_end >> 24);
-	}
-
-	/* GART Enable. */
-	mmhub_v1_0_init_pt_regs(adev);
-	mmhub_v1_0_init_gart_aperture_regs(adev);
-	mmhub_v1_0_init_system_aperture_regs(adev);
-	mmhub_v1_0_init_tlb_regs(adev);
-	mmhub_v1_0_init_cache_regs(adev);
-
-	mmhub_v1_0_enable_system_domain(adev);
-	mmhub_v1_0_dis_identity_aperture(adev);
+	int i;
+	uint32_t tmp;
 
 	for (i = 0; i <= 14; i++) {
 		tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL)
@@ -262,6 +239,33 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
 		WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32) + i*2,
 			upper_32_bits(adev->vm_manager.max_pfn - 1));
 	}
+}
+
+int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
+{
+	DRM_INFO("%s -- in\n", __func__);
+	if (amdgpu_sriov_vf(adev)) {
+		/*
+		 * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
+		 * VF copy registers so vbios post doesn't program them, for
+		 * SRIOV driver need to program them
+		 */
+		WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE),
+			adev->mc.vram_start >> 24);
+		WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP),
+			adev->mc.vram_end >> 24);
+	}
+
+	/* GART Enable. */
+	mmhub_v1_0_init_pt_regs(adev);
+	mmhub_v1_0_init_gart_aperture_regs(adev);
+	mmhub_v1_0_init_system_aperture_regs(adev);
+	mmhub_v1_0_init_tlb_regs(adev);
+	mmhub_v1_0_init_cache_regs(adev);
+
+	mmhub_v1_0_enable_system_domain(adev);
+	mmhub_v1_0_dis_identity_aperture(adev);
+	mmhub_v1_0_setup_vmid_config(adev);
 
 	return 0;
 }
-- 
2.7.4

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[PATCH 09/18] drm/amdgpu: fix to miss program invalidation at resume

[Huang Rui]

This patch moves invalidation into gart enable function from hw_init.
Because we would like align the sequence calling between init and resume.

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 27 +++++++++++++++------------
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 27 +++++++++++++++------------
 2 files changed, 30 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index 7b3447a..da2c9b7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -227,6 +227,20 @@ static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
 	}
 }
 
+static void gfxhub_v1_0_program_invalidation(struct amdgpu_device *adev)
+{
+	unsigned i;
+
+	for (i = 0 ; i < 18; ++i) {
+		WREG32(SOC15_REG_OFFSET(GC, 0,
+					mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32) +
+		       2 * i, 0xffffffff);
+		WREG32(SOC15_REG_OFFSET(GC, 0,
+					mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32) +
+		       2 * i, 0x1f);
+	}
+}
+
 int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
 {
 	DRM_INFO("%s -- in\n", __func__);
@@ -252,6 +266,7 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
 	gfxhub_v1_0_enable_system_domain(adev);
 	gfxhub_v1_0_dis_identity_aperture(adev);
 	gfxhub_v1_0_setup_vmid_config(adev);
+	gfxhub_v1_0_program_invalidation(adev);
 
 	return 0;
 }
@@ -361,18 +376,6 @@ static int gfxhub_v1_0_sw_fini(void *handle)
 
 static int gfxhub_v1_0_hw_init(void *handle)
 {
-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-	unsigned i;
-
-	for (i = 0 ; i < 18; ++i) {
-		WREG32(SOC15_REG_OFFSET(GC, 0,
-					mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32) +
-		       2 * i, 0xffffffff);
-		WREG32(SOC15_REG_OFFSET(GC, 0,
-					mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32) +
-		       2 * i, 0x1f);
-	}
-
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index 536aa86..2f85647 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -241,6 +241,20 @@ static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
 	}
 }
 
+static void mmhub_v1_0_program_invalidation(struct amdgpu_device *adev)
+{
+	unsigned i;
+
+	for (i = 0; i < 18; ++i) {
+		WREG32(SOC15_REG_OFFSET(MMHUB, 0,
+					mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32) +
+		       2 * i, 0xffffffff);
+		WREG32(SOC15_REG_OFFSET(MMHUB, 0,
+					mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32) +
+		       2 * i, 0x1f);
+	}
+}
+
 int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
 {
 	DRM_INFO("%s -- in\n", __func__);
@@ -266,6 +280,7 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
 	mmhub_v1_0_enable_system_domain(adev);
 	mmhub_v1_0_dis_identity_aperture(adev);
 	mmhub_v1_0_setup_vmid_config(adev);
+	mmhub_v1_0_program_invalidation(adev);
 
 	return 0;
 }
@@ -374,18 +389,6 @@ static int mmhub_v1_0_sw_fini(void *handle)
 
 static int mmhub_v1_0_hw_init(void *handle)
 {
-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-	unsigned i;
-
-	for (i = 0; i < 18; ++i) {
-		WREG32(SOC15_REG_OFFSET(MMHUB, 0,
-					mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32) +
-		       2 * i, 0xffffffff);
-		WREG32(SOC15_REG_OFFSET(MMHUB, 0,
-					mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32) +
-		       2 * i, 0x1f);
-	}
-
 	return 0;
 }
 
-- 
2.7.4

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[PATCH 10/18] drm/amdgpu: export gfxhub sw_init into gmc

[Huang Rui]

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 26 ++++++++++++++------------
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h |  1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c    |  2 ++
 3 files changed, 17 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index da2c9b7..39c3b71 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -334,19 +334,8 @@ void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,
 	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL), tmp);
 }
 
-static int gfxhub_v1_0_early_init(void *handle)
-{
-	return 0;
-}
-
-static int gfxhub_v1_0_late_init(void *handle)
+void gfxhub_v1_0_init(struct amdgpu_device *adev)
 {
-	return 0;
-}
-
-static int gfxhub_v1_0_sw_init(void *handle)
-{
-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB];
 
 	hub->ctx0_ptb_addr_lo32 =
@@ -365,7 +354,20 @@ static int gfxhub_v1_0_sw_init(void *handle)
 		SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS);
 	hub->vm_l2_pro_fault_cntl =
 		SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
+}
 
+static int gfxhub_v1_0_early_init(void *handle)
+{
+	return 0;
+}
+
+static int gfxhub_v1_0_late_init(void *handle)
+{
+	return 0;
+}
+
+static int gfxhub_v1_0_sw_init(void *handle)
+{
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h
index 5129a8f..68f38d7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h
@@ -28,6 +28,7 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev);
 void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev);
 void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,
 					  bool value);
+void gfxhub_v1_0_init(struct amdgpu_device *adev);
 
 extern const struct amd_ip_funcs gfxhub_v1_0_ip_funcs;
 extern const struct amdgpu_ip_block_version gfxhub_v1_0_ip_block;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 4da150d..2fee1c6 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -551,6 +551,8 @@ static int gmc_v9_0_sw_init(void *handle)
 	int dma_bits;
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
+	gfxhub_v1_0_init(adev);
+
 	spin_lock_init(&adev->mc.invalidate_lock);
 
 	if (adev->flags & AMD_IS_APU) {
-- 
2.7.4

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[PATCH 11/18] drm/amdgpu: export mmhub sw_init into gmc

[Huang Rui]

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   |  1 +
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 27 +++++++++++++++------------
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h |  1 +
 3 files changed, 17 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 2fee1c6..077b7ce 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -552,6 +552,7 @@ static int gmc_v9_0_sw_init(void *handle)
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
 	gfxhub_v1_0_init(adev);
+	mmhub_v1_0_init(adev);
 
 	spin_lock_init(&adev->mc.invalidate_lock);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index 2f85647..20d8d2c 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -347,19 +347,8 @@ void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
 	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL), tmp);
 }
 
-static int mmhub_v1_0_early_init(void *handle)
+void mmhub_v1_0_init(struct amdgpu_device *adev)
 {
-	return 0;
-}
-
-static int mmhub_v1_0_late_init(void *handle)
-{
-	return 0;
-}
-
-static int mmhub_v1_0_sw_init(void *handle)
-{
-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB];
 
 	hub->ctx0_ptb_addr_lo32 =
@@ -379,6 +368,20 @@ static int mmhub_v1_0_sw_init(void *handle)
 	hub->vm_l2_pro_fault_cntl =
 		SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
 
+}
+
+static int mmhub_v1_0_early_init(void *handle)
+{
+	return 0;
+}
+
+static int mmhub_v1_0_late_init(void *handle)
+{
+	return 0;
+}
+
+static int mmhub_v1_0_sw_init(void *handle)
+{
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h
index aadedf9..f8a57e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h
@@ -28,6 +28,7 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev);
 void mmhub_v1_0_gart_disable(struct amdgpu_device *adev);
 void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,
 					 bool value);
+void mmhub_v1_0_init(struct amdgpu_device *adev);
 
 extern const struct amd_ip_funcs mmhub_v1_0_ip_funcs;
 extern const struct amdgpu_ip_block_version mmhub_v1_0_ip_block;
-- 
2.7.4

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Re: [PATCH 11/18] drm/amdgpu: export mmhub sw_init into gmc

[Christian König]

Am 31.05.2017 um 18:14 schrieb Huang Rui:
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   |  1 +
>   drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 27 +++++++++++++++------------
>   drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h |  1 +
>   3 files changed, 17 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 2fee1c6..077b7ce 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -552,6 +552,7 @@ static int gmc_v9_0_sw_init(void *handle)
>   	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>   
>   	gfxhub_v1_0_init(adev);
> +	mmhub_v1_0_init(adev);
>   
>   	spin_lock_init(&adev->mc.invalidate_lock);
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> index 2f85647..20d8d2c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> @@ -347,19 +347,8 @@ void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
>   	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL), tmp);
>   }
>   
> -static int mmhub_v1_0_early_init(void *handle)
> +void mmhub_v1_0_init(struct amdgpu_device *adev)
>   {
> -	return 0;
> -}
> -
> -static int mmhub_v1_0_late_init(void *handle)
> -{
> -	return 0;
> -}
> -
> -static int mmhub_v1_0_sw_init(void *handle)
> -{
> -	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>   	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB];
>   
>   	hub->ctx0_ptb_addr_lo32 =
> @@ -379,6 +368,20 @@ static int mmhub_v1_0_sw_init(void *handle)
>   	hub->vm_l2_pro_fault_cntl =
>   		SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
>   
> +}
> +
> +static int mmhub_v1_0_early_init(void *handle)
> +{
> +	return 0;
> +}
> +
> +static int mmhub_v1_0_late_init(void *handle)
> +{
> +	return 0;
> +}
> +
> +static int mmhub_v1_0_sw_init(void *handle)
> +{
>   	return 0;

Return with a value in a function returning void?

Check the compile log for warnings introduced by the patch set.

Christian.

>   }
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h
> index aadedf9..f8a57e1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h
> @@ -28,6 +28,7 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev);
>   void mmhub_v1_0_gart_disable(struct amdgpu_device *adev);
>   void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,
>   					 bool value);
> +void mmhub_v1_0_init(struct amdgpu_device *adev);
>   
>   extern const struct amd_ip_funcs mmhub_v1_0_ip_funcs;
>   extern const struct amdgpu_ip_block_version mmhub_v1_0_ip_block;


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Re: [PATCH 11/18] drm/amdgpu: export mmhub sw_init into gmc

[Huang Rui]

On Thu, Jun 01, 2017 at 01:04:52AM +0800, Koenig, Christian wrote:
> Am 31.05.2017 um 18:14 schrieb Huang Rui:
> > Signed-off-by: Huang Rui <ray.huang@amd.com>
> > ---
> >   drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   |  1 +
> >   drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 27 +++++++++++++++------------
> >   drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h |  1 +
> >   3 files changed, 17 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/
> amdgpu/gmc_v9_0.c
> > index 2fee1c6..077b7ce 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> > @@ -552,6 +552,7 @@ static int gmc_v9_0_sw_init(void *handle)
> >        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> >  
> >        gfxhub_v1_0_init(adev);
> > +     mmhub_v1_0_init(adev);
> >  
> >        spin_lock_init(&adev->mc.invalidate_lock);
> >  
> > diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/
> amdgpu/mmhub_v1_0.c
> > index 2f85647..20d8d2c 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> > @@ -347,19 +347,8 @@ void mmhub_v1_0_set_fault_enable_default(struct
> amdgpu_device *adev, bool value)
> >        WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL),
> tmp);
> >   }
> >  
> > -static int mmhub_v1_0_early_init(void *handle)
> > +void mmhub_v1_0_init(struct amdgpu_device *adev)
> >   {
> > -     return 0;
> > -}
> > -
> > -static int mmhub_v1_0_late_init(void *handle)
> > -{
> > -     return 0;
> > -}
> > -
> > -static int mmhub_v1_0_sw_init(void *handle)
> > -{
> > -     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> >        struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB];
> >  
> >        hub->ctx0_ptb_addr_lo32 =
> > @@ -379,6 +368,20 @@ static int mmhub_v1_0_sw_init(void *handle)
> >        hub->vm_l2_pro_fault_cntl =
> >                SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
> >  
> > +}
> > +
> > +static int mmhub_v1_0_early_init(void *handle)
> > +{
> > +     return 0;
> > +}
> > +
> > +static int mmhub_v1_0_late_init(void *handle)
> > +{
> > +     return 0;
> > +}
> > +
> > +static int mmhub_v1_0_sw_init(void *handle)
> > +{
> >        return 0;
> 
> Return with a value in a function returning void?
> 
> Check the compile log for warnings introduced by the patch set.
> 

The diff log doesn't show it well.
Actually, I just define new function named mmhub_v1_0_init as "void" and
its return type is also "void". And mmhub_v1_0_sw_init returning value
should be "0" here.

Yes, I checked compile log, no warning introduced.

Thanks,
Ray
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[PATCH 12/18] drm/amdgpu: export mmhub set clockgating into gmc

[Huang Rui]

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   |  4 +++-
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 12 ++++++++----
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h |  2 ++
 3 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 077b7ce..ea8ee05 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -827,7 +827,9 @@ static int gmc_v9_0_soft_reset(void *handle)
 static int gmc_v9_0_set_clockgating_state(void *handle,
 					enum amd_clockgating_state state)
 {
-	return 0;
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+	return mmhub_v1_0_set_clockgating(adev, state);
 }
 
 static int gmc_v9_0_set_powergating_state(void *handle,
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index 20d8d2c..94ad11e 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -527,11 +527,9 @@ static void athub_update_medium_grain_light_sleep(struct amdgpu_device *adev,
 		WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATHUB_MISC_CNTL), data);
 }
 
-static int mmhub_v1_0_set_clockgating_state(void *handle,
-					enum amd_clockgating_state state)
+int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev,
+			       enum amd_clockgating_state state)
 {
-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
 	if (amdgpu_sriov_vf(adev))
 		return 0;
 
@@ -553,6 +551,12 @@ static int mmhub_v1_0_set_clockgating_state(void *handle,
 	return 0;
 }
 
+static int mmhub_v1_0_set_clockgating_state(void *handle,
+					    enum amd_clockgating_state state)
+{
+	return 0;
+}
+
 static void mmhub_v1_0_get_clockgating_state(void *handle, u32 *flags)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h
index f8a57e1..d9ca985 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h
@@ -29,6 +29,8 @@ void mmhub_v1_0_gart_disable(struct amdgpu_device *adev);
 void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,
 					 bool value);
 void mmhub_v1_0_init(struct amdgpu_device *adev);
+int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev,
+			       enum amd_clockgating_state state);
 
 extern const struct amd_ip_funcs mmhub_v1_0_ip_funcs;
 extern const struct amdgpu_ip_block_version mmhub_v1_0_ip_block;
-- 
2.7.4

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[PATCH 13/18] drm/amdgpu: export mmhub get clockgating into gmc

[Huang Rui]

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   | 8 ++++++++
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 4 +---
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h | 1 +
 3 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index ea8ee05..fed00f7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -832,6 +832,13 @@ static int gmc_v9_0_set_clockgating_state(void *handle,
 	return mmhub_v1_0_set_clockgating(adev, state);
 }
 
+static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags)
+{
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+	mmhub_v1_0_get_clockgating(adev, flags);
+}
+
 static int gmc_v9_0_set_powergating_state(void *handle,
 					enum amd_powergating_state state)
 {
@@ -853,6 +860,7 @@ const struct amd_ip_funcs gmc_v9_0_ip_funcs = {
 	.soft_reset = gmc_v9_0_soft_reset,
 	.set_clockgating_state = gmc_v9_0_set_clockgating_state,
 	.set_powergating_state = gmc_v9_0_set_powergating_state,
+	.get_clockgating_state = gmc_v9_0_get_clockgating_state,
 };
 
 const struct amdgpu_ip_block_version gmc_v9_0_ip_block =
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index 94ad11e..312dcef 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -557,9 +557,8 @@ static int mmhub_v1_0_set_clockgating_state(void *handle,
 	return 0;
 }
 
-static void mmhub_v1_0_get_clockgating_state(void *handle, u32 *flags)
+void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
 {
-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 	int data;
 
 	if (amdgpu_sriov_vf(adev))
@@ -597,7 +596,6 @@ const struct amd_ip_funcs mmhub_v1_0_ip_funcs = {
 	.soft_reset = mmhub_v1_0_soft_reset,
 	.set_clockgating_state = mmhub_v1_0_set_clockgating_state,
 	.set_powergating_state = mmhub_v1_0_set_powergating_state,
-	.get_clockgating_state = mmhub_v1_0_get_clockgating_state,
 };
 
 const struct amdgpu_ip_block_version mmhub_v1_0_ip_block =
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h
index d9ca985..bbfacbc 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h
@@ -31,6 +31,7 @@ void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,
 void mmhub_v1_0_init(struct amdgpu_device *adev);
 int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev,
 			       enum amd_clockgating_state state);
+void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags);
 
 extern const struct amd_ip_funcs mmhub_v1_0_ip_funcs;
 extern const struct amdgpu_ip_block_version mmhub_v1_0_ip_block;
-- 
2.7.4

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[PATCH 14/18] drm/amdgpu: remove gfxhub ip

[Huang Rui]

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  1 -
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c   | 93 ------------------------------
 drivers/gpu/drm/amd/amdgpu/soc15.c         |  1 -
 drivers/gpu/drm/amd/include/amd_shared.h   |  1 -
 4 files changed, 96 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 20da771..f35d124 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1746,7 +1746,6 @@ static int amdgpu_sriov_reinit_early(struct amdgpu_device *adev)
 	static enum amd_ip_block_type ip_order[] = {
 		AMD_IP_BLOCK_TYPE_GMC,
 		AMD_IP_BLOCK_TYPE_COMMON,
-		AMD_IP_BLOCK_TYPE_GFXHUB,
 		AMD_IP_BLOCK_TYPE_MMHUB,
 		AMD_IP_BLOCK_TYPE_IH,
 	};
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index 39c3b71..d952277 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -355,96 +355,3 @@ void gfxhub_v1_0_init(struct amdgpu_device *adev)
 	hub->vm_l2_pro_fault_cntl =
 		SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
 }
-
-static int gfxhub_v1_0_early_init(void *handle)
-{
-	return 0;
-}
-
-static int gfxhub_v1_0_late_init(void *handle)
-{
-	return 0;
-}
-
-static int gfxhub_v1_0_sw_init(void *handle)
-{
-	return 0;
-}
-
-static int gfxhub_v1_0_sw_fini(void *handle)
-{
-	return 0;
-}
-
-static int gfxhub_v1_0_hw_init(void *handle)
-{
-	return 0;
-}
-
-static int gfxhub_v1_0_hw_fini(void *handle)
-{
-	return 0;
-}
-
-static int gfxhub_v1_0_suspend(void *handle)
-{
-	return 0;
-}
-
-static int gfxhub_v1_0_resume(void *handle)
-{
-	return 0;
-}
-
-static bool gfxhub_v1_0_is_idle(void *handle)
-{
-	return true;
-}
-
-static int gfxhub_v1_0_wait_for_idle(void *handle)
-{
-	return 0;
-}
-
-static int gfxhub_v1_0_soft_reset(void *handle)
-{
-	return 0;
-}
-
-static int gfxhub_v1_0_set_clockgating_state(void *handle,
-					  enum amd_clockgating_state state)
-{
-	return 0;
-}
-
-static int gfxhub_v1_0_set_powergating_state(void *handle,
-					  enum amd_powergating_state state)
-{
-	return 0;
-}
-
-const struct amd_ip_funcs gfxhub_v1_0_ip_funcs = {
-	.name = "gfxhub_v1_0",
-	.early_init = gfxhub_v1_0_early_init,
-	.late_init = gfxhub_v1_0_late_init,
-	.sw_init = gfxhub_v1_0_sw_init,
-	.sw_fini = gfxhub_v1_0_sw_fini,
-	.hw_init = gfxhub_v1_0_hw_init,
-	.hw_fini = gfxhub_v1_0_hw_fini,
-	.suspend = gfxhub_v1_0_suspend,
-	.resume = gfxhub_v1_0_resume,
-	.is_idle = gfxhub_v1_0_is_idle,
-	.wait_for_idle = gfxhub_v1_0_wait_for_idle,
-	.soft_reset = gfxhub_v1_0_soft_reset,
-	.set_clockgating_state = gfxhub_v1_0_set_clockgating_state,
-	.set_powergating_state = gfxhub_v1_0_set_powergating_state,
-};
-
-const struct amdgpu_ip_block_version gfxhub_v1_0_ip_block =
-{
-	.type = AMD_IP_BLOCK_TYPE_GFXHUB,
-	.major = 1,
-	.minor = 0,
-	.rev = 0,
-	.funcs = &gfxhub_v1_0_ip_funcs,
-};
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 70bd2b1..b7a4ef0 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -464,7 +464,6 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
 	switch (adev->asic_type) {
 	case CHIP_VEGA10:
 		amdgpu_ip_block_add(adev, &vega10_common_ip_block);
-		amdgpu_ip_block_add(adev, &gfxhub_v1_0_ip_block);
 		amdgpu_ip_block_add(adev, &mmhub_v1_0_ip_block);
 		amdgpu_ip_block_add(adev, &gmc_v9_0_ip_block);
 		amdgpu_ip_block_add(adev, &vega10_ih_ip_block);
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
index 1d1ac1e..a997393 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -75,7 +75,6 @@ enum amd_ip_block_type {
 	AMD_IP_BLOCK_TYPE_UVD,
 	AMD_IP_BLOCK_TYPE_VCE,
 	AMD_IP_BLOCK_TYPE_ACP,
-	AMD_IP_BLOCK_TYPE_GFXHUB,
 	AMD_IP_BLOCK_TYPE_MMHUB
 };
 
-- 
2.7.4

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[PATCH 15/18] drm/amdgpu: remove mmhub ip

[Huang Rui]

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  1 -
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c    | 93 ------------------------------
 drivers/gpu/drm/amd/amdgpu/soc15.c         |  1 -
 drivers/gpu/drm/amd/include/amd_shared.h   |  1 -
 4 files changed, 96 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index f35d124..c6debba 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1746,7 +1746,6 @@ static int amdgpu_sriov_reinit_early(struct amdgpu_device *adev)
 	static enum amd_ip_block_type ip_order[] = {
 		AMD_IP_BLOCK_TYPE_GMC,
 		AMD_IP_BLOCK_TYPE_COMMON,
-		AMD_IP_BLOCK_TYPE_MMHUB,
 		AMD_IP_BLOCK_TYPE_IH,
 	};
 
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index 312dcef..5be7e9e 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -370,61 +370,6 @@ void mmhub_v1_0_init(struct amdgpu_device *adev)
 
 }
 
-static int mmhub_v1_0_early_init(void *handle)
-{
-	return 0;
-}
-
-static int mmhub_v1_0_late_init(void *handle)
-{
-	return 0;
-}
-
-static int mmhub_v1_0_sw_init(void *handle)
-{
-	return 0;
-}
-
-static int mmhub_v1_0_sw_fini(void *handle)
-{
-	return 0;
-}
-
-static int mmhub_v1_0_hw_init(void *handle)
-{
-	return 0;
-}
-
-static int mmhub_v1_0_hw_fini(void *handle)
-{
-	return 0;
-}
-
-static int mmhub_v1_0_suspend(void *handle)
-{
-	return 0;
-}
-
-static int mmhub_v1_0_resume(void *handle)
-{
-	return 0;
-}
-
-static bool mmhub_v1_0_is_idle(void *handle)
-{
-	return true;
-}
-
-static int mmhub_v1_0_wait_for_idle(void *handle)
-{
-	return 0;
-}
-
-static int mmhub_v1_0_soft_reset(void *handle)
-{
-	return 0;
-}
-
 static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
 							bool enable)
 {
@@ -551,12 +496,6 @@ int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev,
 	return 0;
 }
 
-static int mmhub_v1_0_set_clockgating_state(void *handle,
-					    enum amd_clockgating_state state)
-{
-	return 0;
-}
-
 void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
 {
 	int data;
@@ -574,35 +513,3 @@ void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
 	if (data & ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
 		*flags |= AMD_CG_SUPPORT_MC_LS;
 }
-
-static int mmhub_v1_0_set_powergating_state(void *handle,
-					enum amd_powergating_state state)
-{
-	return 0;
-}
-
-const struct amd_ip_funcs mmhub_v1_0_ip_funcs = {
-	.name = "mmhub_v1_0",
-	.early_init = mmhub_v1_0_early_init,
-	.late_init = mmhub_v1_0_late_init,
-	.sw_init = mmhub_v1_0_sw_init,
-	.sw_fini = mmhub_v1_0_sw_fini,
-	.hw_init = mmhub_v1_0_hw_init,
-	.hw_fini = mmhub_v1_0_hw_fini,
-	.suspend = mmhub_v1_0_suspend,
-	.resume = mmhub_v1_0_resume,
-	.is_idle = mmhub_v1_0_is_idle,
-	.wait_for_idle = mmhub_v1_0_wait_for_idle,
-	.soft_reset = mmhub_v1_0_soft_reset,
-	.set_clockgating_state = mmhub_v1_0_set_clockgating_state,
-	.set_powergating_state = mmhub_v1_0_set_powergating_state,
-};
-
-const struct amdgpu_ip_block_version mmhub_v1_0_ip_block =
-{
-	.type = AMD_IP_BLOCK_TYPE_MMHUB,
-	.major = 1,
-	.minor = 0,
-	.rev = 0,
-	.funcs = &mmhub_v1_0_ip_funcs,
-};
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index b7a4ef0..5ffa4c4 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -464,7 +464,6 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
 	switch (adev->asic_type) {
 	case CHIP_VEGA10:
 		amdgpu_ip_block_add(adev, &vega10_common_ip_block);
-		amdgpu_ip_block_add(adev, &mmhub_v1_0_ip_block);
 		amdgpu_ip_block_add(adev, &gmc_v9_0_ip_block);
 		amdgpu_ip_block_add(adev, &vega10_ih_ip_block);
 		if (amdgpu_fw_load_type == 2 || amdgpu_fw_load_type == -1)
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
index a997393..f0c5e87 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -75,7 +75,6 @@ enum amd_ip_block_type {
 	AMD_IP_BLOCK_TYPE_UVD,
 	AMD_IP_BLOCK_TYPE_VCE,
 	AMD_IP_BLOCK_TYPE_ACP,
-	AMD_IP_BLOCK_TYPE_MMHUB
 };
 
 enum amd_clockgating_state {
-- 
2.7.4

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[PATCH 16/18] drm/amdgpu: add ip name print for selecting ips with ip_block_mask

[Huang Rui]

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index c6debba..08d6908 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1490,7 +1490,8 @@ static int amdgpu_early_init(struct amdgpu_device *adev)
 
 	for (i = 0; i < adev->num_ip_blocks; i++) {
 		if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
-			DRM_ERROR("disabled ip block: %d\n", i);
+			DRM_ERROR("disabled ip block: %d <%s>\n",
+				  i, adev->ip_blocks[i].version->funcs->name);
 			adev->ip_blocks[i].status.valid = false;
 		} else {
 			if (adev->ip_blocks[i].version->funcs->early_init) {
-- 
2.7.4

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[PATCH 17/18] drm/amdgpu: add ip block number prints

[Huang Rui]

User is able to follow the ip block number to write the ip_block_mask for
selecting the one which user would like to enable.

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 08d6908..18a1e8b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1368,6 +1368,9 @@ int amdgpu_ip_block_add(struct amdgpu_device *adev,
 	if (!ip_block_version)
 		return -EINVAL;
 
+	DRM_DEBUG("add ip block number %d <%s>\n", adev->num_ip_blocks,
+		  ip_block_version->funcs->name);
+
 	adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
 
 	return 0;
-- 
2.7.4

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[PATCH 18/18] drm/amdgpu: fix the gart table cleared issue for S3

[Huang Rui]

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h     | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c   | 2 ++
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c   | 2 ++
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c   | 2 ++
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   | 3 +++
 6 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 37f9869..50ed985 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -624,6 +624,7 @@ struct amdgpu_mc {
 	uint32_t                srbm_soft_reset;
 	struct amdgpu_mode_mc_save save;
 	bool			prt_warning;
+	unsigned long		stollen_size;
 	/* apertures */
 	u64					shared_aperture_start;
 	u64					shared_aperture_end;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 29c0deb..0406759 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1381,7 +1381,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
 	/* Change the size here instead of the init above so only lpfn is affected */
 	amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
 
-	r = amdgpu_bo_create(adev, 256 * 1024, PAGE_SIZE, true,
+	r = amdgpu_bo_create(adev, adev->mc.stollen_size, PAGE_SIZE, true,
 			     AMDGPU_GEM_DOMAIN_VRAM,
 			     AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
 			     AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index d576edc..540adae 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -873,6 +873,8 @@ static int gmc_v6_0_sw_init(void *handle)
 
 	adev->mc.mc_mask = 0xffffffffffULL;
 
+	adev->mc.stollen_size = 256 * 1024;
+
 	adev->need_dma32 = false;
 	dma_bits = adev->need_dma32 ? 32 : 40;
 	r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 681dda3..92e6e20 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -1060,6 +1060,8 @@ static int gmc_v7_0_sw_init(void *handle)
 	 */
 	adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
 
+	adev->mc.stollen_size = 256 * 1024;
+
 	/* set DMA mask + need_dma32 flags.
 	 * PCIE - can handle 40-bits.
 	 * IGP - can handle 40-bits
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index b5a3852..7738f4c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -1148,6 +1148,8 @@ static int gmc_v8_0_sw_init(void *handle)
 	 */
 	adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
 
+	adev->mc.stollen_size = 256 * 1024;
+
 	/* set DMA mask + need_dma32 flags.
 	 * PCIE - can handle 40-bits.
 	 * IGP - can handle 40-bits
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index fed00f7..31f4f44 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -591,6 +591,9 @@ static int gmc_v9_0_sw_init(void *handle)
 	 */
 	adev->mc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
 
+	/* it needs to reserve 8M stollen memory for vega10 */
+	adev->mc.stollen_size = 8 * 1024 * 1024;
+
 	/* set DMA mask + need_dma32 flags.
 	 * PCIE - can handle 44-bits.
 	 * IGP - can handle 44-bits
-- 
2.7.4

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RE: [PATCH 18/18] drm/amdgpu: fix the gart table cleared issue for S3

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Huang Rui
> Sent: Wednesday, May 31, 2017 12:15 PM
> To: amd-gfx@lists.freedesktop.org; Deucher, Alexander; Koenig, Christian
> Cc: Wang, Ken; Huang, Ray; Huan, Alvin
> Subject: [PATCH 18/18] drm/amdgpu: fix the gart table cleared issue for S3
> 
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h     | 1 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +-
>  drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c   | 2 ++
>  drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c   | 2 ++
>  drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c   | 2 ++
>  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   | 3 +++
>  6 files changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 37f9869..50ed985 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -624,6 +624,7 @@ struct amdgpu_mc {
>  	uint32_t                srbm_soft_reset;
>  	struct amdgpu_mode_mc_save save;
>  	bool			prt_warning;
> +	unsigned long		stollen_size;

Typo: stolen_size
With that fixed:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

>  	/* apertures */
>  	u64					shared_aperture_start;
>  	u64					shared_aperture_end;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index 29c0deb..0406759 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -1381,7 +1381,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
>  	/* Change the size here instead of the init above so only lpfn is
> affected */
>  	amdgpu_ttm_set_active_vram_size(adev, adev-
> >mc.visible_vram_size);
> 
> -	r = amdgpu_bo_create(adev, 256 * 1024, PAGE_SIZE, true,
> +	r = amdgpu_bo_create(adev, adev->mc.stollen_size, PAGE_SIZE,
> true,
>  			     AMDGPU_GEM_DOMAIN_VRAM,
>  			     AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
> |
>  			     AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> index d576edc..540adae 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> @@ -873,6 +873,8 @@ static int gmc_v6_0_sw_init(void *handle)
> 
>  	adev->mc.mc_mask = 0xffffffffffULL;
> 
> +	adev->mc.stollen_size = 256 * 1024;
> +
>  	adev->need_dma32 = false;
>  	dma_bits = adev->need_dma32 ? 32 : 40;
>  	r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> index 681dda3..92e6e20 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> @@ -1060,6 +1060,8 @@ static int gmc_v7_0_sw_init(void *handle)
>  	 */
>  	adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
> 
> +	adev->mc.stollen_size = 256 * 1024;
> +
>  	/* set DMA mask + need_dma32 flags.
>  	 * PCIE - can handle 40-bits.
>  	 * IGP - can handle 40-bits
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> index b5a3852..7738f4c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> @@ -1148,6 +1148,8 @@ static int gmc_v8_0_sw_init(void *handle)
>  	 */
>  	adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
> 
> +	adev->mc.stollen_size = 256 * 1024;
> +
>  	/* set DMA mask + need_dma32 flags.
>  	 * PCIE - can handle 40-bits.
>  	 * IGP - can handle 40-bits
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index fed00f7..31f4f44 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -591,6 +591,9 @@ static int gmc_v9_0_sw_init(void *handle)
>  	 */
>  	adev->mc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
> 
> +	/* it needs to reserve 8M stollen memory for vega10 */
> +	adev->mc.stollen_size = 8 * 1024 * 1024;
> +
>  	/* set DMA mask + need_dma32 flags.
>  	 * PCIE - can handle 44-bits.
>  	 * IGP - can handle 44-bits
> --
> 2.7.4
> 
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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Re: [PATCH 18/18] drm/amdgpu: fix the gart table cleared issue for S3

[Christian König]

[-- Attachment #1.1: Type: text/plain, Size: 5192 bytes --]

Am 31.05.2017 um 18:29 schrieb Deucher, Alexander:
> > -----Original Message-----
> > From: amd-gfx [mailto:amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org] On Behalf
> > Of Huang Rui
> > Sent: Wednesday, May 31, 2017 12:15 PM
> > To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org; Deucher, Alexander; Koenig, Christian
> > Cc: Wang, Ken; Huang, Ray; Huan, Alvin
> > Subject: [PATCH 18/18] drm/amdgpu: fix the gart table cleared issue 
> for S3
> >
> > Signed-off-by: Huang Rui <ray.huang-5C7GfCeVMHo@public.gmane.org>
> > ---
> >  drivers/gpu/drm/amd/amdgpu/amdgpu.h     | 1 +
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +-
> >  drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c   | 2 ++
> >  drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c   | 2 ++
> >  drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c   | 2 ++
> >  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   | 3 +++
> >  6 files changed, 11 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > index 37f9869..50ed985 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > @@ -624,6 +624,7 @@ struct amdgpu_mc {
> >        uint32_t                srbm_soft_reset;
> >        struct amdgpu_mode_mc_save save;
> >        bool                    prt_warning;
> > +     unsigned long           stollen_size;
>
> Typo: stolen_size
> With that fixed:
> Reviewed-by: Alex Deucher <alexander.deucher-5C7GfCeVMHo@public.gmane.org>

Additional to that this should be an uint64_t otherwise 32bit systems 
will break.

Please also add a "/* TODO: Figure out how to avoid that... */ to 
setting the size to 8MB on Vega10.

With that fixed Reviewed-by: Christian König <christian.koenig-5C7GfCeVMHo@public.gmane.org>.

>
> >        /* apertures */
> >        u64 shared_aperture_start;
> >        u64 shared_aperture_end;
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> > index 29c0deb..0406759 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> > @@ -1381,7 +1381,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
> >        /* Change the size here instead of the init above so only lpfn is
> > affected */
> >        amdgpu_ttm_set_active_vram_size(adev, adev-
> > >mc.visible_vram_size);
> >
> > -     r = amdgpu_bo_create(adev, 256 * 1024, PAGE_SIZE, true,
> > +     r = amdgpu_bo_create(adev, adev->mc.stollen_size, PAGE_SIZE,
> > true,
> >                             AMDGPU_GEM_DOMAIN_VRAM,
> > AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
> > |
> > AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> > b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> > index d576edc..540adae 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> > @@ -873,6 +873,8 @@ static int gmc_v6_0_sw_init(void *handle)
> >
> >        adev->mc.mc_mask = 0xffffffffffULL;
> >
> > +     adev->mc.stollen_size = 256 * 1024;
> > +
> >        adev->need_dma32 = false;
> >        dma_bits = adev->need_dma32 ? 32 : 40;
> >        r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> > b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> > index 681dda3..92e6e20 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> > @@ -1060,6 +1060,8 @@ static int gmc_v7_0_sw_init(void *handle)
> >         */
> >        adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
> >
> > +     adev->mc.stollen_size = 256 * 1024;
> > +
> >        /* set DMA mask + need_dma32 flags.
> >         * PCIE - can handle 40-bits.
> >         * IGP - can handle 40-bits
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> > b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> > index b5a3852..7738f4c 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> > @@ -1148,6 +1148,8 @@ static int gmc_v8_0_sw_init(void *handle)
> >         */
> >        adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
> >
> > +     adev->mc.stollen_size = 256 * 1024;
> > +
> >        /* set DMA mask + need_dma32 flags.
> >         * PCIE - can handle 40-bits.
> >         * IGP - can handle 40-bits
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> > b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> > index fed00f7..31f4f44 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> > @@ -591,6 +591,9 @@ static int gmc_v9_0_sw_init(void *handle)
> >         */
> >        adev->mc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
> >
> > +     /* it needs to reserve 8M stollen memory for vega10 */
> > +     adev->mc.stollen_size = 8 * 1024 * 1024;
> > +
> >        /* set DMA mask + need_dma32 flags.
> >         * PCIE - can handle 44-bits.
> >         * IGP - can handle 44-bits
> > --
> > 2.7.4
> >
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx



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[-- Attachment #2: Type: text/plain, Size: 154 bytes --]

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Re: [PATCH 18/18] drm/amdgpu: fix the gart table cleared issue for S3

[Huang Rui]

On Thu, Jun 01, 2017 at 12:58:02AM +0800, Koenig, Christian wrote:
> Am 31.05.2017 um 18:29 schrieb Deucher, Alexander:
> 
>     > -----Original Message-----
>     > From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
>     > Of Huang Rui
>     > Sent: Wednesday, May 31, 2017 12:15 PM
>     > To: amd-gfx@lists.freedesktop.org; Deucher, Alexander; Koenig, Christian
>     > Cc: Wang, Ken; Huang, Ray; Huan, Alvin
>     > Subject: [PATCH 18/18] drm/amdgpu: fix the gart table cleared issue for
>     S3
>     >
>     > Signed-off-by: Huang Rui <ray.huang@amd.com>
>     > ---
>     >  drivers/gpu/drm/amd/amdgpu/amdgpu.h     | 1 +
>     >  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +-
>     >  drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c   | 2 ++
>     >  drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c   | 2 ++
>     >  drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c   | 2 ++
>     >  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   | 3 +++
>     >  6 files changed, 11 insertions(+), 1 deletion(-)
>     >
>     > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>     > b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>     > index 37f9869..50ed985 100644
>     > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>     > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>     > @@ -624,6 +624,7 @@ struct amdgpu_mc {
>     >        uint32_t                srbm_soft_reset;
>     >        struct amdgpu_mode_mc_save save;
>     >        bool                    prt_warning;
>     > +     unsigned long           stollen_size;
> 
>     Typo: stolen_size
>     With that fixed:
>     Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> 
> 
> Additional to that this should be an uint64_t otherwise 32bit systems will
> break.
> 
> Please also add a "/* TODO: Figure out how to avoid that... */ to setting the
> size to 8MB on Vega10.
> 
> With that fixed Reviewed-by: Christian König <christian.koenig@amd.com>.
> 

OK, will fix that.

Thanks,
Ray
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RE: [PATCH 00/18] Vega10 S3 following up

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Huang Rui
> Sent: Wednesday, May 31, 2017 12:15 PM
> To: amd-gfx@lists.freedesktop.org; Deucher, Alexander; Koenig, Christian
> Cc: Wang, Ken; Huang, Ray; Huan, Alvin
> Subject: [PATCH 00/18] Vega10 S3 following up
> 
> Hi all,
> 
> These patches refines gfxhub/mmhub programming sequence to make
> them clear and
> readable. And actually, gfxhub + mmhub = GMCv9 for vega10, we don't need
> specific gfxhub and mmhub ip blocks, and meanwhile, they have different
> resume
> sequence during gfxhub, mmhub, and gmc. That will make thing confused
> and easily
> miss some register configrations. So remove gfxhub and mmhub ip block
> here, and
> merge them into GMC v9.
> 
> Patch 1 -> 8: refine gfxhub/mmhub programming sequence
> Patch 9: fix missed invalidation at resume
> Patch 10 -> 15: remove gfxhub/mmhub ip blocks
> Patch 16 -> 17: add prints to make ip_block mask clear.
> Patch 18: fix gart table cleared and other BOs cleared issue which blocked S3.
> 	(Extend stollen memory for VBIOS)

I'm not sure we need to break this down so fined grained, but I don't really have a strong opinion either way.  With the comments on patches 1, 2, 7, and 18 addressed, the series is:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> 
> Huang Rui (18):
>   drm/amdgpu: abstract gart table initialization for gfxhub/mmhub
>   drm/amdgpu: abstract gart aperture initialization for gfxhub/mmhub
>   drm/amdgpu: abstract system aperture initialization for gfxhub/mmhub
>   drm/amdgpu: abstract TLB initialization for gfxhub/mmhub
>   drm/amdgpu: abstract cache initialization for gfxhub/mmhub
>   drm/amdgpu: abstract system domain enablement for gfxhub/mmhub
>   drm/amdgpu: abstract disable identity aperture for gfxhub/mmhub
>   drm/amdgpu: abstract setup vmid config for gfxhub/mmhub
>   drm/amdgpu: fix to miss program invalidation at resume
>   drm/amdgpu: export gfxhub sw_init into gmc
>   drm/amdgpu: export mmhub sw_init into gmc
>   drm/amdgpu: export mmhub set clockgating into gmc
>   drm/amdgpu: export mmhub get clockgating into gmc
>   drm/amdgpu: remove gfxhub ip
>   drm/amdgpu: remove mmhub ip
>   drm/amdgpu: add ip name print for selecting ips with ip_block_mask
>   drm/amdgpu: add ip block number prints
>   drm/amdgpu: fix the gart table cleared issue for S3
> 
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h        |   1 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |   8 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c    |   2 +-
>  drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c   | 361 +++++++++++---------
> --------
>  drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h   |   1 +
>  drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c      |   2 +
>  drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c      |   2 +
>  drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c      |   2 +
>  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c      |  18 +-
>  drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c    | 373 ++++++++++++------
> -----------
>  drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h    |   4 +
>  drivers/gpu/drm/amd/amdgpu/soc15.c         |   2 -
>  drivers/gpu/drm/amd/include/amd_shared.h   |   2 -
>  13 files changed, 330 insertions(+), 448 deletions(-)
> 
> --
> 2.7.4
> 
> _______________________________________________
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> amd-gfx@lists.freedesktop.org
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RE: [PATCH 00/18] Vega10 S3 following up

[Zhang, Hawking]

I would suggest to use RREG32_SOC15/ WREG32_SOC15 to avoid code refactor again...

Regards,
Hawking

-----Original Message-----
From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf Of Huang Rui
Sent: Thursday, June 01, 2017 0:15
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander <Alexander.Deucher@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>
Cc: Wang, Ken <Ken.Wang@amd.com>; Huang, Ray <Ray.Huang@amd.com>; Huan, Alvin <Alvin.Huan@amd.com>
Subject: [PATCH 00/18] Vega10 S3 following up

Hi all,

These patches refines gfxhub/mmhub programming sequence to make them clear and readable. And actually, gfxhub + mmhub = GMCv9 for vega10, we don't need specific gfxhub and mmhub ip blocks, and meanwhile, they have different resume sequence during gfxhub, mmhub, and gmc. That will make thing confused and easily miss some register configrations. So remove gfxhub and mmhub ip block here, and merge them into GMC v9.

Patch 1 -> 8: refine gfxhub/mmhub programming sequence Patch 9: fix missed invalidation at resume Patch 10 -> 15: remove gfxhub/mmhub ip blocks Patch 16 -> 17: add prints to make ip_block mask clear.
Patch 18: fix gart table cleared and other BOs cleared issue which blocked S3.
	(Extend stollen memory for VBIOS)

Huang Rui (18):
  drm/amdgpu: abstract gart table initialization for gfxhub/mmhub
  drm/amdgpu: abstract gart aperture initialization for gfxhub/mmhub
  drm/amdgpu: abstract system aperture initialization for gfxhub/mmhub
  drm/amdgpu: abstract TLB initialization for gfxhub/mmhub
  drm/amdgpu: abstract cache initialization for gfxhub/mmhub
  drm/amdgpu: abstract system domain enablement for gfxhub/mmhub
  drm/amdgpu: abstract disable identity aperture for gfxhub/mmhub
  drm/amdgpu: abstract setup vmid config for gfxhub/mmhub
  drm/amdgpu: fix to miss program invalidation at resume
  drm/amdgpu: export gfxhub sw_init into gmc
  drm/amdgpu: export mmhub sw_init into gmc
  drm/amdgpu: export mmhub set clockgating into gmc
  drm/amdgpu: export mmhub get clockgating into gmc
  drm/amdgpu: remove gfxhub ip
  drm/amdgpu: remove mmhub ip
  drm/amdgpu: add ip name print for selecting ips with ip_block_mask
  drm/amdgpu: add ip block number prints
  drm/amdgpu: fix the gart table cleared issue for S3

 drivers/gpu/drm/amd/amdgpu/amdgpu.h        |   1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |   8 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c    |   2 +-
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c   | 361 +++++++++++-----------------
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h   |   1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c      |   2 +
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c      |   2 +
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c      |   2 +
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c      |  18 +-
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c    | 373 ++++++++++++-----------------
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h    |   4 +
 drivers/gpu/drm/amd/amdgpu/soc15.c         |   2 -
 drivers/gpu/drm/amd/include/amd_shared.h   |   2 -
 13 files changed, 330 insertions(+), 448 deletions(-)

--
2.7.4

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Re: [PATCH 00/18] Vega10 S3 following up

[Huang Rui]

On Thu, Jun 01, 2017 at 01:00:16AM +0800, Zhang, Hawking wrote:
> I would suggest to use RREG32_SOC15/ WREG32_SOC15 to avoid code refactor
> again...
> 

Right. Thanks to reminder. Will update it in next version.

Thanks,
Ray
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