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From: Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>
To: Nate Watterson <nwatters-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
Cc: iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH] iommu/arm-smmu-v3: Implement shutdown method
Date: Thu, 29 Jun 2017 19:34:39 +0100	[thread overview]
Message-ID: <20170629183438.GF5592@arm.com> (raw)
In-Reply-To: <1498758015-7072-1-git-send-email-nwatters-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>

On Thu, Jun 29, 2017 at 01:40:15PM -0400, Nate Watterson wrote:
> The shutdown method disables the SMMU and its interrupts to avoid
> potentially corrupting a new kernel started with kexec.
> 
> Signed-off-by: Nate Watterson <nwatters-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> ---
>  drivers/iommu/arm-smmu-v3.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)

We should update arm-smmu.c as well.

> diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
> index 380969a..907d576 100644
> --- a/drivers/iommu/arm-smmu-v3.c
> +++ b/drivers/iommu/arm-smmu-v3.c
> @@ -2765,9 +2765,19 @@ static int arm_smmu_device_remove(struct platform_device *pdev)
>  	struct arm_smmu_device *smmu = platform_get_drvdata(pdev);
>  
>  	arm_smmu_device_disable(smmu);
> +
> +	/* Disable IRQs */
> +	arm_smmu_write_reg_sync(smmu, 0, ARM_SMMU_IRQ_CTRL,
> +				ARM_SMMU_IRQ_CTRLACK);
> +

Can you justify the need for this? If we actually need to disable
interrupts, then I'd like to understand why so that we can make sure we
get the ordering right with respect to disabling the device. Also, do we
need to clear the MSI registers too?

My understanding is that kexec will mask irqs at the GIC, so there's not
actually an issue here.

Will

WARNING: multiple messages have this Message-ID (diff)
From: will.deacon@arm.com (Will Deacon)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] iommu/arm-smmu-v3: Implement shutdown method
Date: Thu, 29 Jun 2017 19:34:39 +0100	[thread overview]
Message-ID: <20170629183438.GF5592@arm.com> (raw)
In-Reply-To: <1498758015-7072-1-git-send-email-nwatters@codeaurora.org>

On Thu, Jun 29, 2017 at 01:40:15PM -0400, Nate Watterson wrote:
> The shutdown method disables the SMMU and its interrupts to avoid
> potentially corrupting a new kernel started with kexec.
> 
> Signed-off-by: Nate Watterson <nwatters@codeaurora.org>
> ---
>  drivers/iommu/arm-smmu-v3.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)

We should update arm-smmu.c as well.

> diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
> index 380969a..907d576 100644
> --- a/drivers/iommu/arm-smmu-v3.c
> +++ b/drivers/iommu/arm-smmu-v3.c
> @@ -2765,9 +2765,19 @@ static int arm_smmu_device_remove(struct platform_device *pdev)
>  	struct arm_smmu_device *smmu = platform_get_drvdata(pdev);
>  
>  	arm_smmu_device_disable(smmu);
> +
> +	/* Disable IRQs */
> +	arm_smmu_write_reg_sync(smmu, 0, ARM_SMMU_IRQ_CTRL,
> +				ARM_SMMU_IRQ_CTRLACK);
> +

Can you justify the need for this? If we actually need to disable
interrupts, then I'd like to understand why so that we can make sure we
get the ordering right with respect to disabling the device. Also, do we
need to clear the MSI registers too?

My understanding is that kexec will mask irqs at the GIC, so there's not
actually an issue here.

Will

WARNING: multiple messages have this Message-ID (diff)
From: Will Deacon <will.deacon@arm.com>
To: Nate Watterson <nwatters@codeaurora.org>
Cc: Robin Murphy <robin.murphy@arm.com>,
	Joerg Roedel <joro@8bytes.org>,
	linux-arm-kernel@lists.infradead.org,
	iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] iommu/arm-smmu-v3: Implement shutdown method
Date: Thu, 29 Jun 2017 19:34:39 +0100	[thread overview]
Message-ID: <20170629183438.GF5592@arm.com> (raw)
In-Reply-To: <1498758015-7072-1-git-send-email-nwatters@codeaurora.org>

On Thu, Jun 29, 2017 at 01:40:15PM -0400, Nate Watterson wrote:
> The shutdown method disables the SMMU and its interrupts to avoid
> potentially corrupting a new kernel started with kexec.
> 
> Signed-off-by: Nate Watterson <nwatters@codeaurora.org>
> ---
>  drivers/iommu/arm-smmu-v3.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)

We should update arm-smmu.c as well.

> diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
> index 380969a..907d576 100644
> --- a/drivers/iommu/arm-smmu-v3.c
> +++ b/drivers/iommu/arm-smmu-v3.c
> @@ -2765,9 +2765,19 @@ static int arm_smmu_device_remove(struct platform_device *pdev)
>  	struct arm_smmu_device *smmu = platform_get_drvdata(pdev);
>  
>  	arm_smmu_device_disable(smmu);
> +
> +	/* Disable IRQs */
> +	arm_smmu_write_reg_sync(smmu, 0, ARM_SMMU_IRQ_CTRL,
> +				ARM_SMMU_IRQ_CTRLACK);
> +

Can you justify the need for this? If we actually need to disable
interrupts, then I'd like to understand why so that we can make sure we
get the ordering right with respect to disabling the device. Also, do we
need to clear the MSI registers too?

My understanding is that kexec will mask irqs at the GIC, so there's not
actually an issue here.

Will

  parent reply	other threads:[~2017-06-29 18:34 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-06-29 17:40 [PATCH] iommu/arm-smmu-v3: Implement shutdown method Nate Watterson
2017-06-29 17:40 ` Nate Watterson
2017-06-29 17:40 ` Nate Watterson
     [not found] ` <1498758015-7072-1-git-send-email-nwatters-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-06-29 18:34   ` Will Deacon [this message]
2017-06-29 18:34     ` Will Deacon
2017-06-29 18:34     ` Will Deacon
     [not found]     ` <20170629183438.GF5592-5wv7dgnIgG8@public.gmane.org>
2017-06-29 22:20       ` Nate Watterson
2017-06-29 22:20         ` Nate Watterson
2017-06-29 22:20         ` Nate Watterson
     [not found]         ` <5f655f54-a843-af16-e9e3-0e0d84565994-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-06-30 17:11           ` Will Deacon
2017-06-30 17:11             ` Will Deacon
2017-06-30 17:11             ` Will Deacon

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