From: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
To: Scott Branden <scott.branden-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Frank Rowand
<frowand.list-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org,
Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Srinath Mannam
<srinath.mannam-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>,
Bjorn Helgaas <bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>,
bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w@public.gmane.org
Subject: Re: [RFC PATCH 1/2] dt-bindings: pci: Add drop mask property for MSI and IOMMU
Date: Fri, 7 Jul 2017 16:47:30 +0100 [thread overview]
Message-ID: <20170707154729.GE3425@leverpostej> (raw)
In-Reply-To: <a66fac9a-b8f7-489e-a32a-ab2100c89653-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
On Fri, Jul 07, 2017 at 08:22:21AM -0700, Scott Branden wrote:
> On 17-07-07 07:55 AM, Robin Murphy wrote:
> >On 07/07/17 14:30, Mark Rutland wrote:
> >>On Fri, Jul 07, 2017 at 12:39:58PM +0530, Srinath Mannam wrote:
> >>>+Example (6)
> >>>+===========
> >>>+
> >>>+/ {
> >>>+ #address-cells = <1>;
> >>>+ #size-cells = <1>;
> >>>+
> >>>+ msi: msi-controller@a {
> >>>+ reg = <0xa 0x1>;
> >>>+ compatible = "vendor,some-controller";
> >>>+ msi-controller;
> >>>+ #msi-cells = <1>;
> >>>+ };
> >>>+
> >>>+ pci: pci@f {
> >>>+ reg = <0xf 0x1>;
> >>>+ compatible = "vendor,pcie-root-complex";
> >>>+ device_type = "pci";
> >>>+
> >>>+ /*
> >>>+ * The sideband data provided to the MSI controller is
> >>>+ * a 10bit data derived from the RID by dropping
> >>>+ * 4 MSBs of device number and 2 MSBs of function number.
> >>>+ */
> >>>+ msi-map = <0x0 &msi_a 0x0 0x100>,
> >>>+ msi-map-drop-mask = <0xff09>
> >>>+ };
> >>>+};
> >>... likewise on all counts.
> >>
> >>Your mapping can be expressed today using a number of msi-map entries,
> >>which you can easily generate programmatically with a trivial perl
> >>script, without requiring a new binding or any new kernel code.
> >>
> >>Please do that instead.
> >
> >Indeed. The systems I'm aware of which need to express non-trivial RID
> >to SID mappings tend to have the bootloader probe PCI and dynamically
> >generate map entries per discovered RID, but even if you wanted to
> >statically generate the whole lot for the worst-case bus range that's
> >still only 512 entries, which is not unmanageable. Notably, it's also
> >what would have to be done (in equivalent) for IORT, although I assume
> >this is an embedded platform for which nobody cares about ACPI.
>
> Actually we will care about ACPI and need to add it (doesn't need to
> be in this patchet unless easy to do so...)
Similarly to what I said for the DT case, with IORT you can solve this
today by using multiple ID mapping entries in a node's ID mappings
array.
I don't imagine the sort of change you are proposing will sail into the
IORT spec.
Thanks,
Mark.
WARNING: multiple messages have this Message-ID (diff)
From: Mark Rutland <mark.rutland@arm.com>
To: Scott Branden <scott.branden@broadcom.com>
Cc: Robin Murphy <robin.murphy@arm.com>,
Srinath Mannam <srinath.mannam@broadcom.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
iommu@lists.linux-foundation.org,
Rob Herring <robh+dt@kernel.org>,
bcm-kernel-feedback-list@broadcom.com,
Bjorn Helgaas <bhelgaas@google.com>,
Frank Rowand <frowand.list@gmail.com>
Subject: Re: [RFC PATCH 1/2] dt-bindings: pci: Add drop mask property for MSI and IOMMU
Date: Fri, 7 Jul 2017 16:47:30 +0100 [thread overview]
Message-ID: <20170707154729.GE3425@leverpostej> (raw)
In-Reply-To: <a66fac9a-b8f7-489e-a32a-ab2100c89653@broadcom.com>
On Fri, Jul 07, 2017 at 08:22:21AM -0700, Scott Branden wrote:
> On 17-07-07 07:55 AM, Robin Murphy wrote:
> >On 07/07/17 14:30, Mark Rutland wrote:
> >>On Fri, Jul 07, 2017 at 12:39:58PM +0530, Srinath Mannam wrote:
> >>>+Example (6)
> >>>+===========
> >>>+
> >>>+/ {
> >>>+ #address-cells = <1>;
> >>>+ #size-cells = <1>;
> >>>+
> >>>+ msi: msi-controller@a {
> >>>+ reg = <0xa 0x1>;
> >>>+ compatible = "vendor,some-controller";
> >>>+ msi-controller;
> >>>+ #msi-cells = <1>;
> >>>+ };
> >>>+
> >>>+ pci: pci@f {
> >>>+ reg = <0xf 0x1>;
> >>>+ compatible = "vendor,pcie-root-complex";
> >>>+ device_type = "pci";
> >>>+
> >>>+ /*
> >>>+ * The sideband data provided to the MSI controller is
> >>>+ * a 10bit data derived from the RID by dropping
> >>>+ * 4 MSBs of device number and 2 MSBs of function number.
> >>>+ */
> >>>+ msi-map = <0x0 &msi_a 0x0 0x100>,
> >>>+ msi-map-drop-mask = <0xff09>
> >>>+ };
> >>>+};
> >>... likewise on all counts.
> >>
> >>Your mapping can be expressed today using a number of msi-map entries,
> >>which you can easily generate programmatically with a trivial perl
> >>script, without requiring a new binding or any new kernel code.
> >>
> >>Please do that instead.
> >
> >Indeed. The systems I'm aware of which need to express non-trivial RID
> >to SID mappings tend to have the bootloader probe PCI and dynamically
> >generate map entries per discovered RID, but even if you wanted to
> >statically generate the whole lot for the worst-case bus range that's
> >still only 512 entries, which is not unmanageable. Notably, it's also
> >what would have to be done (in equivalent) for IORT, although I assume
> >this is an embedded platform for which nobody cares about ACPI.
>
> Actually we will care about ACPI and need to add it (doesn't need to
> be in this patchet unless easy to do so...)
Similarly to what I said for the DT case, with IORT you can solve this
today by using multiple ID mapping entries in a node's ID mappings
array.
I don't imagine the sort of change you are proposing will sail into the
IORT spec.
Thanks,
Mark.
next prev parent reply other threads:[~2017-07-07 15:47 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-07-07 7:09 [RFC PATCH 0/2] Add sideband data extraction Srinath Mannam
2017-07-07 7:09 ` Srinath Mannam
2017-07-07 7:09 ` [RFC PATCH 1/2] dt-bindings: pci: Add drop mask property for MSI and IOMMU Srinath Mannam
[not found] ` <1499411399-25103-2-git-send-email-srinath.mannam-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
2017-07-07 13:30 ` Mark Rutland
2017-07-07 13:30 ` Mark Rutland
2017-07-07 14:55 ` Robin Murphy
2017-07-07 14:55 ` Robin Murphy
2017-07-07 15:22 ` Scott Branden
[not found] ` <a66fac9a-b8f7-489e-a32a-ab2100c89653-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
2017-07-07 15:42 ` Robin Murphy
2017-07-07 15:42 ` Robin Murphy
2017-07-07 15:47 ` Mark Rutland [this message]
2017-07-07 15:47 ` Mark Rutland
2017-07-07 7:09 ` [RFC PATCH 2/2] pcie: sideband data by dropping RID bits Srinath Mannam
[not found] ` <1499411399-25103-3-git-send-email-srinath.mannam-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
2017-07-07 13:33 ` Mark Rutland
2017-07-07 13:33 ` Mark Rutland
[not found] ` <1499411399-25103-1-git-send-email-srinath.mannam-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
2017-07-07 13:21 ` [RFC PATCH 0/2] Add sideband data extraction Mark Rutland
2017-07-07 13:21 ` Mark Rutland
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