From: shawnguo@kernel.org (Shawn Guo)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] ARM: dts: imx: Correct B850v3 clock assignment
Date: Wed, 12 Jul 2017 16:31:10 +0800 [thread overview]
Message-ID: <20170712083109.GK3172@dragon> (raw)
In-Reply-To: <20170630134337.18245-1-romain.perier@collabora.com>
On Fri, Jun 30, 2017 at 03:43:37PM +0200, Romain Perier wrote:
> From: Martyn Welch <martyn.welch@collabora.co.uk>
>
> The IPU that drives HDMI must have its pre_sel set to pll2_pfd_396m
> to avoid stepping on the LVDS output's toes, as the PLL can't be clocked
> to the pixel clock and to the LVDS serial clock (3.5*pixel clock) at the
> same time.
>
> As we are using ipu1_di0 and ipu2_di0, ensure both are switched to
> to pll2_pfd2_396m to avoid issues. The LDB driver will switch the
> required IPU to ldb_di1 when it uses it to drive LVDS.
>
> Signed-off-by: Martyn Welch <martyn.welch@collabora.co.uk>
> Signed-off-by: Romain Perier <romain.perier@collabora.com>
Applied, thanks.
WARNING: multiple messages have this Message-ID (diff)
From: Shawn Guo <shawnguo@kernel.org>
To: Romain Perier <romain.perier@collabora.com>
Cc: Sascha Hauer <kernel@pengutronix.de>,
Fabio Estevam <fabio.estevam@nxp.com>,
devicetree@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
Ian Campbell <ijc+devicetree@hellion.org.uk>,
Pawel Moll <pawel.moll@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Kumar Gala <galak@codeaurora.org>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Martyn Welch <martyn.welch@collabora.co.uk>
Subject: Re: [PATCH] ARM: dts: imx: Correct B850v3 clock assignment
Date: Wed, 12 Jul 2017 16:31:10 +0800 [thread overview]
Message-ID: <20170712083109.GK3172@dragon> (raw)
In-Reply-To: <20170630134337.18245-1-romain.perier@collabora.com>
On Fri, Jun 30, 2017 at 03:43:37PM +0200, Romain Perier wrote:
> From: Martyn Welch <martyn.welch@collabora.co.uk>
>
> The IPU that drives HDMI must have its pre_sel set to pll2_pfd_396m
> to avoid stepping on the LVDS output's toes, as the PLL can't be clocked
> to the pixel clock and to the LVDS serial clock (3.5*pixel clock) at the
> same time.
>
> As we are using ipu1_di0 and ipu2_di0, ensure both are switched to
> to pll2_pfd2_396m to avoid issues. The LDB driver will switch the
> required IPU to ldb_di1 when it uses it to drive LVDS.
>
> Signed-off-by: Martyn Welch <martyn.welch@collabora.co.uk>
> Signed-off-by: Romain Perier <romain.perier@collabora.com>
Applied, thanks.
next prev parent reply other threads:[~2017-07-12 8:31 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-30 13:43 [PATCH] ARM: dts: imx: Correct B850v3 clock assignment Romain Perier
2017-06-30 13:43 ` Romain Perier
2017-06-30 13:43 ` Romain Perier
2017-07-02 13:43 ` Fabio Estevam
2017-07-02 13:43 ` Fabio Estevam
2017-07-02 13:43 ` Fabio Estevam
2017-07-12 8:31 ` Shawn Guo [this message]
2017-07-12 8:31 ` Shawn Guo
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