From: Stephen Boyd <sboyd@codeaurora.org>
To: Marek Vasut <marek.vasut@gmail.com>
Cc: linux-clk@vger.kernel.org,
Marek Vasut <marek.vasut+renesas@gmail.com>,
Alexey Firago <alexey_firago@mentor.com>,
Michael Turquette <mturquette@baylibre.com>,
Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
linux-renesas-soc@vger.kernel.org
Subject: Re: [PATCH V3 8/8] clk: vc5: Add support for IDT VersaClock 5P49V6901
Date: Wed, 12 Jul 2017 16:10:34 -0700 [thread overview]
Message-ID: <20170712231034.GN22780@codeaurora.org> (raw)
In-Reply-To: <20170709132814.2339-8-marek.vasut+renesas@gmail.com>
On 07/09, Marek Vasut wrote:
> Update IDT VersaClock 5 driver to support IDT VersaClock 6 5P49V6901.
> This chip has two clock inputs (external XTAL or external CLKIN), four
> fractional dividers (FODs) and five clock outputs (four universal clock
> outputs and one reference clock output at OUT0_SELB_I2C).
>
> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
> Cc: Alexey Firago <alexey_firago@mentor.com>
> Cc: Stephen Boyd <sboyd@codeaurora.org>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Cc: linux-renesas-soc@vger.kernel.org
> Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> on Salvator-XS with the display LVDS output.
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2017-07-12 23:10 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-07-09 13:28 [PATCH V3 1/8] clk: vc5: Prevent division by zero on unconfigured outputs Marek Vasut
2017-07-09 13:28 ` [PATCH V3 2/8] clk: vc5: Fix trivial typo Marek Vasut
2017-07-12 23:10 ` Stephen Boyd
2017-07-09 13:28 ` [PATCH V3 3/8] clk: vc5: Do not warn about disabled output buffer input muxes Marek Vasut
2017-07-12 23:10 ` Stephen Boyd
2017-07-09 13:28 ` [PATCH V3 4/8] clk: vc5: Configure the output buffer input mux on prepare Marek Vasut
2017-07-12 23:10 ` Stephen Boyd
2017-07-09 13:28 ` [PATCH V3 5/8] clk: vc5: Split clock input mux and predivider Marek Vasut
2017-07-12 23:10 ` Stephen Boyd
2017-07-09 13:28 ` [PATCH V3 6/8] clk: vc5: Add support for the input frequency doubler Marek Vasut
2017-07-12 23:10 ` Stephen Boyd
2017-07-09 13:28 ` [PATCH V3 7/8] clk: vc5: Add bindings for IDT VersaClock 5P49V6901 Marek Vasut
2017-07-09 13:28 ` Marek Vasut
2017-07-12 23:10 ` Stephen Boyd
2017-07-09 13:28 ` [PATCH V3 8/8] clk: vc5: Add support " Marek Vasut
2017-07-12 23:10 ` Stephen Boyd [this message]
2017-07-12 23:10 ` [PATCH V3 1/8] clk: vc5: Prevent division by zero on unconfigured outputs Stephen Boyd
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